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《电子产品世界》2006,(9X):45-46
安华高科技(Avago Technologies)推出两款采用扩展型SSO(Stretched Small Outline)封装的新型门驱动光电耦合器,主要适用干家用电器和工业应用领域的交流和直流无刷电机。ACPL—W302和ACPL—W314光电耦合器的封装尺寸据称比传统的双列直插式封装要小50%,同时产品外形更薄。这些光电耦合器可以实现长达8mm的耙电距离和电气间隙,符合IEC、UL和CSA对增强安全和绝缘调节的要求。ACPL—W302是一款峰值电流为0.4A的隔离门驱动光电耦合器,而ACPL—W314N是一款峰值电流为0.6A的隔离门驱动光电耦合器。这两款产品在1000V的共模电压(VCM)下皆实现了15kV/us的最小共模瞬变免疫性, 相似文献
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本文详细介绍了一种带电机方向控制信号的隔离型单极PWM功率放大器的设计原理和实现方法,通过优化栅极驱动电路以减小电路震荡、提高电路效率,通过设计信号、电源三端隔离电路,有效地增强了电路的抗干扰能力和可靠性,本文将重点阐述该种PWM功率放大器的关键技术及其解决方案。 相似文献
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设计一个脉宽调制(Pulsewidthmodulates,PWM)控制器的雷达伺服直流控制系统,对整个控制系统的方案背景及模型的建立进行了分析、介绍。该设计对PWM控制器中的脉宽调制电路、隔离驱动电路、功率驱动电路、保护电路等各主要电路分别进行原理或功能上的描述,同时对雷达伺服直流控制系统总体设计及其中的电磁兼容性问题也进行详细的讨论。实验表明,该设计具有较好的动、静态性能,可广泛用于各型雷达伺服直流控制系统中。 相似文献
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基于IR2136的无刷直流电机驱动电路的设计 总被引:1,自引:0,他引:1
实现了一个基于IR2136的适用于无刷直流电机的三相全桥驱动电路的设计。详细介绍了电路的信号隔离模块、逻辑综合电路、三相逆变驱动电路和过流保护电路,并对电路中的关键参数进行了计算分析和选择,最后通过Saber仿真分析软件对设计完成的电路进行了仿真。仿真分析结果证明,电路的设计性能完全满足使用要求。 相似文献
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Yagishita A. Saito T. Nakajima K. Inumiya S. Akasaka Y. Ozawa Y. Hieda K. Tsunashima Y. Suguro K. Arikado T. Okumura K. 《Electron Devices, IEEE Transactions on》2000,47(5):1028-1034
A novel transistor formation process (damascene gate process) was developed in order to apply metal gates and high dielectric constant gate insulators to MOSFET fabrication and minimize plasma damage to gate insulators. In this process, the gate insulators and gate electrodes are formed after ion implantation and high temperature annealing (~1000°C) for source/drain formation, and the gate electrodes are fabricated by chemical mechanical polishing (CMP) of gate materials deposited in grooves. Metal gates and high dielectric constant gate insulators are applicable to the MOSFET, since the processing temperature after gate formation can be reduced to as low as 450°C. Furthermore, process-damages on gate insulators are minimized because there is no plasma damage caused by source/drain ion implantation and gate reactive ion etching (RIE). By using this process, fully planarized metal (W/TiN or Al/TiN) gate transistors with SiO2 or Ta2O5 as gate insulators were uniformly fabricated on an 8-in wafer. Further, the damascene metal gate transistors exhibited low gate sheet resistivity, no gate depletion and drastic improvement in gate oxide integrity, resulting in high transistor performance 相似文献
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In this paper, dependences of electric field strength around gate-edge in gate dielectrics of MISFETs with high-k gate dielectrics on design parameters are studied. It is newly found that locations of sidewall/gate dielectric interfaces relative to gate electrode edges are critical to electric field strength of high-k MISFETs. Electric field can be as high as 4 MV/cm, which could have large influences on the yield of large scale integrated circuits (LSIs) with high-k gate dielectrics. An explanation of this phenomenon is given by considering discontinuity in electric field at interfaces between two materials with different dielectric constants. It is clarified that an electrical potential of side and top surfaces of gate dielectrics is strongly affected by the discontinuity of electric field strength at interfaces. As a result, electric field strength around gate electrode edges critically depends on locations of sidewall/gate dielectrics interfaces relative to gate electrode edges. Based on the physical considerations, a structure, in which gate sidewalls are also made of high-k materials, is studied from the viewpoint of electric field strength around gate electrode edges. It is shown that this structure effectively suppresses electric field strength around gate edges. 相似文献
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利用磁控溅射的方法在p- Si上制备了高k(高介电常数)栅介质Hf O2薄膜的MOS电容,对薄栅氧化层电容的软击穿和硬击穿特性进行了实验研究.利用在栅极加恒电流应力的方法研究了不同面积Hf O2 薄栅介质的击穿特性以及击穿对栅介质的I- V特性和C- V特性的影响.实验结果表明薄栅介质的击穿过程中有很明显的软击穿现象发生,与栅氧化层面积有很大的关系,面积大的电容比较容易发生击穿.分析比较了软击穿和硬击穿的区别,并利用统计分析模型对薄栅介质的击穿机理进行了解释 相似文献
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Novel analytical models for subthreshold current and subthreshold slope of a generic underlap DGMOSFET are proposed. The proposed models are validated with published models, experimental data along with numerical simulation results. The reasonably good agreement shows the accuracy of the proposed model. It is demonstrated how device subthreshold leakage current and subthreshold slope values can be favorably affected by proper back gate biasing, back gate asymmetry and gate work function engineering in combination with gate underlap engineering. It is demonstrated that independent gate operation in combination with gate underlap engineering significantly reduce subthreshold leakage currents as compared to nonunderlap-tied gate DGMOSFET. With the reduction in body thickness, an improvement in subthreshold slope value of underlap 4T DGMOSFET is seen, particularly as back/front gate oxide asymmetry. Developed models demonstrate that asymmetric work function underlap 4T DGMOSFETs would have better device subthreshold slope value along with increased back gate oxide asymmetry. 相似文献
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Expressions for the spectral densities of the gate/source and gate/drain noise currents caused by current flow through the gate oxide of MOSFETs are derived. It is shown that these noise currents can also be expressed in terms of equivalent gate and drain noise currents, and by linearizing the position dependence of the gate current density, simple analytic expressions for these equivalent noise currents and their correlation are obtained in terms of the total gate current and the drain/source partition ratio. It is also shown that the predictions of this simple theory are consistent with published experimental data and results from numerical simulations. 相似文献
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以等效氧化层厚度(EOT)同为2.1nm的纯SiO2栅介质和Si3N4/SiO2叠层栅介质为例,给出了恒定电压应力下超薄栅介质寿命预测的一般方法,并在此基础上比较了纯SiO2栅介质和Si3N4/SiO2叠层栅介质在恒压应力下的寿命.结果表明,Si3N4/SiO2叠层栅介质比同样EOT的纯SiO2栅介质有更长的寿命,这说明Si3N4/SiO2叠层栅介质有更高的可靠性. 相似文献
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研究 LDMOS在一次雪崩击穿后的大电流区,栅压对器件内部温度的影响.结果表明:温度随正栅压升高而升高,随负栅压升高而降低,并分析了有源区内电场强度、电流密度和功率密度随栅压的变化规律.从而证明,与LDMOS栅接地时相比,正栅压降低了器件的静电放电能力,而负栅压则提高了器件的静电放电能力. 相似文献
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Sudden failures appearing during static gate bias — temperature aging of CMOS transistors are investigated in this paper. Shorts between the gate and substrate as well as open gate circuits are found to be failure modes appearing during testing. The subsequent failure analysis reveals that the reaction between the aluminium and gate oxide is the failure mechanism, while defects in P+-diffusion regions (which are transferred onto the gate oxide) are the cause of the observed failures. 相似文献