嵌入式图形处理器中几何变换引擎的设计

针对嵌入式系统处理三维图形时需要良好的实时性要求,提出使用专用嵌入式图形处理器负责图形处理,用以缓解CPU负担,提高处理速度的解决方法。几何变换引擎位于图形处理器内部图形流水线的第一级,负责处理三维图形在空间坐标系中的位置变换。设计了几何变换引擎的架构模型,采用Verilog HDL实现引擎的IP软核,并在Modelsim和QuartusII环境中完成IP核的功能仿真与时序验证。综合后,IP核占用FPGA资源为9715逻辑单元,单顶点的处理时间为160ns,实现处理图形几何变换的任务,达到预期设计要求。     

嵌入式图形处理器裁剪引擎的设计

以计算机图形学为基础,文章设计了一种具有较好通用性的嵌入式图形处理器裁剪引擎。重点剖析了裁剪算法和裁剪引擎RTL级模型的设计,该模型采用Verilog HDL实现引擎的IP软核,并在QuartusⅡ环境中完成IP核的功能仿真与时序验证。综合后,IP核占用FPGA资源为9489逻辑单元,实现了对图形进行裁剪的任务,达到了预期的设计要求。     

OpenCMP：一个支持事务存储模型的多核处理器模拟器

CPU设计正在由仅开发指令级并行性的单线程单核结构转向利用线程级并行性的多线程多核结构，但至今还没有一个可移植性好并被广泛使用的开源多核处理器模拟器，限制了在这样的结构上开展高质量的研究工作。我们开发了一个多核处理器体系结构模拟器OpenCMP，用于支持当前和未来对多线程多核处理器体系结构关键技术的研究。该模拟器适当地抽象了多核处理器结构，为主流的多核处理器结构研究提供一个可扩展、灵活的模拟工具框架，包括支持对乱序、顺序的处理器核和同时多线程处理器核的模拟，以便对更大的多核设计空间进行比较性研究。本文以支持事务存储模型的多核处理器结构模拟器为例，详细描述了如何通过抽象多核结构和事务存储模型的最基本特性和组成部分，扩展单核处理器模拟器SimpleScalar，设计与实现一个多核处理器模拟器。初步研究表明，与现有的多核处理器模拟器相比，该模拟器能够较好地支持对事务存储模型和基于事务存储模型的多核处理器体系结构的研究．     

十二款GeForce2 GTS、GeForce2 MX显示卡横向评测报告

一、前言 1999年8月31日对于3D图形芯片技术的发展史来说应当是一个值得纪念的日子,在这一天世界知名图形芯片制造厂商nVIDIA公司正式发布了代号为NV10的GeForce 256图形处理芯片。在新发布的GeForce 256图形处理芯片中,nVIDIA公司首次提出了GPU(图形处理器)的概念,按照这种概念,GPU所应当具备的特性包括:单芯片图形处理器,集成有几何引擎、光照引擎、三角形设置、图形剪裁引擎、纹理渲染引擎等,其处理能力为每秒1000万个以上多边形。GPU的概念,从字面上     

基于TLM2.0的SPARC事务级建模

为提高可扩展处理器体系结构(SPARC)的设计抽象层次和仿真速度,设计一种符合第8版SPARC(SPARC V8)的事务级模型。该模型基于TLM2.0标准,采用解释型指令集仿真方法实现程序执行。通过构建验证环境,证明该事务级模型能够正确运行并跟踪SPARC V8程序,仿真速度比寄存器传输级提高2个数量级。     

多核处理器事务级模型多视图协同验证环境

随着集成电路工艺持续高速发展,片上处理器核数目呈现指数增长规律,设计复杂程度不断增长,对处理器验证提出了严峻的挑战,至今仍缺乏有效的工具手段。提出了一种多核处理器事务级模型的多视图协同验证方法,将模拟验证、形式验证、应用验证三种不同验证视图,采用统一平台集成为一体化验证环境。从而可在一体化验证环境中,充分发挥多种验证方法综合应用的优势,协同高效完成多核处理器事务级模型验证任务。基于SoCLib事务级建模仿真平台实现了一个具有良好可扩展性的多视图协同验证环境MVIE。初步应用实验结果表明,多视图协同验证和传统单一视图验证方法相比,在模型验证的方便性、完备性、高效性以及模型数据一致性维护等方面,具有明显的优势。     

粗粒度数据流网络处理器体系结构及原型系统设计

网络处理器是一种支持高速报文处理和转发的可编程通信集成电路.作为路由器中的重要组件,网络处理器设计不但强调高性能,还要求足够的灵活性以支持未来的网络协议.针对控制流网络处理器固定拓扑结构及指令级并行性开发方面的不足,采用粗粒度数据流设计思想,提出了一种粗粒度数据流网络处理器体系结构及原型--DynaNP.DynaNP不但可利用处理引擎内控制流执行方式获得高可编程性,还利用处理引擎间数据流执行方式有效开发报文处理中的任务级并行性.此外,DynaNP提供了处理路径动态配置机制,可有效提高系统流量.DynaNP的原型系统基于SoPC技术设计实现.多个PE和功能模块通过片上高速通信网络连接,其中,核心处理引擎采用嵌入式RISC处理器核LEON3实现,并采用指令集扩展技术优化网络协议处理.该原型系统可有效验证粗粒度数据流网络处理器的功能和关键技术.     

一种嵌入式图形支持库的设计与实现

在嵌入式系统中,由于硬件的限制和软件工程实施上的困难,一直缺乏一种较为完善的2D/3D图形设计以及游戏图形控制引擎.为了解决上述问题,提出了一种同时支持2D和3D图形处理和I/O控制的嵌入式图形接口模型.该模型采用组件化模式,支持2D GUI设计,也可用作为3D图形设计和游戏引擎开发.     

网络处理器自适应负载均衡调度机制*

对TLDP结构网络处理器的线程调度问题展开讨论,设计并用硬连线实现了TLPD结构的微引擎间自适应负载均衡线程调度机制。它根据TLDP结构内部各个微引擎的实时负载状态和历史信息自动调整活动微引擎的数量,然后在被选择的活动微引擎集合上实现微引擎间的动态负载均衡,最大程度地提高了TLDP结构网络处理器的分组吞吐率。通过对TLDP结构的RTL级模型仿真说明,该机制能有效地实现微引擎间的实时负载均衡。     

支持推测并行化的事务存储硬件模拟系统

多核处理器通过增加处理器核数提高计算能力,虽然可以通过同时运行多道程序的方式利用处理器资源,但是多核处理器真正的成功取决于解决并行应用开发中的难题.为此,处理器体系结构和编程模型的协同开发是必须的.而随着核数的增多,传统上使用的软件模拟器因为软件的串行性而性能越来越差,无法支持这种软硬件协同开发.FPGA天生的并行性使它在模拟多核处理器时具有较高的模拟性能和高度的可扩放性,成为处理器体系结构研究的理想工具.本文介绍了基于FPGA的多核模拟系统,RAMP-Pink.该系统基于HASim实现,同时支持事务存储和线程级推测,用于对事务存储和线程级推测的软硬件协同开发.该模拟系统可配置不同的FPGA开发平台,也可以以软件模拟方式运行.     

Modeling irregular boundary with transmission‐line modeling method

This work proposes a model to represent internal and external fractional boundary nodes without increasing the computational time and memory comparing to other techniques. The limiting effects on the simulation time steps are the same of the basic transmission‐line nodes. This model is also indicated for parallel processing, once it does not produce branching in the algorithm stream. The processing time is the same as a basic transmission‐line modeling (conventional TLM) mesh independent of the boundary complexity. The accuracy is higher than the one obtained with the basic TLM (full nodes). This model is suitable for hybrid and general TLM symmetrical condensed nodes. Validations are made against analytical results, numerical TLM results (conventional TLM), and other published results. © 2012 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2013.     

Equivalence checking between SLM and TLM using coverage directed simulation

The increasing complexity of digital systems makes designers begin to design using abstract system level modeling (SLM). However, SLM brings new challenges for verification engineers to guarantee the functional equivalence between SLM specifications and lower-level implementations such as those of transaction level modeling (TLM). This paper proposes a novel method for equivalence checking between SLM and TLM based on coverage directed simulation. Our method randomly simulates an SLM model and uses an satisfiability modulo theories (SMT) solver to generate stimuli for the uncovered area with the direction of a composite coverage metric (code coverage and functional coverage). Then we run all the generated stimuli (random stimuli and direct stimuli) on both SLM and TLM designs. At the same time, the selected observation variables are compared to evaluate the equivalence between SLM and TLM. Promising experimental results show that our equivalence checking method is more efficient with lower simulation cost.     

Time-domain approach to microwave circuit modeling: A view of general relations between TLM and FDTD (Invited article)

The author's research on the time-domain methods for electromagnetic simulation is reported with focus on the expanded-node FDTD and TLM approaches. The theorem of formal equivalence of FDTD and TLM together with its fundamental consequences (published recently or yet unpublished) is summarized. As an example of application of the theorem, a new family of nonequidistant TLM algorithms with controlled stability margin is originally derived by transformation from FDTD. Several meshing techniques for the modeling of irregular geometries are compared, and the locally modified grids based on local integral approximations are shown to provide optimum accuracy to computer resources ratio for practical microwave problems. © 1996 John Wiley & Sons, Inc.     

片上系统设计中事务级建模技术综述

随着集成电路复杂度的提高,事务级建模成为了片上系统设计中一个新的研究方向.系统地总结了近年来事务级建模技术的研究热点及设计者关注的问题,介绍了该技术在建模与模拟验证中的作用与优势;分析了事务级建模发展中需要解决的问题,并对其前景进行了展望.     

TLM modeling of a probe‐coupled cylindrical cavity based on compact wire model in the cylindrical mesh

This article describes an implementation of a compact wire model into the three‐dimensional transmission‐line matrix (TLM) cylindrical mesh for the purpose of an efficient analysis of probe‐coupled cylindrical microwave cavity devices. Because of a cylindrical grid structure and empirical nature of the compact model, this implementation has to take into account a change of wire model parameters with a variable cross section of the TLM nodes through which a wire conductor passes. The model accuracy has been experimentally verified and compared with the corresponding results reached by the TLM method based on a rectangular grid in order to consider its advantages. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2012.     

Application of the transmission line method to the solution of the continuous Kalman filter equations of general order

In this paper, the transmission line method (TLM) is applied to the solution of the general, nth order, continuous Kalman filter estimation equations. A comparison is made between this method, the first-order Gear algorithm and the fourth-order Runge-Kutta method, in the estimation of the voltage drop and its derivative across a capacitor in an LCR circuit. An analysis is made of the sensitivity of the algorithms to changing time step and measurement error variance. In most cases, the Runge-Kutta method has the best performance at the expense of computing time. However, in some cases, the new algorithm yields less biased and smoother estimates. The TLM algorithm performs consistently better than the Gear method for the particular problem analysed. The CPU time for the TLM algorithm has also been compared with that required by the Gear and Runge-Kutta methods; the TLM method is found to take approximately 25% of the time required by the Runge-Kutta method to process one measurement. The TLM algorithm appears to present a compromise between accuracy of estimation and computing time. Finally, suggestions are made for further work.     

A GPU Tile-Load-Map architecture for terrain rendering: theory and applications

This paper describes a robust, modular, complete GPU architecture—the Tile-Load-Map (TLM)—designed for the real-time visualization of wide textured terrains created with arbitrary meshes. It extends and completes our previous succinct paper Amara et al. (ISVC 2007, Part 1, Lecture Notes in Computer Science, vol. 4841, pp. 586–597, Springer, Berlin, 2007) by giving further technical and implementation details. It provides new solutions to problems that had been left unresolved, in the context of a joint use of OpenGL and CUDA, optimized on the G80 graphics chip. We explain the crucial components of the shaders, and emphasize the progress we have proposed, while resolving some difficulties. We show that this texturing architecture is well suited to current challenges, and takes into account most of the distinctive aspects of terrain rendering. Finally, we demonstrate how the design of the TLM facilitates the integration of geomatic input-data into procedural selection/rendering tasks on the GPU, and immediate applications to amplification. Electronic Supplementary Material  The online version of this article () contains supplementary material, which is available to authorized users.

TLM analysis of a cylindrical metallic cavity excited with a real‐feed probe

The influence of feed‐probe dimensions on the resonant frequencies in a cylindrical metallic cavity is investigated and presented. Cavity modelling is achieved by using the transmission‐line matrix (TLM) time‐domain method and a wire node to account for the feed‐probe presence. The results of the TLM analysis are validated against the experimental results. © 2006 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2006.     

电力电子电路的传输线计算机仿真模型研究

准确、稳定的电力电子电路计算机仿真模型是进行电路分析和研究的基础,传输线模型(TLM)是一种基于数值求解微分方程的电力电子电路计算机仿真模型,通过研究电路元件传输线模型的数值计算局部截断误差和整体截断误差,证明了电力电子电路传输线模型数值计算的收敛性和稳定性.与原有的分析电力电子电路暂态过程的离散分析方法相比,这种方法使用简单,物理概念明确,在小步长情况下同样有较好的稳定性,通过Matlab的M文件对模型的仿真结果与经典RK4计算结果的比对,表明了该方法的有效性.