An Effective Test and Diagnosis Algorithm for Dual‐Port Memories

This paper proposes a test algorithm that can detect and diagnose all the faults occurring in dual‐port memories that can be accessed simultaneously through two ports. In this paper, we develop a new diagnosis algorithm that classifies faults in detail when they are detected while the test process is being developed. The algorithm is particularly efficient because it uses information that can be obtained by test results as well as results using an additional diagnosis pattern. The algorithm can also diagnose various fault models for dual‐port memories.     

Testing content addressable memories with physical fault models

Content addressable memory （CAM） is widely used and its tests mostly use functional fault models. However, functional fault models cannot describe some physical faults exactly. This paper introduces physical fault models for write-only CAM. Two test algorithms which can cover 100% targeted physical faults are also proposed. The algorithm for a CAM module with N-bit match output signal needs only 2N＋2L＋4 comparison operations and 5N writing operations, where N is the number of words and L is the word length. The algorithm for a HIT-signal-only CAM module uses 2N＋2L＋5 comparison operations and 8N writing operations. Compared to previous work, the proposed algorithms can test more physical faults with a few more operations. An experiment on a test chip shows the effectiveness and efficiency of the proposed physical fault models and algorithms.     

Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests

The ever increasing trend to reduce DPM levels of memories requires tests with very high fault coverage and low cost. This paper describes an important fault class, called dynamic faults, that cannot be ignored anymore. The dynamic fault behavior can take place in the absence of the static fault behavior, for which the conventional memory tests have been constructed. The concept of dynamic fault will be established and validated for both dynamic and static Random-Access-Memories. A systematic way to develop fault models for dynamic faults will be introduced. Further, it will be shown that conventional memory tests do not necessarily detect its dynamic faulty behavior, which has been shown to exist in real designs. The paper therefore also presents new memory tests to target the dynamic fault class.     

Fault Models and Test Procedures for Flash Memory Disturbances

Disturbances are special type of faults that are unique to flash memories. Causes of the disturbances are defects within the insulating layers of the memory element. These defects result in abnormal behavior of a memory cell under specific conditions. This paper describes characteristics of these defects as well as their manifestation as DC-Programming, DC-Erasure, and Drain Disturbance. We develop fault models to capture the behavior of faulty flash memories. We introduce three different fault models based on the underlying defects in a memory cell. These models are: Simple, Exclusive and General Fault model. Further, we develop test algorithms that detect disturbance faults under each of the fault models. The test algorithms reported in this paper for the simple fault model for each type of disturbance require optimal number of program, read, and flash operations; where as the algorithms for the remaining two fault models require near optimal number of these operations.     

Effective march algorithms for testing single-order addressed memories

Today's commonly used macro generators provide for read/write memories of type SRAM, Register File, Multi-Port RAM, Single-Order Addressed Memory (e.g. FIFO), CAM (Content Addressable Memory), etc. In addition to automatically generating the required momory, the appropriate test, which may be applied externally or internally as a BIST, has to be determined.Current literature provides tests for most memory types; however, tests for single-order addressed (SOA) memories, whereby the address can only change in one direction (e.g. from address 0 ton-1) have not been published yet. SOA memories are used in FIFOs and in applications where the BIST area overhead and/or speed penalty for normal (dual) order addressing are not acceptable.This article illustrates the testing problems and presents a family of march algorithms optimized for testing SOA memories.     

存储器故障诊断算法的研究与改进

由于存储器的结构比较复杂，应用又十分广泛，所以一直是国内外测试领域重点研究的课题之一。在研究经典的存储器故障诊断算法的基础上，吸取经典算法的思想，并结合实际需要，提出了一种基于地址移位的存储器故障诊断方法。他克服了以往算法占用计算机存储空间大、诊断耗时长的缺点，简单易行。实践证明，他的故障覆盖率完全满足要求。     

Defect Analysis and Defect Tolerant Design of Multi-port SRAMs

Multi-port SRAMs are often implemented using static random access memory (SRAM) due to its fast operation and the ability to support multiple read and write operations simultaneously, thus increasing data throughput in embedded systems and meeting the expected demands of parallel or pipelined microprocessors. With the continuous scaling of transistor feature size, designing low power robust memories and investigating their failure characteristics become critical. In this paper, we study the defects occurring in the multi-port SRAM cells. The memory is modeled at the transistor level and analyzed for electrical defects by applying a set of test patterns. Not only have existing models been taken into account in our simulation but also a new fault model, namely, simultaneous deceptive destructive read fault for the multi-port memory is introduced. In addition, we extend our study to the defect tolerant design of memories by proposing a differential current-mode sense amplifier for 3-port SRAM based register file. We examine the fault models of resistive defects within the SRAM cell and its failure boundary. A read disturb fault for multi-port memories is tested on the faulty cell by simultaneous read operations with different numbers of ports. Experimental results show that the proposed current-mode sensing scheme has improvements for memory fault-tolerance of resistive defects at 4.6× for dual-port read and 5.8× for 3-port read compared to voltage-mode sensing with 0.18 μm manufacturing process technology.     

Testing and Reliability Techniques for High-Bandwidth Embedded RAMs

Application-specific integrated circuits (ASICs) and high-performance processors such as Itanium and Compaq Alpha use a total of almost 75% of chip real estate for accommodating various types of embedded (or on-chip) memories. Although most of these embedded memories are single-port static (and in relatively few cases, dynamic) RAMs today, the high demand for bandwidth in digital television, fast signal processing, and high-speed networking applications will also fuel the need for on-chip multiport memories in the foreseeable future. The reliability of a complex VLSI chip will depend largely on the reliability of these embedded memory blocks. With device dimensions moving rapidly toward the ultimate physical limits of device scaling, which is in the regime of feature sizes of 50 nm or so, a host of complex failure modes is expected to occur in memory circuits. This tutorial underlines the need for appropriate testing and reliability techniques for the present to the next generation of embedded RAMs. Topics covered include: reliability and quality testing, fault modeling, advanced built-in self-test (BIST), built-in self-diagnosis (BISD), and built-in self-repair (BISR) techniques for high-bandwidth embedded RAMs.     

基于低摆幅策略的低功耗多端口寄存器文件设计

本文通过使用低摆幅策略和修改的与非型地址译码器设计了一种低功耗的寄存器文件。该低摆幅策略基于反馈机制并利用动态逻辑减少主动反馈引入的功耗。低摆幅策略分为读写两部分。在低摆幅写策略中,设计了一种存储单元用来支持低摆幅写入。修改后的NAND解码器,不仅功耗更低,同时面积也大幅减少。对比传统单端位线的寄存器文件,低摆幅技术在读和写部分能分别降低51.15%和34.5%的功耗。后仿结果表明在十二个端口同时工作时,低摆幅策略能够降低39.4%的功耗。     

Concurrent error detection in highly structured logic arrays

Two strategies for encoding the inputs and outputs of highly structured logic arrays (HSLAs) are introduced. The two schemes are particularly relevant for concurrent error detection of both permanent and nonpermanent errors in programmable logic arrays (PLAs) and read-only memories (ROMs). The first method of concurrent error detection (CED) is based on a comprehensive fault model and relies on detection of unidirection errors. The second approach relies on a detailed examined of decoder layouts resulting in fault avoidance through layout rules, which avoid failures causing unidirectional errors. Efficient parity techniques are shown to provide a low-overhead solution to concurrent error detection when coupled with appropriate fault-avoidance techniques.     

On the generation of higher order chaotic oscillators via passive coupling of two identical or nonidentical sinusoidal oscillators

We investigate the possibility of generating higher order chaos via passive coupling of two identical or nonidentical sinusoidal oscillators. The examples of such a technique, which have already been reported in the literature, suffer from the lack of generality and apply only to particular sinusoidal oscillator circuits. Here, we treat sinusoidal oscillators either as generic single-port or two-port networks, and examine all the different coupling possibilities of any two stages. For this purpose, we choose the simplest possible coupling technique composed of two diodes; one of which represents a self-stage-controlled nonlinearity while the other represents an inter-stage mutually controlled nonlinearity. Experimental observations for selected coupling cases are shown.     

基于云进化算法的3D NoC测试端口优化选择

针对于三维片上网络测试时,如何选择测试端口以提高测试效率的难题,采用基于云模型的进化算法对三维片上网络测试端口进行位置寻优,并对IP核的测试数据进行合理分配,在测试功耗约束条件下,以重用片上网络作为测试访问机制,基于XYZ路由算法和非抢占式测试调度方式,对三维片上网络IP核实施并行测试,以提高测试效率。研究结果表明,该方法可对测试端口的位置及组合方案进行精确寻优,且有效减少了测试时间。     

Testable design of large random access memories

In this paper we propose a method for testable design of large Random Access Memories. The design technique relies on modification of address decoders to achieve multi-writes and multi-reads during test mode. Almost no modification is required in the design of memory array.A number of different designs for decoders are proposed. In all the designs the objective has been to keep the extra hardware for enhancing testability to as small as possible while causing a minimal or no degradation at all in the speed performance of RAM. Use of extra control and observation points is allowed as long as such points cause only a very small increase in the number of extra pins.We also propose the design of decorders in which only a limited number of cells of RAM are written to or read from during test mode.     

RF and IF ports matching circuit synthesis for a simultaneousconjugate-matched mixer using quasi-linear analysis

A quasi-linear two-port approach between RF and IF ports to design a simultaneous conjugate-matched mixer is presented in this paper. Conventionally, mixer design is treated as a nonlinear three-port device problem. Nonetheless, with the exception of the large-signal local oscillator (LO) that exists at the LO port, the input RF and output IF signals that exist at the RF and IF ports, respectively, are small signals. Consequently, mixers can be approximated as bilateral quasi-linear two-port circuits with a time-variant transfer function between the RF and IF ports, in which the LO port of the mixer is treated as part of the two-port network. With this approximation, it can be shown mathematically that the optimum source and load matching networks required for attaining simultaneous conjugate match at the RF and IF ports are actually time invariant, thus implying that it is possible to synthesize these optimum impedance values. This proposed mixer design technique, together with the equations derived, are verified with block-diagram simulation and experimental measurements of two 2.4-GHz RF/420-MHz IF double-balanced diode mixers     

Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets

An automatic test pattern generation (ATPG) procedure for linear analog circuits is presented in this work. A fault-based multifrequency test approach is considered. The procedure selects a minimal set of test measures and generates the minimal set of frequency tests which guarantee maximum fault coverage and, if required, maximal fault diagnosis, of circuit AC hard/soft faults. The procedure is most suitable for linear time-invariant circuits which present significant frequency-dependent fault effects.For test generation, the approach is applicable once parametric tests have determined DC behaviour. The advantage of this procedure with respect to previous works is that it guarantees a minimal size test set. For fault diagnosis, a fault dictionary containing a signature of the effects of each fault in the frequency domain is used. Fault location and fault identification can be achieved without the need of analog test points, and just in-circuit checkers with an observable go/no-go digital output are required for diagnosis.The procedure is exemplified for the case of an analog biquadratic filter. Three different self-test approaches for this circuit are considered. For each self-test strategy, a set of several test measures is possible. The procedure selects, in each case, the minimal set of test measures and the minimal set of frequency tests which guarantee maximum fault coverage and maximal diagnosis. With this, the self-test approaches are compared in terms of the fault coverage and the fault diagnosability achieved.This work is part of AMATIST ESPRIT-III Basic Research Project, funded by CEC under contract #8820.     

Tutorial on semiconductor memory testing

This article is a tutorial introduction to the field of semiconductor memory testing. It begins by describing the structure and operation of the main types of semiconductor memory. The various ways in which manufacturing defects and failure mechanisms can cause erroneous memory behavior are then reviewed. Next we describe the different contexts in which memories are tested together with the corresponding different types of tests. The closely related processes of fault modeling and test development are then summarized. Various design for testability strategies for memories are also presented. Finally, current trends in the design and testing of memory are outlined.This work was supported by the Natural Sciences and Engineering Research Council of Canada under grant OGP 0105567.     

SOC中嵌入式存储器阴影逻辑的可测性设计

在使用ATPG工具对集成电路进行固定故障测试时,嵌入式存储器模块被视为简单的I/O模型,ATPG工具无法传递存储器周围组合逻辑的故障.通过研究SOC的可测性设计后,针对某数字信息安全芯片设计,利用扫描设计原理,改进了其存储器周围逻辑的设计,为阴影逻辑提供了可测试路径,提高了整个芯片的测试覆盖率和故障覆盖率.分析了设计的功耗、面积,确定了设计的有效性.     

Extended selection of switching target faults in CONT algorithm for test generation

We describe an extended selection of switching target faults in the CONT algorithm. The main difficulty in test generation is the conflict that arises in the process of determining the signal values due to reconvergent fanouts. Conventional approaches for test generation change a signal value, which causes conflicts to another possible choice for backtracking. In the CONT algorithm, a strategy of switching target fault was proposed as a new backtracking mechanism. In this method, the target fault is switched to a new target fault instead of making an alternative assignment on the primary input value when a conflict occurs. A disadvantage of the CONT algorithm is that unjustified lines exist in the process of test generation. These unjustified lines make the procedure of switching targets complicated and restrict the possible choice in selecting the new target fault. In the new version of CONT, called CONT-2, we have removed the unjustified lines in the process of test generation and have extended to two target-fault types for switching targets. Implementing CONT-2 by a Fortran program, ISCAS85 benchmark circuits are examined. Experiments on a combined system with fault simulation followed by CONT-2 are also presented.     

Technology and layout-related testing of static random-access memories

Static random-access memories (SRAMs) exhibit faults that are electrical in nature. Functional and electrical testing are performed to diagnose faulty operation. These tests are usually designed from simple fault models that describe the chip interface behavior without a thorough analysis of the chip layout and technology. However, there are certaintechnology and layout-related defects that are internal to the chip and are mostly time-dependent in nature. The resulting failures may or may not seriously degrade the input/output interface behavior. They may show up as electrical faults (such as a slow access fault) and/or functional faults (such as a pattern sensitive fault). However, these faults cannot be described properly with the functional fault models because these models do not take timing into account. Also, electrical fault models that describe merely the input/output interface behavior are inadequate to characterize every possible defect in the basic SRAM cell. Examples of faults produced by these defects are: (a) static data loss, (b) abnormally high currents drawn from the power supply, etc. Generating tests for such faults often requires a thorough understanding and analysis of the circuit technology and layout. In this article, we shall examine ways to characterize and test such faults. We shall divide such faults into two categories depending on the types of SRAMs they effect—silicon SRAMs and GaAs SRAMs.     

基于系统级诊断理论的卫星网络故障诊断

本文将系统级诊断引入到卫星网络的故障诊断领域.针对卫星可以具有多个通信方向且可以部分通信失效的特性,提出了一种新颖的卫星网络建模方法——双层节点图,设计了基于广播的卫星网络系统级诊断方案,并对其通信开销进行了理论分析.测试中充分利用了卫星广播和一对多的通信模式,使本方案不但适用于任意类型的网络拓扑,而且可以节省通信量.仿真结果表明诊断的通信开销随网络中可通信端口数量的减少而下降.