A Design of a Low-Voltage Current-Mode Fully-Differential Analog CMOS Integrator Using FG-MOSFETs and Its Implementation

In the field of analog signal processing, there is a strong need for low-voltage and low-power integrated circuits. Especially in the mobile communication circuitry, an analog signal processing circuit must be fed by dry batteries of 1–1.5 V. This paper presents a design and implementation of a current-mode fully-differential analog CMOS integrator operable with such a low supply voltage. This integrator is built with a cross-coupled matched pair of 3-input FG(Floating Gate)-MOSFETs, a matched pair of 2-input FG-MOSFETs, and four bias current sources. In this circuit, both a low apparent threshold voltage of FG-MOSFETs and voltage signal summation at the floating gates are effectively utilized to enable the circuit operation with a low supply voltage and to simplify the circuit configuration. The influence of the common-mode signal and noise to the signal processing are minimized by adopting fully-differential structure. The performance of the proposed integrator circuit is predicted by theoretical analysis and by HSPICE simulations. The circuit works as an integrator in the frequency range 4–750 MHz at a 1.5 V supply voltage and dissipates DC power of about 70 W. The proposed circuit was fabricated by a Motorola 1.2 m double-poly CMOS process in the chip fabrication program of VLSI Design and Education Center (VDEC).     

A 5-V front-end chip for a universal voice-band modem

A circuit that, combined with one or two commercially available digital signal processing (DSP) chips, may implement all voice-band modem standards from 300 b/s to 14.4 kb/s, in full or half duplex operation including echo-cancelling standards, is presented. All analog functions and all non-DSP digital functions are performed by the circuit. Good dynamic range with low distortion in the analog circuitry is maintained while designing for a high-density digital process with high-quality capacitors. Such a process can be used to achieve an area-efficient circuit. The circuit has been implemented in a 1.2-μm CMOS double-poly, double-metal process, operates off a single 5-V supply, and measures only 63 kmil² (40.7 mm²)     

A single-chip 5-V 2400-b/s modem

A single-chip split-band 2400-b/s modem has been implemented in a 3-μm CMOS process. A high-level of integration results in a low-cost, high-performance modem. Single-ended analog switched-capacitor circuitry and an application-specific digital signal processor (DSP) combine to perform all modem signal processing. The transmit processing is performed almost entirely in the analog domain. The receiver is performed almost entirely in the analog domain. The IC also supports a number of lower-speed (⩽1200 b/s) split-band modem standards. The chip occupies 68.8 mm² and dissipates 120 mW while operating off a single 5-V supply. System and circuit aspects of the design are discussed, and the measured performance of the IC is summarized     

A single-chip CMOS PCM codec

Describes a single-chip full duplex per channel PCM codec implemented in a metal gate CMOS process. An 8-bit companding DAC, a novel autozeroed analog subsystem, and a 3.5-MHz frame interface control logic comprise the 175/spl times/195-mil integrated circuit. The DAC is implemented with matched n channel devices and utilizes redundancy and feedback to achieve the required accuracy. The analog subsystem contains two sample and hold circuits, autozeroing circuitry, CMOS amplifiers, and a fast CMOS comparator.     

A four-channel CMOS codec filter circuit “SICOFI-4”

Cost reduction by integration of complex mixed analog-digital systems on a single chip and an excellent yield to area ratio is a major goal for IC design in the nineties. In this paper, a four-channel codec-filter chip for analog subscriber lines in ISDN-orientated networks is presented, giving an exceptional example for high level system implementation combined with parallel DSP integration and analog circuitry with high performance. The chip combines four analog frontends, digital signal processing realized by different approaches for a sophisticated filter concept in addition with test strategies including digital and analog BIST. The circuit is fabricated in a standard 1-μm CMOS technology, needs a single 5-V power supply, and can easily be programmed to world-wide different country specifications and applications     

CMOS Design of a Current-Mode Multiplier/Divider Circuit with Applications to Fuzzy Controllers

Multiplier and divider circuits are usually required in the fields of analog signal processing and parallel-computing neural or fuzzy systems. In particular, this paper focuses on the hardware implementation of fuzzy controllers, where the divider circuit is usually the bottleneck. Multiplier/divider circuits can be implemented with a combination of A/D-D/A converters. An efficient design based on current-mode data converters is presented herein. Continuous-time algorithmic converters are chosen to reduce the control circuitry and to obtain a modular design based on a cascade of bit cells. Several circuit structures to implement these cells are presented and discussed. The one that is selected enables a better trade-off speed/power than others previously reported in the literature while maintaining a low area occupation. The resulting multiplier/divider circuit offers a low voltage operation, provides the division result in both analog and digital formats, and it is suitable for applications of low or middle resolution (up to 9 bits) like applications to fuzzy controllers. The analysis is illustrated with Hspice simulations and experimental results from a CMOS multiplier/divider prototype with 5-bit resolution. Experimental results from a CMOS current-mode fuzzy controller chip that contains the proposed design are also included.     

Measuring and modeling the effects of substrate noise on the LNAfor a CMOS GPS receiver

The influence of substrate noise coupling on the performance of a low-noise amplifier (LNA) for a CMOS GPS receiver has been investigated both analytically and experimentally. A frequency-domain approach has been used to model both noise injection into the substrate from digital circuitry integrated on the same chip and the mechanisms by which that noise can affect analog circuit behavior. The results of this study reveal that substrate noise can modulate the LNA input signal as well as couple directly to the amplifier's output     

Design of a window comparator with adaptive error threshold for online testing applications

This paper presents a novel window comparator circuit whose error threshold adjusts adaptively with respect to its input signal levels. Advantages of adaptive error thresholds over constant or relative error thresholds in analog testing applications are discussed. Analytical equations for guiding the design of the comparator circuitry are derived. The proposed comparator circuit has been designed and fabricated using a CMOS technology. Measurement results of the fabricated chip are presented.     

A 27-MHz digital-to-analog video processor

The authors describe a circuit intended for the restitution of a digital video signal into its analog red, green, and blue components. Sampling parameters according to CCIR recommendation 601 have been adopted for the digital interface. The circuit consists mainly of a complex digital processing part and three digital-to-analog converters. All of these functions have been implemented in a 38-mm² CMOS chip. The design goal was achieved by the development of an efficient 2-μm CMOS technology dedicated to analog and digital applications     

A 256-element CMOS imaging receiver for free-space optical communication

This paper describes a CMOS imaging receiver for free-space optical (FSO) communication. The die contains 256 optical receive channels with -47 dBm optical sensitivity and 30 dB optical dynamic range at 500 kb/s/channel while consuming 67 mW. Received signals are amplified by digitally self-calibrated open-loop amplifiers and digitized before clock and data recovery. The sampled data also provide inputs for digital automatic gain and offset control loops closed around the analog amplifier chain to compensate for signal variations due to atmospheric turbulence and daylight interference. Gain control logic can adapt to incident signals over the 30 dB dynamic range within 28 bit periods. Low-power logic design and analog circuit techniques are used to minimize digital crosstalk to single-ended photodetectors referenced to a bulk substrate. Local arbitration circuitry at each channel forms an intrachip data passing network to multiplex received data words from the 16 /spl times/ 16 array onto a common off-chip bus. The 1.6 M transistor mixed-signal die fabricated in a 0.25 /spl mu/m CMOS process measures 6.5/spl times/6.5 mm/sup 2/. Reception at 500 kb/s through a 1.5 km atmospheric channel is demonstrated with 3 mW optical transmit power during nighttime and daylight hours.     

A wireless implantable multichannel digital neural recording systemfor a micromachined sieve electrode

This paper reports the development of an implantable, fully integrated, multichannel peripheral neural recording system, which is powered and controlled using an RF telemetry link. The system allows recording of ±500 μV neural signals from axons regenerated through a micromachined silicon sieve electrode. These signals are amplified using on-chip 100 Hz to 3.1 kHz bandlimited amplifiers, multiplexed, and digitized with a low-power (<2 mW), moderate speed (8 μs/b) current-mode 8-b analog-to-digital converter (ADC). The digitized signal is transmitted to the outside world using a passive RF telemetry link. The circuit is implemented using a bipolar CMOS process. The signal processing CMOS circuitry dissipates only 10 mW of power from a 5-V supply while operating at 2 MHz and consumes 4×4 mm² of area. The overall circuit including the RF interface circuitry contains over 5000 transistors, dissipates 90 mW of power, and consumes 4×6 mm² of area     

A CMOS low-noise and low-power charge sampling integrated circuitfor capacitive detector/sensor interfaces

This paper describes the design and experimental results of a multichannel calibrationless charge sampling integrated circuit for capacitive detector/sensor interfaces. The integrated circuit incorporates multiple channels of sensitive charge preamplifiers, current/charge-mode amplifiers, pipelined analog storage cells, A/D converters, and static CMOS digital control circuitry. It is implemented in a 1.2 μm single-poly double-metal CMOS p-well technology. The power dissipation is 1 mW/channel. The input-referred equivalent noise charge (ENC) for a detector/sensor source capacitance of 30 pF and an integration time window of 128 ns is 1800 rms electrons. The input-referred channel-to-channel offset variation from chip to chip is only 292 rms electrons while the storage-cell-to-storage-cell offset variation is 142 rms electrons. The channel-to-channel gain variation from chip to chip is 1.6%     

A 14-bit 80-kHz sigma-delta A/D converter: modeling, design andperformance evaluation

The development is described of a sigma-delta A/D (analog-to-digital) converter. Included is a brief overview of sigma-delta conversion. The A/D converter achieves an 88.5-dB dynamic range and a maximum signal-to-noise ratio of 81.5 dB. The harmonic distortion is negligible. This level of performance is about 10 dB higher than previously reported results for oversampled A/D converters in this frequency range. The analog modulator uses a double-integration switched-capacitor architecture with an oversampling rate of 10.24 MHz. Transconductance amplifiers having a 160-MHz f_t were developed for the integrators. The circuit is implemented in a 1.75-μm 5-V CMOS process. The analog circuitry occupies 2 mm² of silicon area and consumes 75 mW of power. Some of the difficult problems associated with evaluating the performance of sigma-delta converters are described. The design of a sigma-delta development and performance evaluation system is presented. This system includes a custom interface board linking the chip to a Sun workstation, and extensive digital signal processing and analysis software     

An insect vision-based motion detection chip

The architectural and circuit design aspects of a mixed analog/digital very large scale integration (VLSI) motion detection chip based on models of the insect visual system are described. The chip comprises two one-dimensional 64-cell arrays as well as front-end analog circuitry for early visual processing and digital control circuits. Each analog processing cell comprises a photodetector, circuits for spatial averaging and multiplicative noise cancellation, differentiation, and thresholding. The operation and configuration of the analog cells is controlled by digital circuits, thus implementing a reconfigurable architecture which facilitates the evaluation of several newly designed analog circuits. The chip has been designed and fabricated in a 1.2-μm CMOS process and occupies an area of 2×2 mm²     

Single-polarity dual-rail logic

Static CMOS circuit techniques are widely used for processor design. The authors introduce an add-on technique for high-speed static circuit realisation. The underlying processes of this technique, a time-shifting process and a collision process, are described and the performance of the resulting circuitry is compared with that of the conventional version. The new technique, which utilises a single polarity signal on a separate path, achieves ~15% delay reduction compared with the conventional static CMOS design     

Analog VLSI Circuit Implementation of an Adaptive Neuromorphic Olfaction Chip

In this paper, we present the analog circuit design and implementation of the components of an adaptive neuromorphic olfaction chip. A chemical sensor array employing carbon black composite sensing materials with integrated signal processing circuitry forms the front end of the chip. The sensor signal processing circuitry includes a dc offset cancellation circuit to ameliorate loss of measurement range associated with chemical sensors. Drawing inspiration from biological olfactory systems, the analog circuits used to process signals from the on-chip odor sensors make use of temporal "spiking" signals to act as carriers of odor information. An on-chip spike time dependent learning circuit is integrated to dynamically adapt weights for odor detection and classification. All the component subsystems implemented on chip have been successfully tested in silicon     

Current-mode CMOS multiplier/divider circuit operating in linear/saturation regions

A CMOS current-mode analog multiplier/divider circuit is presented. It is suited to standard CMOS fabrication and can be successfully employed in a wide range of analog signal processing applications. Measurement results for a 0.5 μm CMOS test chip prototype verify the approach employed. The circuit consumes 120 μW using a single supply voltage of 1.5 V and requires a silicon area of 150 × 140 μm.     

CMOS analog front end of a transceiver with digital echocancellation for ISDN

A CMOS analog front-end which contains a novel pulse-shaping circuit, an extremely linear-line-driver state, an oversampling second-order noise-shaping coder, and a wake-up signal detector is discussed. An analog front-end for 4B 3T coded signals is realized in a 2.5-μm CMOS technology and operates up to 4.5 km with 0.4-mm-diameter lines, needing only one 5-V power supply. It is possible to transmit 2B 1Q coded signals also, using a modified pulse-shaping circuit     

具有视网膜仿生处理功能的CMOS图像传感器

借鉴生物视网膜进行图像采集和处理的结构及功能,设计了具有视网膜仿生片上信号处理电路的智能CMOS图像传感器(CIS)。像元内的仿生处理电路主要由自适应光接受器、滤波网络和减法运算电路3部分构成;CIS采用结构简单的空间滤波电阻网络和基于运算放大器的减法电路分别模拟水平细胞和双极细胞的功能,实现图像的边缘检测。在Chartered 0.35μm 2P4M CMOS工艺参数下,对各单元电路及6×6 CIS阵列进行仿真。