To optimize electrical properties of the ultrathin (1.6 nm)nitride/oxide gate stacks with bottom oxide materials andpost-deposition treatment

The electrical properties affected by the bottom oxide materials and the post-deposition treatment on the ultrathin (down to 1.6 nm) nitride/oxide (N/O) stacks, prepared by rapid thermal chemical vapor deposition (RTCVD) with two-step NH₃/N₂O post-deposition annealing, for deep submicrometer dual-gate MOSFETs have been studied extensively. N/O stack with NO-grown bottom oxide exhibits fewer flat-band voltage shifts and higher hole and electron mobility, but suffers from worse leakage current than that with conventional O₂-grown bottom oxide. In post-deposition treatment, increasing NH₃ nitridation temperature can effectively reduce the equivalent oxide thickness (EOT) and improve leakage current reduction rate, but can result in worse mobility. Furthermore, the subsequent N₂O annealing eliminates the defects and offers a contrary effect on the N/O stack in comparison with the NH₃ nitridation step     

Formation of high-quality oxide/nitride stacked layers on ruggedpolysilicon electrodes by rapid thermal oxidation

It is demonstrated that the use of rapid thermal oxidation (RTO) of thin Si₃N₄ films deposited on rugged poly-Si electrodes greatly improves the reliability of the films, compared to conventional wet (steam) oxidation. Superior TDDB characteristics and suppression of capacitance loss during high-field stress have been achieved by RTO     

Determination of the electrical properties of thermally grown ultrathin nitride films

The aim of this work is to obtain the electrical properties of a leaky 2 nm ultrathin thermally grown nitride film using the classical HF C(V) measurements. The substrate Si (1 0 0) surface cleaned in UHV is nitrided in a low pressure of nitric oxide (NO) gas at 1050°C. This film is characterized by Auger electron spectroscopy (AES), fourier transform infra red spectroscopy (FTIR), transmission electron microscopy (TEM) and electron energy loss spectrum (EELS). The deposition of a self-assembled insulating monolayer of organic molecules (octadecyltrichlorosilane) on the nitride gives rise to a metal–insulator–semiconductor (MIS) structure, which permits to obtain the electrical properties of the ultrathin nitride film.     

Electrical properties of ultrathin oxide grown by high pressure oxidation and N2O nitridation for ULSI device applications

For the first time, the feasibility of ultrathin oxides grown by high pressure oxidation (HIPOX) technology in O₂ ambient and nitrided in N₂O ambient with rapid thermal processing has been investigated in order for them to be used as a gate oxide of ULSI devices. The dielectric breakdown electric field (E _BR) and the midgap interface trap density (D _itm) of the nitrided-HIPOX oxide are ?13:9MVcm^?1 and 2 × 10¹⁰cm^?2eV^?1 respectively which are almost the same as those of the control oxide and the nitrided-control oxide. The time-tobreakdown (t_BD) of the nitrided-HIPOX oxide is longer than that of the control oxide at low electric field (<10^?4 A cm^?2) owing to the combination of nitrogen and defects near the Si?SiO₂ interface during nitridation. The lifetimes of the nitrided-HIPOX oxides increase initially, reaching a maximum value of 1:2 × 10⁹ s at a stress current density of 1 × 10^?6 A cm^?2,corresponding to over 10 years, and then decrease as nitridation proceeds.     

High-quality ultrathin (1.6 nm) nitride/oxide stack gatedielectrics prepared by combining remote plasma nitridation and LPCVDtechnologies

Ultrathin nitride/oxide (N/O) gate dielectric stacks with equivalent oxide thickness of 1.6 nm have been fabricated by combining remote plasma nitridation (RPN) and low pressure chemical vapor deposition (LPCVD) technologies. NMOSFETs with these gate stacks exhibit good interface properties, improved subthreshold characteristics, low off-state currents, enhanced reliability, and about one order of magnitude reduction in gate leakage current to their oxide counterparts     

High-quality oxide/nitride/oxide gate insulator for GaN MISstructures

We report on a SiO₂/Si₃N₄/SiO₂ (ONO) gate insulator stack deposited on GaN by jet vapor deposition (JVD) technique. Capacitors fabricated using the JVD-ONO on GaN are characterized from room temperature to 450°C using capacitance-voltage (C-V), current-voltage (I-V), AC conductance, and constant-current stress measurements. We find excellent operating characteristics over the measured range, most notably: (1) very low leakage current, (2) extremely high hard-breakdown strength, (3) low interface-trap density, and (4) low net dielectric-charge density. Moreover these performance figures remain well within acceptable limits even for operating temperatures as high as 150°C. In addition, we measure both the capture cross-section of the interface traps and the surface-potential fluctuation at the GaN/ONO interface. All results suggest that JVD-ONO is an excellent choice for a gate dielectric in GaN-based MISFETs     

Formation of high quality ultrathin oxide/nitride (ON) stackedcapacitors by in situ multiple rapid thermal processing [DRAMcells]

High quality, ultrathin (<30 Å) SiO₂/Si₃ N₄ (ON) stacked film capacitors have been fabricated by in situ rapid-thermal multiprocessing. Si₃N₄ film was deposited on the RTN-treated poly-Si by rapid-thermal chemical vapor deposition (RTCVD) using SiH₄ and NH₃, followed by in situ low pressure rapid-thermal reoxidation in N₂O (LRTNO) or in O₂ (LRTO) ambient. While the use of low pressure reoxidation suppresses severe oxidation of ultrathin Si₃N₄ film, the use of N₂O-reoxidation significantly improves the quality of ON stacked film, resulting in ultrathin ON stacked film capacitors with excellent electrical properties and reliability     

Electrical properties of zinc oxide sputtered thin films

ZnO thin films were deposited on silicon substrate by rf magnetron sputtering from metallic zinc target. The electrical properties of ZnO are currently being studied. In this work, measurements of the ac conductivity properties of ZnO sandwich structures with silver and platinum electrodes are reported. The frequency dependence of both the ac conductivity and dielectric constant of thin films of ZnO have been investigated in the frequency range 5 kHz-13 MHz. It is shown that the total ac conductivity σ(ω), obeys the equation σ(ω)=Aω^S where s is an index which increases with frequency and decreases with temperature. It appears that for ZnO films, the conduction mechanism is thermally activated and both the overlap large polaron tunnelling and the correlated barrier-hopping of charge carrier over localized states fit the experimental data. The dielectric constant, ε_r, lies in the range 8-9 at room temperature and is independent of the frequency in the dielectric thin films.     

Electrical and physical properties of ultrathin reoxidized nitridedoxides prepared by rapid thermal processing

A systematic study of the correlations between electrical and physical properties of nanometer-range reoxidized nitrided oxide films is reported. Rapid thermal processing was applied to the full fabrication process 7.7-nm-thick oxides nitrided at various conditions were reoxidized at 900-1150°C for 15-600 s. Nitridation- and reoxidation-condition dependences of charge-trapping properties, i.e. the flat-band voltage shift and the increase of midgap interface state density induced by a high-field stress, were studied. The hydrogen concentration in the film and the nitrogen concentration near the Si-SiO ₂ interface were measured by secondary ion mass-spectroscopy and Auger electron spectroscopy respectively. It was shown that striking improvement of the charge-trapping properties by rapid reoxidation is achieved by the reducing of hydrogen concentration while keeping the nitrogen concentration near the interface unchanged     

Electrical qualification of new ultrathin integration techniques

The aim of this paper is to analyze the feasibility of ultrathin packages through the electrical qualification of the technological process used, i.e. mechanical lapping. It considers polysilicon bipolar transistors which thickness can reach values lower than 10 μm. Forward mode and reverse mode characterizations show no significant degradation of pertinent characteristics, thus allowing to find applications in new compact packaging concept.     

Double polysilicon plate capacitors with oxide/nitride insulator

The letter describes the fabrication procedure and the electrical properties of a double polysilicon plate capacitor with composite SiO2/Si3N4 insulators. The presence of the Si3N4 layer allows elimination completely of low-voltage breakdown events and reduces the leakage current to the 10?9 A/cm2 level. Different layout configurations are compared based on the evaluation of experimental data.     

Dual-metal gate CMOS technology with ultrathin silicon nitride gatedielectric

We report the first demonstration of a dual-metal gate complementary metal oxide semiconductor (CMOS) technology using titanium (Ti) and molybdenum (Mo) as the gate electrodes for the N-metal oxide semiconductor field effect transistors (N-MOSFETs) and P-metal oxide semiconductor field effect transistors (P-MOSFETs), respectively. The gate dielectric stack consists of a silicon oxy-nitride interfacial layer and a silicon nitride (Si₃N₄) dielectric layer formed by a rapid-thermal chemical vapor deposition (RTCVD) process. C-V characteristics show negligible gate depletion. Carrier mobilities comparable to that predicted by the universal mobility model for silicon dioxide (SiO₂) are observed     

Eyring acceleration model in thick nitride/oxide dielectrics

A kinetic model is developed, which can predict failure times in thick nitride/oxide dielectric stacks at elevated temperatures. It is shown that failure time depends on the applied bias stress and temperature and, in the general case, obeys a two-stress Arrhenius-type relationship known as an Eyring acceleration model:

where t_f is the failure time before charge saturation condition occurs, k is the Boltzmann constant, T is the absolute temperature, ΔH is the activation energy, M and N are the voltage and time dependent parameters, respectively, V_STRESS is the externally applied voltage stress and B is a proportionality constant. Furthermore it is demonstrated that the obtained kinetic equation is physically related to the nitride conduction, described by Frenkel–Poole equation.     

Plasma etching optimization of oxide/nitride/oxide interpolydielectric breakdown time in flash memory devices

The breakdown time of flash memory oxide/nitride/oxide (ONO) layer t_bd under positive constant current stressing has been found to be closely related to the cumulative extent of (over)etch of the tungsten silicide, control polysilicon, and ONO layers, i.e., Σ(ΛOE). An empirical first-order relation between t_bd and Σ(ΛOE) has been derived to facilitate the plasma etch recipe optimization. This has led to a four-fold increase in the average t_bd across a 200-mm wafer to 208 s. More importantly, the spread in t_bd has been tightened to ~5%, which is down from ~54%     

Microstructure evaluation and mechanical properties of nanolayered chromium nitride/tungsten nitride coating

Chromium nitride (CrN) and tungsten nitride (WN) multilayer coating were fabricated by radiofrequency (rf) magnetron reactive sputtering technique. These two nitride coatings were deposited sequentially with a dual-gun system, and an alternating nanolayered CrN/WN coating was derived. The bilayer period, one CrN and one WN layer, of the multilayer was controlled at 10 nm and 24 nm, respectively. The microstructure of the CrN/WN nanolayered coatings was inspected by scanning electron microscopy (SEM) and transmission electron microscopy (TEM). Elemental distribution and periodic feature of the nanolayered coatings were revealed by the Auger electron depth profiling analysis. Nanoindentation technique was employed to evaluate the mechanical properties, including hardness and Young’s modulus. The nanolayered CrN/WN coatings exhibited a high hardness around 30 GPa, which was superior to that of the CrN single-layer coating. The nanolayered structure with confined grains of the nitrides in the nano range was beneficial to the enhancement of the mechanical performance for the multilayer coating.     

Electrical properties of carbon nitride thin films: Role of morphology and hydrogen content

The influence of hydrogen content and ambient humidity on the electrical properties of carbon nitride (CN_x) films deposited by reactive magnetron sputtering from a graphite target in Ar discharges mixed with N₂ and H₂ at a substrate temperature of 350°C have been investigated. Carbon films deposited in pure Ar exhibit a dark resistivity at room temperature of ∼4 × 10⁻² Ωcm, while the resistivity is one order of magnitude lower for CN_0.25 films deposited in pure N₂, due to their denser morphology. The increasing H₂ fraction in the discharge gas leads to an increased resistivity for all gas mixtures. This is most pronounced for the nitrogen-free films deposited in an Ar/H₂ mixture, where the resistivity increases by over four orders of magnitude. This can be related to a decreased electron mobility as H inhibits the formation of double bonds. After exposure to air, the resistivity increases with time through two different diffusion regimes. The measured electrical properties of the films are related to the apparent film microstructure, bonding nature, and ambient humidity.     

Simulation of electronic structure of Si–Si bond traps in oxide/nitride/oxide structure

Numerical simulation using MINDO/3 was performed to study the electronic structure of Si–Si bond traps in the silicon oxide/nitride/oxide structure. Results show that the neutral diamagnetic Si–Si bond in Si₃N₄ can capture both electrons and holes. Simulation results also suggest that the creation of charged diamagnetic defect pairs is unfavorable in Si₃N₄. Electron and hole trapping models are also proposed for the Si–Si bond.     

Tunneling leakage current in ultrathin (<4 nm) nitride/oxidestack dielectrics

The leakage current in high-quality ultrathin silicon nitride/oxide (N/O) stack dielectric is calculated based on a model of one-step electron tunneling through both the nitride and the oxide layers. The results show that the tunneling leakage current in the N/O stack is substantially lower than that in the oxide layer of the same equivalent oxide thickness (EOT). The theoretical leakage current in N/O stack has been found to be a strong function of the nitride/oxide EOT ratio: in the direct tunneling regime, the leakage current decreases monotonically as the M/O ratio increases, while in the Fowler-Nordheim regime the lowest leakage current is realized with a N/O EOT ratio of 1:1. Due to the asymmetry of the N/O barrier shape, the leakage current under substrate injection is higher than that under gate injection, although such a difference becomes smaller in the lower voltage regime. Experimental data obtained from high quality ultrathin N/O stack dielectrics agree well with calculated results     

Interface structure of ultrathin oxide prepared by N/sub 2/O oxidation

With X-ray photoelectron spectroscopy (XPS) measurements, we found in the N/sub 2/O-grown oxide that the nitrogen incorporation should involve the NO or N reaction with the Si-Si bond and P/sub b/ centers at the interface. Consequently, nitrogen content is very low and accumulated mainly at the interface. In addition, we found that the nitrogen atoms at the interface exist in the form of Si-N bonding and the interface oxynitride layer is a mixture of SiO/sub 2/ and Si/sub 3/N/sub 4/ clusters. This structure will result in several undesirable effects. It will give rise to the permittivity and bandgap fluctuations at the interface and hence induced gigantic surface potential fluctuation and mobility degradation in the channel of MOS devices. This bonding structure also explains the interface trap generation during the electrical stressing. The sources of trap generation are attributed to the Si-Si bonds, P/sub b/ centers, and nitride-related defects due to the over-constrained silicon atoms in the Si/sub 3/N/sub 4/ clusters at the interface.     

A high-quality stacked thermal/LPCVD gate oxide technology for ULSI

By stacking thermal and high-quality LPCVD (low-pressure chemical vapor deposition) SiO₂ films, gate oxides with very low defect densities are demonstrated. Whereas previous reports suggested that a thick layer of LPCVD oxide can improve the stacked gate oxide defect density, it is demonstrated that even 25 Å of LPCVD oxide is sufficient to dramatically reduce the defect density compared to thermal oxide films. The projected scaling limit for this technology is estimated to be as low as 70 Å for the total stack thickness. An optimized thermal/LPCVD oxide technology is very promising as the gate dielectric for sub-half-micrometer CMOS technology