一种消除伴生调幅的光源调频型相位生成载波解调方法

为了克服伴生调幅对光源调频型相位生成载波(PGC)解调方法的影响,提出一种基于双路干涉信号和微分-交叉相乘(DCM,differential-cross multiply)的PGC解调方法.通过3×2耦合器引入双路干涉信号,直接调制光源频率获得相位载波.实验结果表明,新方法较好地消除了光源伴生调幅的影响.对于4 rad...     

干涉型光纤传感的相位载波调制解调算法

相位载波调制解调算法是干涉测量的关键技术之一。阐述了相位载波的调制解调原理,说明了相关参数的最佳选取数值,介绍了两种传统的相位载波解调算法,描述了相位载波算法存在的有限的动态范围问题、伴生调幅问题、载波相位延迟问题和相应的解决办法。最后总结相位载波调制解调算法的问题并展望了光纤传感器的发展趋势。     

一种消除伴生调幅影响的PGC解调方法

为了克服内调制时伴生调幅现象对相位生成载波解调结果的影响,提出了一种相位生成载波解调改进算法。通过利用干涉信号中的三次谐波分量和基频分量进行解调,有效地消除了伴生调幅对解调结果的影响。改进后的算法减少了一路混频信号的产生,降低了数字解调时占用的内存及系统的采样频率。给出了改进算法的Matlab仿真和CCS硬件仿真实验结果,分析验证了算法的可行性。     

基于声表面波延迟线的相位解调器设计

该文提出了一种基于声表面波延迟线的相位解调器,其原理是利用声表面波延迟线将调相信号转换为调幅信号,并采用“延迟相加”的方法进行解调。该延迟线实现了频率2.695～3.000 GHz内1μs的延迟时间,解调器可以实现调制速率为500 kHz和1 MHz的二进制相移键控(BPSK)调制信号的解调。     

基于基频混频的相位生成载波调制解调方法研究

提出了干涉型光纤传感器的相位生成载波(PGC)解调的一种改进方法。在传感信号的幅度较小的情况下,该解调方法只由基频信号对输入信号混频,就可以得到与原始传感信号波形成正比的信号,从而提高整个解调过程的效率。仿真分析及实验结果都验证了改进算法的可行性。在基于马赫-曾德尔干涉仪(MZI)以及外调制方式的信号检测实验中,采用该解调方法所得信号和原信号相关系数达0.99以上。     

基于同步载波复原的干涉相位生成载波解调算法

为了有效消除载波延迟对相位生成载波(PGC)算法的影响,提出了一种基于同步载波复原的混频基频、二倍频信号生成方法,直接从干涉信号中提取出载波信息并进行同步载波复原。阐述了该方法的生成原理,并通过理论分析、数值计算与仿真解调等手段对相位延迟的影响进行了详细的分析。仿真与实验结果表明,基于同步载波复原方法获得的混频信号与干涉信号完全对齐,可以保证PGC算法实现稳定、精确的解调。     

干涉型光纤水听器相位载波调制及解调方案研究

本概述了Ｍａｃｈ－Ｚｅｈｎｄｅｒ干涉型光纤水听器两种不同的相位载波调制（ＰＧＣ）原理，着重分析了在直接调制半导体激光器实现相位载波的信号解调技术中伴生调幅的影响及解决办法，指出采用直接调制光源实现相位载波技术是将来构成全光纤干涉型水听器系统的优选方案。     

基于相位生成载波解调的光纤FP传声器的研究

本文针对基于相位生成载波解调的光纤法布里-珀罗(Fabry-Perot,FP)传声器展开了研究。经过反正切函数,提取传声器的相位信息,降低了激光器对信号的影响,实现了声信号的还原。通过采用数字化归一化参数实时估计方法和相位累加算法,分别减小了信号对相位调制深度的依赖性和消除反正切函数对信号幅度的限制。在实验中,通过采用对比法,测试了基于相位载波生成解调的光纤FP传声器的性能。实验结果表明,基于相位载波生成解调的光纤FP传声器的灵敏度可达273m V/Pa@1k Hz,其频率响应为50Hz^5k Hz@±3d B。本文的研究能够很好的应用于语音通讯和声探测等领域。     

匹配型迈克尔逊干涉结构中PZT相位调制对PGC解调算法的影响

通过对相位生成载波(PGC)解调算法的仿真以及参考大量相关文献,可以发现调制度C对PGC解调结果有着极其重要的影响。而调制度C的大小由压电陶瓷PZT(Piezoelectric Transducter)对光路实际产生的相位调制决定,因此,对PZT光相位调制器相位调制常数的校准以及实际产生的相位调制计算很重要。其中对于光相位调制器相位调制常数的校准,可以根据PZT的特性,对PZT施加固定频率的三角波电压,观察干涉信号的变化。通过分析匹配型迈克尔逊干涉仪的PZT调制方式,给出计算调制度C的公式,并分析了调制方式对载波调制度大小和相位的影响,得出PZT对光路信号调制两次,与PZT的调制度两次叠加基本相等,但是会对载波基频增加一个固定的相位延迟,对调制解调算算法有影响,需计算其具体大小,在运算时消掉其影响。     

相位敏感OTDR系统的信号解调方法

提出了一种改进的关于相位敏感光时域反射计(OTDR)系统的信号解调方法.从理论上阐述了该方法的原理,分析了该方法中关键参数(平均次数、滑动窗口和相减间隔)的取值对相位敏感OTDR系统信号处理结果的影响,并且总结了它们取值的指导依据。与常规的数字平均方法对比,利用该方法进行数据处理,有效地解调出扰动信号,进一步说明该方法的可行性.结果表明,该方法根据信号的波动特征将原始数据进行分组,提高了各组数据的相关性,从而明显改善了系统的信噪比,对长距离相位敏感OTDR系统性能的优化有一定的指导意义.     

Static Phase Offset in a Multiplying Phase Detector

This article analyzes the static phase offset $DeltaPhi_{O}$ of a Gilbert cell phase detector, and attributes the majority of the offset to intrinsic channel transit time. A 6.5 GHz phase detector fabricated in a standard 0.18 $mu{rm m}$ CMOS technology is used for the study. The static phase offset is broken down into layout and intrinsic contributions, and a simple model is used to calculate the intrinsic component. The use of analytical equations for current and intrinsic phase offset results in prediction of the intrinsic static phase offset to within 12% for the current ranges considered. The use of the intrinsic model with extracted parasitics is then shown via analysis, simulation and experimental data to be useful in predicting the phase detector static phase offset. The analysis, confirmed by measurements, indicates the degree to which the static phase offset can be reduced by increasing the tail bias current.      

自偏置锁相环的相位噪声分析

自偏置锁相环被提出以来,被认为能够以简单的电路结构降低锁相环的环内分频比从而改善环路带宽内的相位噪声。从噪声的相关性出发,分析了信号经过自偏置电路后对相位噪声的影响,并通过计算自偏置锁相环的相位传递函数得到其相位噪声模型,对比于传统单环式锁相环结构,其环内分频比并未降低。通过设计一2. 28～2. 52GHz 的自偏置锁相环,对其相位噪声进行测试并与传统单环和偏置式锁相环进行比较,测试结果也表明自偏置锁相技术并不能降低锁相环的带内相位噪声。     

Optical Phase Locking by Local Oscillator Phase Dithering

A new type of optical phase-locked loop (OPLL), called the dither loop, is mathematically analyzed. The dither loop extracts a phase-error signal by applying a small phase disturbance to the local oscillator laser, and synchronously demodulating the resulting power fluctuation in the output signal of the receiver. The dither loop is superior to other OPLL designs, because it does not need the transmission of a residual carrier, it employs a 180deg/3-dB hybrid, an ac-coupled front end, and it accepts a large variety of input signals. Furthermore, in a dither loop, the amount of power which is fed to the phase-locking branch can be adaptively controlled within the receiver. The analysis first focuses on an expression for the phase detector gain in a dither loop. Using a linearized model, the phase-error variance due to phase dithering, white frequency noise induced phase noise and shot noise is evaluated. A simplified expression for the power penalty generated by the phase dither signal is presented. In a more complex calculation, the overall power penalty due to phase dithering and the residual phase error is found. This allows us to synthesize a design rule for dither loops with optimum performance measures. The design rule determines all relevant system parameters, based on specified values of the system bit rate, the laser linewidth, the photodiode responsivity and the required bit-error rate     

时序测相法测相精度的改进研究

高精度微波相位测试在许多情况下非常重要。本文对幅度权重和相位权重两种时序相干测相方法进行了比较研究,并结合两种方法各自的优点,提出一种新的混合方法。为了提高相干精度,还采取了参考信号通道和待测信号通道幅度自动平衡的措施。这一新方法结合改进措施,使测相精度明显提高。实验结果表明,本系统对各种可能被测相位的最大测相误差小于±1．5°。     

Phase change

Samsung says it has started the first commercial production of phase-change memory chips. Known as PRAM, this nonvolatile memory technology holds bits according to the conductive phase of a special material, which melts to change phase.     

相移干涉计量中相移器的原路相干相位检测标定

介绍一种原路相干相位检测的标定方法,该方法具有很高的精度,对相移器的线性没有特别要求,相移器的标定与使用是同一光路,消除了标定光路与使用光路不同所带来的误差     

Robust Time and Phase Synchronization for Continuous Phase Modulation

A novel joint timing and phase-recovery technique is proposed for continuous phase modulation (CPM) systems based on Kalman filtering and an approximate representation of CPM signals with nonorthogonal exponential expansions (nOEE). Compared with existing techniques, the proposed synchronizer requires a less complex front-end processor, and can achieve reliable acquisition performance with a shorter preamble. The asymptotic stability and convergence of the proposed synchronizer is analyzed, including the effect of statistical channel-modeling errors on the convergence characteristics. The selection of suboptimal nOEEs and the design of triple-initialized Kalman filters are also discussed. Both theoretical and simulation results show that the proposed synchronizer is robust in acquiring and tracking both the time shift and the phase offset on either time-invariant or time-variant channels.     

Low Complexity Carrier Phase Tracking Decoders for Continuous Phase Modulations

Phase tracking capability is incorporated into two sequence estimation decoders for continuous phase modulations. One decoder employs the Viterbi algorithm; the other uses a reduced-survivor approach proposed earlier by one of the authors [11] for the more bandwidth efficient of these modulations. Computational complexity with the simplest of the joint data/phase algorithms is only marginally greater than that required for the equivalent decoding algorithm employing an externally derived carrier phase reference as supplied by a conventional carrier recovery circuit. Simulations with representative partial response modulations demonstrate the phase synchronization and tracking capabilities of the decoders. High SNR losses relative to an optimal receiver having perfect phase knowledge are found to be small (∼ 1 dB).     

Phase Detectors/Phase Frequency Detectors for High Performance PLLs

Phase Frequency Detectors (PFDs) for use in clock distribution PLLs and Phase Detectors (PDs) for clock recovery PLLs that we have proposed recently to achieve high performance are reviewed and discussed. For the PFD, operating speed limitation and phase detecting characteristics are improved with two kinds of approaches, i.e., gate/logic design and configuration design. For the PD, a simple compensation technique to prevent the deterioration of the phase detecting characteristics by D-F/F and a new PD with delay cell of VCO replica are proposed to reduce the jitter caused by PD. By SPICE simulations and experiments, it is confirmed that the maximum operating speed of PFD is improved to more than twice of conventional one and the jitter caused by PD is reduced to a minimum level.     

一种相位精确可调的四路正交信号发生器

设计了一种相位精确可调的四路正交信号发生器,由相位精确调节器和二分频器构成。相位精确调节器通过控制尾电流源的导通产生可编程的电流,再使该电流转换成偏置电压叠加在时钟信号上,以此来调节二分频器产生的四路信号的相位差,使其相位精确互差90°。电路采用SMIC 0.13 μm CMOS工艺进行仿真验证。结果表明,在电源电压为1.2 V,偏置电流为7.2 μA,且电平信号的选通位数n=6时,产生的四路正交信号的误差精度可达±0.1°,调相范围达±3.6°。