A Current Mirror for Low Voltage, High Performance Analog Circuits

A current mirror for low voltage analog and mixed mode circuits is proposed. The current mirror has high input and output voltage swing capability and can operate at ±1.0 V supply. P-Spice simulations confirm the input current range of 1 A to 500 A with 2.5 GHz bandwidth for the proposed current mirror. Adaptive biasing increases the input voltage swing capability and decreases the undesired offset current. Resistive and capacitive compensation are used to increase its bandwidth.     

A Switched Opamp-Based Bandpass Filter: Design and Implementation in a 0.35 μm CMOS Technology

A fully differential SC bandpass filter (central frequency, 58 kHz; Q = 15; and voltage gain, 8) based on the switched-opamp approach is designed and implemented in this work. The filter operates from a single 1 V supply voltage and is realized in a 0.35 m CMOS technology. It has been characterized with a sampling frequency of 1 MHz and its power consumption is about 230 W. As a main internal filter component, an appropiate switched opamp was also designed. Its common-mode feedback circuit was implemented by using an error amplifier and sampling of the output common-mode voltage is carried out by applying a DC offset to level shift the common-mode sample. It provides an accurate common-mode output for a wide temperature and supply voltage ranges.     

Class AB Output Stages for Low Voltage CMOS Opamps with Accurate Quiescent Current Control by Means of Dynamic Biasing

Two new class AB output stages for CMOS op-amps are proposed with accurate quiescent current control. The second proposed stage also provides accurate control of the minimum current through the output transistors. The proposed stages can be operated with a supply voltage close to a transistor threshold voltage. A dynamic biasing scheme allows them to operate in a wide range of supply voltages. Using these stages two opamps have been designed using a 0.8 m CMOS technology. Experimental results show a unity gain frequency of 15 MHz with 290 A of quiescent current and a 10 pF load, using a 1.5 V single voltage supply.     

Multi-Value Voltage-to-Voltage Converter Using a Multi-Stage Symmetrical Charge Pump for On-Chip EEPROM Programming

A fully integrated multi-stage symmetrical structure chargepump and its application to a multi-value voltage-to-voltage converterfor on-chip EEPROM programming are presented. The multi-valuevoltage-to-voltage converter is designed to offer two output voltages,power supply and triple power supply alternatively, which is neededfor a memory array. A dynamic analysis of the multi-stage symmetricalstructure charge pump and an optimization design in terms of circuitarea are also given. The circuit is implemented in a 1.2 CMOSprocess and the measurement results show that a voltage pulse as shortas 5 s with a rise time of 3 s is obtained. For a 5 V powersupply and with a resistive charge of 100 k, the programmingoutput voltage can reach as high as 11 V and output current forprogramming is over 110 A, which are high enough to program thememory cell.     

High-Speed High-Precision CMOS Current Conveyor

In this paper a new class-AB CMOS second generation current conveyor (CCII) based on a novel high-performance voltage follower topology is proposed. Post-layout simulation results from a 0.8 m design supplied at 3.3 V show very low resistance at node X (<50 ), high frequency operation (100 MHz), high precision in the voltage and current transference and reduced offset. As application examples, a V-I converter and a current feedback operational amplifier (CFOA) have been implemented. The latter presents slew-rate levels higher than ±100 V/s.     

An Analog Correlator for a WCDMA Receiver

A prototype analog correlator structure suitable for a WCDMA receiver was implemented. The advantages of this correlator are low power consumption compared to a digital correlator and small chip area. The target is to use such correlator as parallel correlators (fingers) of a RAKE receiver. The analog baseband correlator utilizes passive MOS-multipliers, a first-order low-pass continuous-time oversampling sigma–delta analog-to-digital converter and a second-order sinc type of decimation filter (for both I and Q input paths). The modulator sampling rate is twice the chip rate with oversampling ratios of 8–512 depending of the PN code length. The circuit was implemented in 0.8 m CMOS-technology with a supply voltage of 2.8 V. The layout size is 345 m×686 m and the current drain is approximately 370 A.     

A Design of a Low-Voltage Current-Mode Fully-Differential Analog CMOS Integrator Using FG-MOSFETs and Its Implementation

In the field of analog signal processing, there is a strong need for low-voltage and low-power integrated circuits. Especially in the mobile communication circuitry, an analog signal processing circuit must be fed by dry batteries of 1–1.5 V. This paper presents a design and implementation of a current-mode fully-differential analog CMOS integrator operable with such a low supply voltage. This integrator is built with a cross-coupled matched pair of 3-input FG(Floating Gate)-MOSFETs, a matched pair of 2-input FG-MOSFETs, and four bias current sources. In this circuit, both a low apparent threshold voltage of FG-MOSFETs and voltage signal summation at the floating gates are effectively utilized to enable the circuit operation with a low supply voltage and to simplify the circuit configuration. The influence of the common-mode signal and noise to the signal processing are minimized by adopting fully-differential structure. The performance of the proposed integrator circuit is predicted by theoretical analysis and by HSPICE simulations. The circuit works as an integrator in the frequency range 4–750 MHz at a 1.5 V supply voltage and dissipates DC power of about 70 W. The proposed circuit was fabricated by a Motorola 1.2 m double-poly CMOS process in the chip fabrication program of VLSI Design and Education Center (VDEC).     

A 1.2 V Rail-to-Rail Analog CMOS Rank-Order Filter with k-WTA Capability

In this paper, we design a rank-order filter with k-WTA capability for 1.2 V supply voltage. The circuit can find a rank order among a set of input voltages by setting different binary signals. Moreover, without modifying the circuit, the k-WTA function can be easily configured. The circuit has been designed using a 0.5 m DPDM CMOS technology. Seven input voltages are used to verify the performance of the circuit. The results of HSPICE post-layout simulation show that the response time of the circuit is 10 s for each rank-order operation, the input dynamic range is rail-to-rail, and the resolution is 10 mV for 1.2 V supply voltage. An experimental chip has been fabricated, in which accuracy of the comparator is measured as 40 mV for low-voltage operation. The dynamic power dissipation of the chip is 550 W.     

A silicon potentiometer for hearing aids

An angledetector with a digital output is described. The component is meant as an alternative to the traditional slide potentiometer used as volume control in many hearing aid applications. The component is based on the use of magnetic field sensitive MOSFET's (MAGFET's) detecting the position of a tiny bar magnet placed above a silicon chip. Because of the galvanic separation between the anglesetting bar magnet and the electrical circuit, this component is insensitive to the rather hostile environment hearing aids are exposed to. The lifetime of the component is thereby increased significantly. The electrical circuit contains a switched current A/D-D/A conversion system for offset compensating the MAGFET's and for converting the MAGFET signal currents into a digital output proportional to the input angle. The system can operate with a supply voltage down to 2.3 V. The average current consumption is 1.5 A. The peak current is close to 160 A. The system operates correctly within the clock frequency range of 5 Hz to 25 kHz. It is implemented using a commercially available 1.5 m CMOS process.     

A CMOS Voltage Comparator with Rail-to-Rail Input-Range

A simple new continuous-time CMOS comparator circuit with rail-to-rail input common-mode range and rail-to-rail output is presented. This design uses parallel complementary decision paths to accommodate power-supply-valued inputs. The 2 decision results are combined at a current summing node, converted to a voltage, and buffered to drive voltage loads. The circuit has been realized in an area of 416 m×221 m in a MOSIS 2-micron CMOS technology. Average delay of about 63 ns has been measured at 3 V (1.3 mA), and about 89 ns at 5 V (1.1 mA).     

Low-Power Low-Voltage Class-AB Linear OTA for HF Filters with a Large Tuning Range

This letter presents a new low-voltage class-AB differential linear OTA. The proposed transconductor uses a novel scheme based on two cross-coupled class-AB pseudo-differential pairs biased by a Flipped Voltage Follower [1]. The transconductor has been designed using a 0.8 m CMOS technology to operate at 2 V supply voltage with only 260 W of quiescent power consumption. Simulation results show 90 MHz bandwidth with more than two decades of transconductance tuning range.     

Low Voltage Class AB Output Stage for CMOS Op-Amps Using Multiple Input Floating Gate Transistors

A new class AB output stage for CMOS op-amps is proposed with simple and accurate quiescent current control using floating gate transistors. The proposed stage can be operated with a supply voltage close to a transistor's threshold voltage. Experimental results are provided showing a 15 MHz gain-bandwidth product when it is used as the second stage of an op-amp with 1.5 V supply voltage in a standard 0.8 m CMOS technology.     

Design and Analysis of Built-In Testers for CMOS Switched-Current Circuits

This paper presents the design and analysis of a built-in tester circuit for MOS switched-current circuits used in low-voltage/low-power mixed-signal circuits/systems. The use of the tester can reduce the test length significantly. The developed tester is comprised of a current comparator, a voltage window comparator, and a digital latch. The current comparator is required to have high-accuracy, low-power consumption, simple structure with small chip area, and moderate speed. Results show that the developed current comparator circuit is developed with a small offset current, 0.1 nA, low power consumption, 20 W, and a layout area of 0.01 mm², where the circuit is simulated with the MOSIS SCN 2 m CMOS process parameters and 2 V supply voltage.     

IC Voltage to Current Transducers with Very Small Transconductance

This paper deals with the design of very small ac transconductance voltage to current transducers intended for the design of low frequency continuous-time filters, very large resistors and other applications. The first type of Operational Transconductance Amplifiers (OTA) is based on a triode biased transistor and a current division technique. The second one uses partial positive feedback which allows to reduce transistor dimensions but the sensitivity to transistor mismatches increases. The proposed techniques can be used for the design of high-order low frequency IC filters, ladder or based on biquads, with moderated transistor dimensions while the dynamic range-cutoff frequency performance is comparable to previously reported structures. A 10 Hz third order lowpass ladder filter has been designed with these techniques, and it shows a dynamic range of 62 dB. Besides, a novel biasing technique for capacitive sources coupled preamplifiers is proposed. Experimental results for a prototype, fabricated in a 1.2 m 1 level below 15 _RMS and dynamic range of 63 dB. The power consumption is only 10 watts and the supply voltages are ± 1.5 volts.     

A Very Low Power Consumption, Low Noise Analog Readout Chip for Capacitive Detectors with a Power Supply of 3.3 V

An analog frontend block of a VLSI readout chip, dedicated to high spatial resolution X or beta ray imaging, using capacitive silicon detectors, is described. In the present prototype, an ENC noise of 343 electrons at 0 pF with a noise slope of 28 electrons/pF has been obtained for a peaking time of 10 s, a 37 mV/fC conversion gain, a 3.5 V power supply and a 150 W/channel power consumption.     

Temperature Dependence of Output Voltage Generated by Interaction of Threshold Voltage and Mobility of an NMOS Transistor

Mutual compensation of mobility andthreshold voltage temperature variations mayresult in a zero temperature coefficient (ZTC)bias point of an NMOS transistor. Theconditions under which this effect occurs,stability of this bias point, and thetemperature dependence of the output voltagefor a diode-connected transistor operating inthe vicinity of ZTC point are investigated inthis paper. Some possible applications of thiseffect include temperature sensors with lineardependence of voltage versus temperature, andvoltage and current reference circuits. Thetheory is verified experimentallyinvestigating the temperature behavior of anNMOS transistor realized in 0.35 m CMOSprocess. The design and simulation results ofsimple current and voltage reference circuitsfor implementation in 0.18 m CMOStechnology are given.     

A Low Power Dissipation Technique for a Low Voltage OTA

This paper proposes a novel low power dissipation technique for a low voltage OTA. A conventional low power OTA with a class AB input stage is not suitable for a low voltage operation (±1.5 V supply voltages), because it uses composite transistors (referred to CMOS pair) which has a large threshold voltage. On the other hand, the tail-current type OTA needs a large tail-current value to obtain a sufficient input range at the expense of power dissipation. Therefore, the conventional tail-current type OTA has a trade-off between the input range and the power dissipation to the tail-current value. The trade-off can be eliminated by the proposed technique. The technique exploits negative feedback control including a current amplifier and a minimum current selecting circuit. The proposed technique was used on Wang's OTA to create another OTA, named Low Power Wang's OTA. Also, SPICE simulations are used to verify the efficiency of Low Power Wang's OTA. Although the static power of Low Power Wang's OTA is 122 W, it has a sufficient input range, whereas conventional Wang's OTA needs 703 W to obtain a sufficient input range. However, we can say that as the input signal gets larger, the power of Low Power Wang's OTA becomes larger.     

A 70-MHz Continuous-Time CMOS Band-Pass ΣΔ Modulator for GSM Receivers

A 70-MHz continuous-time CMOS band-pass modulator for GSM receivers is presented. Impulse-invariant-transformation is used to transform a discrete-time loop-filter transfer function into continuous-time. The continuous-time loop-filter is implemented using a transconductor-capacitor (G _m -C) filter. A latched-type comparator and a true-single-phase-clock (TSPC) D flip-flop are used as the quantizer of the modulator. Implemented in a MOSIS HP 0.5-m CMOS technology, the chip area is 857 m × 420 m, and the total power consumption is 39 mW. At a supply voltage of 2.5 V, the maximum SNDR is measured to be 42 dB, which corresponds to a resolution of 7 bits.     

Ultra Low Power CORDIC Processor for Wireless Communication Algorithms

We designed and implemented an ultra low power CORDIC processor which targets the implementation of advanced wireless communications algorithms based on Givens rotations and Householder reflections. We propose a modified CORDIC algorithm and architecture, and we elaborate on the low power architectural and algorithmic techniques for minimizing its power consumption. Our CORDIC implementation consumes, in rotate mode, on average 50 W @ 10 MHz under 1 V supply voltage in a .25 m technology.