Fault detection for multiple-valued logic circuits with fanout-free

The single fault and multiple fault detections for multiple-valued logic circuits are studied in this paper. Firstly, it is shown that the cardinality of optimal single fault test set for fanout-free m-valued circuits with n primary inputs is not more than n + 1, for linear tree circuits is two, and for multiplication modulo circuits is two if n is an odd number or if n is an even number and m > 3, where the optimal test set of a circuit has minimal number of test vectors. Secondly, it is indicated that the cardinality of optimal multiple fault test set for linear tree circuits with n primary inputs is 1 + [n/(m - 1)], for multiplication modulo circuits is n + 1, for fanout-free circuits that consist of 2-input linear tree circuits and 2-input multiplication modulo circuits is not greater than n+ 1, where [x] denotes the smallest integer greater than or equal to x. Finally, the single fault location approaches of linear tree circuits and multiplication modulo circuits are presented, and all faults in th     

FAULT DETECTION TEST SET FOR TESTABLE REALIZATIONS OF LOGIC FUNCTIONS WITH ESOP EXPRESSIONS

The circuit testable realization and its fault detection for logic functions with ESOP （EXOR-Sum-Of-Products） expressions are studied. First of all, for the testable realization by using XOR gate cascade, a test set with 2n ＋ m ＋ 1 vectors for the detections of AND bridging faults and a test set with 2n ＋ m vectors for the detections of OR bridging faults are presented. Secondly, for the testable realization by using ）（OR gate tree, a test set with 2n ＋ m vectors for the detections of AND bridging faults and a test set with 3n ＋ m ＋ 1 vectors for the detections of OR bridging faults are presented. Finally, a single fault test set with n ＋ 5 vectors for the XOR gate tree realization is presented. Where n is the number of input variables and m is the number of product terms in a logic function.     

通用Toffoli可逆门的固定故障测试

可逆电路技术在低功耗芯片和量子通信中广泛使用。目前,大部分学者着重研究可逆电路的合成,对电路的故障测试却很少问津,但是可逆电路的测试在应用中却十分重要。文中构造了一种四输入通用Toffoli门（universal toffoli gate,UTG）用来检测电路故障,这个门可以实现所有基本的布尔逻辑。UTG门可以检测到所...     

Dynamic effects in the detection of bridging faults in CMOS ICs

Dynamic effects in the detection of bridging faults in CMOS circuits are taken into account showing that a test vector designed to detect a bridging may be invalidated because of the increased propagation delay of the faulty signal. To overcome this problem, it is shown that a sequence of two test vectors < T ₀, T ₁ >, in which the second can detect a bridging fault as a steady error, can detect the fault independently of additional propagation delays if T₀ initializes the faulty signal to a logic value different from the fault-free one produced by T ₁. This technique can be conveniently used both in test generation and fault simulation. In addition, it is shown how any fault simulator able to deal with FCMOS circuits can be modified to evaluate the impact of test invalidation on the fault coverage of bridging faults. For any test vector, this can be done by checking the state of the circuit produced by the previous test vector.     

Dynamic-type CMOS four-valued logic circuits

We first briefly introduce the various kinds of basic CMOS four-valued logic circuit that can be suitably employed for circuits with clock pulses. Using these, the design of multiple-valued MAX and MIN circuits with many inputs, each of which has two quaternary figures, are developed. It is shown that the number of MOS transistors required for these circuits can be reduced in comparison to binary circuits having equivalent functions. Successful simulation results using SPICE-2 for the circuit operations are given.     

基于多值模相关性的电流型CMOS电路设计

本文根据模相关性的性质，指出多值模代数系统中模无关。方程组有唯一解，矩阵可逆，函数的规范展开，模运算的完备性之间互为等价关系，并指导了四值单变量查函数的电流型ＣＭＯＳ电路设计，它比传统的成本法优越。     

Multiple fault detection in two-level multi-output circuits

It is often stated that in irredundant two-level logic circuits, a test set for all single stuck faults will also detect all multiple stuck faults. We show by a simple example that this result does not hold for multi-output circuits even when each output function is prime and irredundant. Using a result from the programmable logic array technology, we give an output ordering constraint that, if satisfied during test generation, will make a single stuck fault test set a valid multiple stuck fault test set for irredundant two-level multi-output circuits.     

Design of a modulo p multiplier

Some basic problems on the design of multiple-valued circuits are discussed on the basis of a modulo 5 full-multiplier. It is shown that appropriate transformations at the highest abstraction level may reduce some design constraints. In the case of the mod 5 multiplier, it is possible to alleviate linear dynamics range demands. Moreover it is shown that multiple-valued design may offer some space-time trade-offs with respect to binary.     

Self-timed is self-checking

Self-checking circuits detect (at least some of) their own faults. We describe self-timed circuits, including combinational logic and sequential machines, which either halt or generate illegal output if they include any single stuck-at faults. The self-timed circuits employ dual rail data encoding to implement ternary logic of 0, 1, andundefined states; the fourth state is used to signal illegal output and is shown to result only from certain circuit faults. The self-timed circuits also employ four-phase signaling according to a well-defined protocol of communications between the circuit and its environment; failures due to certain faults prevent the circuit from communicating properly, thus causing the circuit to halt. We show that any single stuck-at fault falls in either the first or the second category, thus providing complete fault coverage through self checking. No hardware needs to be added to our circuits to achieve the complete self-checking property; further, the circuit is guaranteed to never generate a legal but erroneous output if it contains a fault. Minimal hardware is needed to detect that a circuit has either halted or has generated an illegal output.     

基于连续逻辑的十值十进制算术运算电路的设计

本文提出了用ＤＹＬ系列器件构成的直接用十进制进行运算的十值电路。ＤＹＬ器件是一种线性元件,它可以工作于０－３Ｖ范围内的任意信号电压,对信号的分辨率极高,为实现高信息密度的十值电路提供了方便条件。本文提出的电路其工作原理是基于一种我们称之为“赋值－选通”的方法,将可能的输出值全部赋予电路,根据输入信息,通过选通电路直接将计算结果输出,这种赋值－选通法对多值电路的设计有普遍意义。     

谐振隧穿晶体管数字单片集成电路

阐述了谐振隧穿器件构成的与非门、单/双稳逻辑转换电路、或非门、流水线逻辑门、D触发器、静态存储器、多值逻辑和静态分频器等数字单片集成电路,它们具有高频高速、低功耗、多值逻辑、节点少、节省器件、简化电路等显著优势,将是数字集成电路后续小型化最有希望的代表。指出材料生长和芯片工艺制作等问题是其实现工业化生产的瓶颈。综述了国内外在该领域的研究现状和发展趋势,特别是美国已经有高水平的谐振隧穿晶体管数字单片电路问世,我国正在开展少量的研究工作。     

Design of a DTCTGAL circuit and its application

By research on the switch-signal theory for multiple-valued logic circuits, the theory of three essential elements and the principle of adiabatic circuits, a design scheme for a double power clock ternary clocked transmission gate adiabatic logic (DTCTGAL) circuit is presented. The energy injection and recovery can be conducted by the bootstrapped NMOSFET, which makes the circuit maintain the characteristics of energy recovery as well as multiple-valued input and output. An XOR/XNOR circuit based on DTCTGAL is also presented using this design scheme. Finally, using the parameters of a TSMC 0.25 μm CMOS device, PSPICE simulation results indicate that the proposed circuits have correct logic and significant low power characteristics.     

Compact non-binary fast adders using single-electron devices

This paper proposes compact adders that are based on non-binary redundant number systems and single-electron (SE) devices. The adders use the number of single electrons to represent discrete multiple-valued logic state and manipulate single electrons to perform arithmetic operations. These adders have fast speed and are referred as fast adders. We develop a family of SE transfer circuits based on MOSFET-based SE turnstile. The fast adder circuit can be easily designed by directly mapping the graphical counter tree diagram (CTD) representation of the addition algorithm to SE devices and circuits. We propose two design approaches to implement fast adders using SE transfer circuits: the threshold approach and the periodic approach. The periodic approach uses the voltage-controlled single-electron transfer characteristics to efficiently achieve periodic arithmetic functions. We use HSPICE simulator to verify fast adders operations. The speeds of the proposed adders are fast. The numbers of transistors of the adders are much smaller than conventional approaches. The power dissipations are much lower than CMOS and multiple-valued current-mode fast adders.     

Design of C-testable DCVS binary array dividers

Clocked differential cascode voltage switch (DCVS) circuits are dynamic CMOS circuits that have the advantage of being protected against test-set invalidation due to circuit delays and timing skews. The problem of testing nonrestoring and restoring DCVS binary array dividers is discussed. It is shown that a DCVS nonrestoring array divider can be made C-testable with only four or five vectors. These vectors detect all the detectable single stuck-at, stuck-open, and stuck-on faults in the circuit. The additional hardware required to achieve C-testability for an n×n nonrestoring array divider only consists of n-1 two-input XOR gates and one control input. It is also shown that a restoring DCVS binary array divider can be made C-testable with only six vectors, which also detect all the detectable single stuck-at, stuck-open, and stuck-on faults in the circuit. The hardware overhead required for the C-testable design of the n×n restoring array divider consists of n two-input XOR gates and one control input     

Testability and test generation for majority voting fault-tolerant circuits

The testability of majority voting based fault-tolerant circuits is investigated and sufficient conditions for constructing circuits that are testable for all single and multiple stuck-at faults are established. The testability conditions apply to both combinational and sequential logic circuits and result in testable majority voting based fault-tolerant circuits without additional testability circuitry. Alternatively, the testability conditions facilitate the application of structured design for testability and Built-In Self-Test techniques to fault-tolerant circuits in a systematic manner. The complexity of the fault-tolerant circuit, when compared to the original circuit can significantly increase test pattern generation time when using traditional automatic test pattern generation software. Therefore, two test pattern generation algorithms are developed for detecting all single and multiple stuck-at faults in majority voting based circuits designed to satisfy the testability conditions. The algorithms are based on hierarchical test pattern generation using test patterns for the original, non-fault-tolerant circuit and structural knowledge of the majority voting based design. Efficiency is demonstrated in terms of test pattern generation time and cardinality of the resulting set of test patterns when compared to traditional automatic test pattern generation software.     

Robust tests for parity trees

Linear logic circuits are used extensively in digital computing and signal processing systems. They are constructed as regular arrays (for example as cascade or tree circuits), employing linear gates such as Exclusive OR (EOR) and Exclusive NOR (ENOR) gates. Earlier studies on fault diagnosis in linear logic circuits were based on the classical fault model of line stuck-at faults. Transistor stuck-open (SOP) and stuck-on (SON) faults in linear circuits were studied recently, but the effect of signal transients due to circuit delays and time skews in input changes were not considered in the derivation of test sequences. These latter factors are known to cause invalidation of two pattern tests for stuck-open faults. In this article we consider the problem of generating robust tests for linear logic circuits. These tests are not affected by circuit transients caused by delays. A major finding in this paper is that, if the test invalidation problem is redressed by introducing robust tests, the test length becomes a linear function of the depth of the circuit as opposed to the constant number of tests derived in previous studies, by neglecting circuit transients. A lower bound on minimum number of distinct test patterns needed for a tree of EOR gates of depthd is derived. This number depends on the specific implementation of the gate. Robust test-generation procedures are proposed for both single and multiple fault models and their optimalities are argued. Given that every gate in a parity tree is robustly testable, a test sequence that can test for all faults in the circuit, regardless of the nature of gate implementation, is calleduniversal robust test sequence for a parity tree. Finally we propose an optimal universal robust test sequence.     

Differential BiCMOS logic circuits: fault characterization anddesign-for-testability

Merged Current Switch Logic (MCSL) and Differential Cascode Voltage Switch Logic (DCVSL) are two common structures for differential BiCMOS logic family, that have several potential applications in high-speed VLSI circuits. This paper studies the fault characterization of these BiCMOS circuits. The impact of each possible single defect on the behavior of the circuits is analyzed by simulation. A new class of faults which is unique to differential circuits is identified and its testability is assessed. We propose a design-for-testability method that facilitates testing of this class of faults. Two different realizations for this method are introduced. The impact of this circuit modification on the behavior of the circuit in normal mode is investigated     

A cubical logic circuit modelling for reliability studies

A deeper insight into the problem of reliability analysis for combinational logic circuits is presented. Reliability is defined as the probability that the logic circuit correctly processes a given set of inputs. While the straightforward approach to this evaluation requires a formidable amount of computations, the presented approach is fast, easy to implement, memory efficient and applicable to circuits of any size and complexity. This is due to a new concept for logic circuit modelling, which allows the covering of all possible faults in a circuit by a relatively small number of sets of logically equivalent faults.For modelling purposes the excitations of inputs and the states of terminals in logic gates are presented in the form of a state vector. The logically equivalent state vectors are merged to form highest-order cubes which are mapped onto a gate equivalent graph (GEG). According to the connections among gates in the logic circuit this graphical model is extended to the circuit equivalent graph (CEG), which comprises the highest-order cubes for a circuit in the form of appropriate subgraphs, the so called state graphs (SGs).     

基于RT器件的三值与非门、或非门电路设计

共振隧穿（resonant tunnel,RT）器件本身所具有的微分负阻（negative differential resistance,NDR）特性使其成为天然的多值器件，文中利用RT器件的负阻特性,以开关序列原理为指导,设计了基于RT电路的开关模型,实现了更为简单的三值RT与非门和或非门电路,并利用MOS网络模型,通过SPICE软件仿真验证了所设计电路的正确性，该设计思想可推广到更高值的多值电路设计中。     

Universal delay test sets for logic networks

It has been shown earlier that, if we are restricted to unate gate network (UGN) realizations, there exist universal test sets for Boolean functions. Such a test set only depends on the function f, and checks any UGN realization of f for all multiple stuck-at faults and all robustly testable stuck-open faults. In this paper, we prove that these universal test sets are much more powerful than implied by the above results. They also constitute complete delay fault test sets for arbitrary UGN implementations of a given function. This is even true for UGN networks which are not completely testable with respect to the gate or path delay fault model. Our ability to prove the temporal correctness of such circuit realizations comes from the fact that we do not argue the correctness of individual paths, but rather complete path systems