单方向分离式母板互联设计技术

针对电路模块的功能扩展带来的模块对外接口不足的问题,通过对分离式母板互联技术研究,确定了结构上分离的母板互联形式,主要对单方向分离互联母板互联设计、结构设计、印制板设计、可靠性设计等设计技术展开探讨,从一个角度解决了传统母板限制电路模块功能扩展带来的互联问题,实现了电路模块功能的有效扩展。     

基于FPGA的高速同步HDLC通信控制器设计

高级数据链路控制HDLC协议是一种面向比特的链路层协议,具有同步传输数据、冗余度低等特点,是在通信领域中应用最广泛的链路层协议之一.提出实现HDLC通信协议的主要模块-CRC校验模块及'0'比特插入模块的FPGA实现方法.CRC校验模块采用状态机设计方法,而'0'比特插入模块是利用FIFO实现,为HDLC通信控制器的设计提供新的思路.该方法已在Spartan3s400开发板上实现,并能正确传输.     

基于DFA的电脑主机分析

本文以国内电脑为例，对装配零件的固定方式、零件的插入及抓取、零件的对称性等进行DFA（面向装配的设计）过程分析，得出每个零件的在紧固、抓取、插入以及利用操作工具等所用的装配时间，得出装配效率，同时给出重新装配设计的建议，从理论上验证了再设计建议方案的可行性。     

IC芯片大小的完整10A开关模式DC/DC电源由凌特公司提供的高性能模拟解决方案

预制的DC/DC电源(也被称作负载点POL模块)一直在保证着更简单、更小巧和更快速的解决方案.然而,它在满足高密度嵌入式电路板的系统装配要求方面则显出不足.有些POL模块解决方案需要一个外部电感器、多个附加的输入和输出电容器以及补偿电路.它们大多安装在一块小型印刷电路板(PCB)上,并且需要进行手工插入和外观检查以确保可靠性,这是因为电路组件是外露式的,并且容易受损.     

高性能PCle Gen2硬核IP的低成本实现

1 前言 PCIe技术可作为母板级互联(连接安装在母板上的外设)、无源背板互联,以及插入电路板的扩展卡接口等,适用于从工业和医疗到消费类和服务器应用等电子行业的所有领域. PCIe规范于2003年由PCI特殊兴趣组(PCI-SIG)推出,此后不断发展,数据速率和带宽都不断提高.这一规范不但是高端处理器和FPGA中软核知识产权(IP)的主要规范,而且还逐步涉及到FPGA中的硬核IP.以前,主要由高性能和中端FPGA提供这类高级速率和吞吐量支持.     

在嵌入式应用中节省空间的4路Sparc多处理母板——小型母板的计算密度是传统服务器的3倍,所占空间仅为它的三分之一

SPARC engine Ultra AXmp是一种4路Sparc处理器母板,主要用于嵌入式通信和联网应用。具有四个250、300或360MHz Utra-Sparc-ⅡS系列微处理器模块的母板可装入5U高底盘或小的4U定制底盘。多达10块Ultra Axmp母板可放入一个19英寸的齿条机壳,是办公系统母板数的3倍。     

产品电缆自动化设计

针对传统电缆设计中经常出现的设计图纸和最终装配出来的产品不一致、图纸与实物有所不特等问题,提出一种新的电缆设计方法-电缆自动化设计.即利用Unigraphics(简称UG软件系统)中的Routing模块,通过建立的结构装配数学模型进行电缆自动化设计;完成了导线和线束的空间路径设置和调整,并根据线路设计在结构中进行线路布...     

基于FPGA的液晶控制器设计

介绍了一种基于 FPGA 的集成液晶控制器.系统由显示模块和控制模块组成,显示模块(LEM101)为10 bit 多功能通用型器件,内含看门狗(WDT)/时钟发生器,2 种频率的蜂鸣驱动电路,内置显示RAM,及3-4线串行接口.控制器基于1.5万门 FPGA 芯片(Xilinx XC3S1500),易于扩展和升级.利用 Verilog 语言,在 FPGA 芯片中实现了控制模块的设计,通过 GR-XC3S-1500 开发板验证,本设计完全满足对液晶模块的控制要求,并成功应用于光栅测量显示控制系统中.控制模块由四部分组成:存储、译码、串并转换器、输出控制.文章讨论了设计方法和设计过程,给出了部分 Verilog 代码.此外,本设计还创造性地在电源和 FPGA 芯片间插入低成本元件,满足了液晶上电后,初始化命令的延迟要求,从而节约了 FPGA 的硬件资源.     

插入式BGA器件

利用管脚插入形式将电子元件固定到电脑主板上,作为一项非常流行的制造技术已经有二十多年的历史了。然而使用插座系统用于对BGA器件进行组装的设计师却面临着新的挑战,即将昂贵的IC器件固定到昂贵的母板上所需的封装问题。确保良好封装的重要一点是:要尽可能早的在设计开始时确定插座系统。满足可生产性的设计由于通过插座能够很容易地实现插入或者拨出,使得插座具有提高组装、测试和返修工艺的能力,从而体现出了采用插座形式的长远价值。除此之外,它们对生产过程的其他方面也起到了一定的积极作用。如果在设计初期考虑到这些问题,不仅能…     

BGA焊点互连的可靠性

与SOIC、PLCCs或QFPs相比,母板上BGA互连一般在每个设备上有更多焊点,因此出现故障的可能性也随之增大.加上对它检查、返工和维修都比较困难,所以确保成形阵列互连的一致性,以及它们的质量及集成度都很重要.阵列互连的可靠性主要有两方面,首先,阵列焊点互连较传统的外引线互连顺从性要低.顺从性低导致互连在疲劳环境里性能下降.这里的疲劳环境是由温度波动及内部电路开/关造成热应力导致的.另外,在板级装配中,表面安装阵列互连及其应用相对来说才刚刚起步,缺乏性能方面的统计数据。影响焊点长期可靠性的因素主要有以下6点。     

基于COMe模块的加固计算机主板设计

设计了一种基于COMe模块的加固计算机主板,COMe模块集成了英特尔处理器、英特尔芯片组、DDR2 控制器、网络控制器、相关总线控制器等。基于COMe模块的主板具有可重用性、可扩展性、灵活性、兼容性、功耗低等优点。基于此技术设计的加固计算机主板具有环境适应性强、主板升级方便、载板重用性好的优点。该主板对外提供多种总线接口、显示接口、扩展接口,在抗恶劣环境计算机中得到广泛应用。     

High Cycle Cyclic Torsion Fatigue of PBGA Pb-Free Solder Joints

In this study, a comprehensive experimental and numerical approach was used to investigate high cycle cyclic torsion fatigue behavior of lead-free solder joints in a plastic ball grid array (PBGA) package. The test vehicle was a commercial laptop motherboard. The motherboard was subjected to torsional loading and life tests were conducted. Using finite element analysis (FEA), the test assembly was simulated as a global model and the BGA component was simulated as a local model. Strains measured on the motherboard surface near by the BGA were used to calibrate the FEA models. By combining the life test results and FEA simulations, a high cycle fatigue model for the lead-free solder joints was generated based on the Coffin-Manson strain-range fatigue damage model. This model can now be used to predict the cycles to failure of BGA interconnects for new electronic product design under cyclic torsion loading.     

Extension of a multilayer interconnection technology in MCM-Si with opto-electronic facilities

The increasing I/O-density of today’s packages is dealt with by using multilayer modules. Since there is also a trend towards faster interconnections by using optics, the extension of the interconnection module with V-grooves is in high demand. This paper reports on the electro-optical extensions of an earlier developed standard MCM-Si technology (Lernout et al., Journal of IMAPS (Europe) 1998; 15(1): 39–42; Ref. 1). The technology aspects of this standard MCM-Si technology are presented.The extended thin-film multilayer module is built up using two metal and three insulator layers. Additionally an implementation with low TCR resistors (NiCr) can be made. Fiber holding structures, namely V-grooves, are created into the bulk (100) silicon substrate by means of an anisotropic etching, performed in aqueous KOH. A passivation layer of silicon nitride, optimised towards low silicon content, served as protection mask during the KOH etching. The compatibility of this aggressive wet etching step with other processing steps is discussed. As for the insulators in the multilayer module, these high quality PECVD (Plasma Enhanced Chemical Vapour Deposition) layers are optimised towards low stress content and uniformity.Subsequently, the use of this interconnection substrate as a motherboard in multichip modules (MCM) is considered. The extension of the motherboard with V-grooves makes it possible to integrate opto-electronic (O/E) components, fibers and electronics on the same MCM-Si. Some of the major advantages are: low cost solution (saving non-used silicon area), compact assembly (carriers of fibers integrated with electronics), ability to reach higher frequencies (shorter interconnection distances),… Also low coupling losses between laser and fiber are achieved: the accuracy of V-grooves in silicon permits to place the fiber with high precision, and the self-aligning property of solder assures the control over the flip-chip (FC) mounted O/E-components (e.g. laser diodes).     

基于激光驱动芯片的信号完整性仿真分析

结合SA2669激光驱动芯片的测试系统进行仿真,仿真并分析了基于IBIS模型的高速数据采集系统的信号完整性问题。发现并解决该测试系统的存在会影响到性能的反射、振铃问题,提出了修改建议,并取得良好的仿真结果。结果证明高速电路设计中采用基于信号完整性的仿真设计是必要的、可行的。     

基于ARM9的嵌入式系统研究及设计

为适应嵌入式技术在现代工业及电子等更多领域的广泛应用,通过对ARM9嵌入式微处理器芯片S3C2410的研究,设计出基于S3C2410核心板的嵌入式系统开发底板,更多的需求及功能可在其底板上进行扩展与实现.首先对ARM9嵌入式微处理器S3C2410进行介绍,然后给出了基于S3C2410核心板的嵌入式系统开发底板的设计与功能扩展,包括开发板总体设计,电源模块设计,各种通信模块设计如串口、JTAG接口、网络接口、CAN总线通信接口等.该模板的设计实现了嵌入式系统在更多更广泛领域应用的灵活性.     

Penalty-free 2.5 Gbit/s photonic switching using a semiconductorfour-gate-array module

A penalty-free photonic switching experiment at 2.5 Gbit/s using a gate-array module of four semiconductor optical amplifiers, flip-chip-mounted on a silicon motherboard and provided with highspeed electronic drivers, is reported for the first time. Switching times shorter than 400 ps are obtained, allowing for guardbands as short as two bits between consecutive cells     

基于S3C2440嵌入式系统主板的电磁兼容性设计

为解决嵌入式高速主板存在的电磁兼容性问题,以基于S3C2440的嵌入式系统主板为平台,结合EMIStream,Hyperlynx仿真软件,对整个主板设计进行板极电磁干扰控制,采用源端串联端接阻抗的方法有效地减小了共模辐射和差模辐射干扰对整个主板产生的电磁兼容性影响。结合仿真,采用源端端接阻抗的方法可消除潜在电磁干扰问题,减小了开发周期和开发成本。     

Explication and sharing of design knowledge through a novel product design approach

At the beginning of the 21st century, the emergence of knowledge management is viewed as a natural evolution. Knowledge management is defined as the formal management of knowledge for facilitating creation, access, and reuse of knowledge, typically by using advanced technology. To be easily communicated and shared, tacit knowledge has to be explicated as explicit knowledge (e.g., in product specification or a scientific formula or production rules); and this explicit knowledge has to be shared as applicable data through the use of information technology. Product design is such a business process that a great part of the design knowledge is often a tacit type, being difficult to share, or available only in forms of natural language documents. However, the expertise recorded in these documents is an essential resource of successful competition in the market. This paper presents a knowledge explication and sharing approach; specifically focusing on the knowledge management of modular product design. The solution approach involves modeling modular products, formulating the explicit knowledge, discovering new design knowledge with data mining, and sharing the knowledge with web services technology. The proposed approach is to be applied to an actual case of motherboard design/assembly in one of the largest PC manufacturing enterprises.     

Design and development of optoelectronic mixed signal system-on-package (SOP)

This paper describes the design and development of a 2.5-Gb/s optical transceiver module as a mixed signal SOP for access networks. The module development consists of concurrent design of an optoelectronic package optimizing optical, electrical, thermal, mechanical functions and optical subassembly and RFICs housed in a chip-on-board package. The optical subassembly (OSA) consists of laser and photodiode assembled on a silicon substrate. The transmit and the receiver sections are combined into a single fiber through a polymer coupler on silicon. The splitter between the transmit and receive section is realized using a polymer waveguide. The electronic ICs are assembled on a multilayer organic substrate. The package design includes optical coupling design, impedance matched transmission line design for RF signals, electrical layout design for mixed signals and thermal design for the package. The module is housed in a plastic molded nonhermetic package to achieve low cost packaging. The assembly is completed using passive alignment of optical devices and attachment of electronic devices using adhesives. In this paper, we present the details of the component design and the development of packaging process methods to achieve the design specifications, test results and process guidelines for assembly and integration.