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三进制编码实现硬件演化方法研究 总被引:3,自引:0,他引:3
针对硬件演化在演化算法中采用定长染色体编码结构位串,其编码过长会造成演化速度慢、成本高等缺点,提出基于三进制编码实现演化算法的方法.利用 Matlab 矩阵运算的优势,采用遗传算法实现演化算法,找到最优电路编码矩阵,得到了最佳电路函数表达式.实例反映了三进制编码比定长染色体编码规模小,遗传算法中采用多点定向变异具有收敛速度快等优点,证明了三进制编码演化算法的有效性. 相似文献
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电路的演化设计方法是演化硬件研究的一个主要分支,它是开展演化硬件研究的基础,也是演化硬件得以具备自适应和自修复特性的技术前提。首先介绍了数字电路演化设计的理论基础,然后对系统开发所使用的硬件平台进行了描述,最后对电路演化设计的系统流程做了详细描述。为进一步深入到基于演化硬件的数字电路自适应和自修复技术研究打下了基础。 相似文献
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提出一种基于演化算法的可测性调度分配方法.应用演化算法,在调度和分配过程中研究电路的可测性设计.该方法的贡献是:给出了三个可测性准则;设计了可测性目标函数;提出了一种新颖的演化编码和演化操作,提高了搜索速度和解的质量.实验结果验证了该方法的可行性. 相似文献
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演化超网络在多类型癌症分子分型中的应用 总被引:2,自引:0,他引:2
该文提出一种用于多类型癌症分子分型的演化超网络模式识别方法。首先采用“一对多”方法,将一个多类分型问题转化为多个二类分型问题;然后利用信噪比方法对DNA微阵列数据进行信息基因选择;经过超网络对训练集的演化学习,构造一系列二类分类器并进行集成,最终构建一个多类型癌症分型系统并对待测样本进行分类。对急性白血病、儿童小圆蓝细胞肿瘤和GCM数据集实验结果表明:演化超网络留一交叉验证(LOOCV)识别率分别为:98.61%,100%和85.35%。演化超网络有利于挖掘癌症相关基因,具有良好的学习结果可读性。 相似文献
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文章提出了动态数据的高阶非线性微分方程的并行演化建模算法。动态系统的传统模型多采用线性模型,不能充分描述复杂系统的动态行为,建立高阶非线性微分方程模型更具普遍意义。我们通过将建模过程分解为可以分布并行的、模型结构选择和“模型参数优化”二个步骤,在异构网络环境中用CORBA实现了高阶微分方程建模的并行演化算法。实验表明,新的并行演化算法对于复杂动态系统的建模是十分有效的。 相似文献
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针对进化方法在多态自检电路设计方面存在的扩展性问题,该文提出了一种基于输入分解输出匹配的多态自检电路进化设计方法。该方法将原始电路分解为可进化生成部分和固定部分,由此减少待进化设计电路的输入个数以及适应度评价时真值表输入输出组合数量,从而降低电路进化复杂度;在适应度评价阶段,当电路输出位与理想输出匹配度小于1/2时,通过添加非门的形式提高候选电路适应度和种群多样性,防止最优结构的丢失。进化设计实验将多态门和普通门相结合,进行了两种多态自检加法器的设计。结果表明,与传统多态自检电路进化设计方法相比所提方法进化代数分别减少了47.9%和89.1%,单个测试参量下故障覆盖率分别提高了75.7%和79.7%,具有收敛速度快、扩展性好、故障覆盖率高的优点。 相似文献
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提出了一种基于真值表变量分离技术的数字电路进化设计方法.该方法旨在减少待进化系统的输入输出位数,将较难实现的整体进化系统分解成几个容易实现的进化子系统,从而实现较大规模数字电路的进化设计.同时结合多目标遗传算法,优化电路结构.并以加法器和乘法器为设计实例,结果证明了该方法能有效进化出较大规模的数字电路,得到的进化电路资源更少,时延更短. 相似文献
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容差模拟电路故障模糊诊断方法及其实现 总被引:1,自引:3,他引:1
提出了基于SOFM神经网络的容差模拟电路故障模糊诊断方法及其实现。该方法将网络撕裂法和SOFM神经网络相结合进行故障测试.并运用所设计的模糊逻辑神经网络系统判断测试条件,定位容差模拟电路的子网络级故障。仿真试验表明该方法故障定位精确度高。撕裂迅速,有利于大规模容差模拟电路故障诊断的实现。 相似文献
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Reducing the NoC power is critical for scaling up the number of nodes in future many-core systems. Most NoC designs adopt packet-switching to benefit from its high throughput and excellent scalability. These benefits, however, come at the price of the power consumption and latency overheads of routers. Circuit-switching, on the other hand, enjoys a significant reduction in power and latency of communication by directing data over pre-established circuits, but the relatively large circuit setup time and low resource utilization of this switching mechanism is often prohibitive. In this paper, we address one of the major problems of circuit-switching, i.e. the circuit setup time overhead, by an efficient and fast algorithm based on the time-division multiplexing (TDM) scheme. We then further improve the performance by reserving circuits for anticipated messages, and hence completely hide circuit setup time. To address the low resource utilization problem, we integrate the proposed circuit-switching into a packet switched NoC and use unused circuit resources to transfer packet-switched data. Evaluation results show considerable reduction in NoC power consumption and packet latency. 相似文献
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读出电路开窗是红外焦平面和图像传感器读出电路中,用于提高图像帧频降低带宽的重要技术。该技术通过减小读出阵列的窗口尺寸,降低电路读出的数据量,从而提高帧频。介绍了两类主要的开窗模式:异步读出模式和同步读出模式。针对异步读出模式扩展性差、存在竞争冒险的问题,以及同步读出模式占用像元面积和窗口切换速度慢的问题,基于同步读出提出了一种行列控制字架构,并设计了一种用于该架构的可重复单元电路,提高了对不同面阵规格的扩展性。完成了所提出的开窗电路设计和版图设计,并对该电路进行了仿真验证。对比其他方案,文中设计实现了任意位置、最小1×1尺寸的开窗,同时解决了占用像元面积和竞争冒险问题,并提高了窗口切换速度。 相似文献
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Combining the time and frequency location and multiple-scale analysis of wavelet transform with the nonlinear mapping and
generalizing of neural network, an efficient defect-oriented parametric test method using Wavelet Neural Network (WNN) for
switched-current integrated circuits is proposed. Contraposing to the fully compatible digital CMOS technology and current
scaling calculation of SI circuits, parameter cohort of switched current elements is used to compute the sensitivity and gain
tolerance and is applied for selecting the test models. The selecting of the appropriate wavelet function based on particular
switched current fault signal is discussed, and the number of network input and output nodes are determined by the circuit
status and dimension of eigenvector which is the energy of wavelet decomposition coefficient. To simplify configuration of
the neural network, the sampled data was preprocessed by wavelet transform. Illustrative examples show that the proposed wavelet
neural network method for testing of switched current circuits is effective. 相似文献
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We describe a new reverse simulation approach to analog and mixed-signal circuit test generation that parallels digital test generation. We invert the analog circuit signal flow graph, reverse simulate it with good and bad machine outputs, and obtain test waveforms and component tolerances, given circuit output tolerances specified by the functional test needs of the designer. The inverted graph allows backtracing to justify analog outputs with analog input sinusoids. Mixed-signal circuits can be tested using this approach, and we present test generation results for two mixed-signal circuits and four analog circuits, one being a multiple-input, multiple-output circuit. This analog backtrace method can generate tests for second-order analog circuits and certain non-linear circuits. These cannot be handled by existing methods, which lack a fault model and a backtrace method. Our proposed method also defines the necessary tolerances on circuit structural components, in order to keep the output circuit signal within the envelope specified by the designer. This avoids the problem of overspecifying analog circuit component tolerances, and reduces cost. We prove that our parametric fault tests also detect all catastrophic faults. Unlike prior methods, ours is a structural, rather than functional, analog test generation method. 相似文献
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Kondratyev A. Cortadella J. Kishinevsky M. Lavagno L. Yakovlev A. 《Proceedings of the IEEE. Institute of Electrical and Electronics Engineers》1999,87(2):347-362
Logic decomposition is a well-known problem in logic synthesis, but it poses new challenges when targeted to speed-independent circuits. The decomposition of a gate into smaller gates must preserve not only the functional correctness of a circuit but also speed independence, i.e., hazard freedom under unbounded gate delays. This paper presents a new method for logic decomposition of speed-independent circuits that solves the problem in two major steps: (1) logic decomposition of complex gates and (2) insertion of new signals that preserve hazard freedom. The method is shown to be more general than previous approaches and its effectiveness is evaluated by experiments on a set of benchmarks 相似文献