首页 | 官方网站   微博 | 高级检索  
相似文献
 共查询到20条相似文献,搜索用时 0 毫秒
1.
Digital watermarking is the process of hiding information into a digital signal to authenticate the contents of digital data. There are number of watermarking algorithm implemented in software and few in hardware. This paper discusses the implementation of robust invisible binary image watermarking algorithm in Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuits (ASIC) using connectivity preserving criteria. The algorithm is processed in spatial domain. The algorithm is prototyped in (i) XILINX FPGA (ii) 130 nm ASIC. The algorithm is tested in Virtex-E (xcv50e-8-cs144) FPGA and implemented in an ASIC.  相似文献   

2.
分析了 CMOS数字专用集成电路功耗的来源,给出了半定制数字专用集成电路功耗的计算方法以及功耗优化设计的方法。  相似文献   

3.
在专用集成电路的设计中,采用FPGA来验证专用集成电路的功能是一个重要而必不可少的过程,本文介绍了用2片Ahera公司的FLEX10K系列FPGA验在规模 和集成电路功能的过程,给出了在和集成电路设计中充分利用工具和原有集成电路的设计成果进行FPGA验证的步骤,并提出了如何解决验证过程中遇到的一些疑难问题。  相似文献   

4.
Information security has always been important in all aspects of life. It can be all the more important as technology continues to control various operations in our day to day life. Cryptography provides a layer of security in cases, where the medium of transmission is susceptible to interception, by translating a message into a form that cannot be read by an unauthorized third party. Several software implementations of blowfish crypto algorithms are described in the literature, but few attempts have been made to describe hardware implementations. The ultimate objective of the research presented in this paper is to develop low-power, high-throughput, real-time, reliable and secure crypto algorithm, which can be achieved through hardware implementations. The blowfish crypto algorithm is prototyped in 130 nm custom integrated circuit.  相似文献   

5.
FPGA与ASIC之兼容设计   总被引:1,自引:0,他引:1  
为了利用FPGA和ASIC设计各自的优点,很多设计首先通过FPGA来实现,再根据需求转换成ASIC实现,同时更多的ASIC设计为了降低风险和成本,在设计过程中会选择使用FPGA进行功能验证。这就需要设计能在两者之间互相转换,怎样使电路设计以最快的速度、最小的代价来满足这一转换,本文提出了一些兼容设计方法,并进行了分析,最后给出了兼容设计实例,设计实践表明这些设计方法对FPGA与ASIC的兼容设计是行之有效的。  相似文献   

6.
高延敏 《微电子学》1992,22(4):31-34
本文介绍了ASIC设计自动化最新工具——FPGA开发系统的软、硬件支撑环境,FPGA的概况,特点和基本结构,FPGA系列器件和工作频率以及在微机FPGA开发系统上如何进行ASIC电路的设计,最后给出一个设计实例的流程。  相似文献   

7.
FPGA和ASIC设计特点及应用探讨   总被引:2,自引:0,他引:2  
孟李林 《半导体技术》2006,31(7):526-529
介绍了ASIC、FPGA的设计步骤和设计流程,重点比较两者之间的设计特点和应用趋向,采用这两种不同方法完成40G高阶数字交叉连接芯片设计.通过比较表明:FPGA技术适用于小批量、产品更新快、周期短的电子产品设计,可以明显提高设计速度,缩短产品上市时间;ASIC技术适用于大批量、产品比较成熟、生命周期长的电子产品设计.ASIC的集成度和单片价格都比FPGA有优势.  相似文献   

8.
由于FPGA的种种优点,越来越多的电子设计师在初次设计电子产品时选择FPGA来完成电路的prototype设计。然后,再在必要时将prototype设计从FPGA转换成ASIC。在此转换过程中有一定的风险,如ASIC电路的复位、时钟树的设计、封装形式的选择以及可测性设计等。文中讨论了这些风险,并给出了减少这些风险的解决方案。  相似文献   

9.
介绍了一种利用ALTERA公司现场可编程芯片设计的步进电机脉冲分配电路模块,结合实例详尽叙述了开发软件及其设计输入方法。  相似文献   

10.
FPGA在ASIC设计流程中的应用   总被引:6,自引:0,他引:6  
本文介绍了FPGA器件在ASIC芯片开放中的应用,通过仿ASIC的FPGA在系统验证板在实际硬件环境中的验证可以弥补ASIC设计流程中仿真的不足,通过该验证也可以加快ASIC设计且降低由于逻辑问题所造成ASIC开发中的成本损耗。  相似文献   

11.
郭安华  黄世震 《电子器件》2012,35(3):313-316
芯片设计中一个非常重要的环节是验证.随着FPGA技术的迅速发展使基于FPGA的原型验证被广泛的用于ASIC的开发过程,FPGA原型验证是ASIC有效的验证途径,但传统FPGA原型验证的可视性非常差.为了解决传统FPGA原型验证可视性的问题,验证工程师采用了结合TotalRecall技术的FPGA原型验证方法对一款鼠标芯片进行验证.获得该方法不仅能提供100%的可视性,还确保FPGA原型验证以实时硬件速度运行.该方法创新了ASIC的验证方法学.  相似文献   

12.
论述了H.264解码器的ASIC(专用芯片)解决方案及其FPGA验证平台.该方案比常见DSP解决方案有更快的解码速度和更低的能耗,解决了H.264解码器由于算法复杂性增大带来的速度和能耗问题.鉴于大规模SoC芯片验证的复杂性,还比较详细地介绍了该芯片基于FPGA的验证平台.  相似文献   

13.
FPGA的应用越来越广泛,随着制造工艺水平的不断提升,越来越高的器件密度以及性能使得功耗因数在FPGA设计中越来越重要。器件中元件模块的种类和数量对FPGA设计中功耗的动态范围影响较大,对FPGA的电源功耗进行了分析,并介绍了如何利用Altera公司的PowerPlay Early Power Estimator这一工具在设计前期尽可能准确地估计功耗并通过估计功耗对硬件设计进行优化选择。  相似文献   

14.
传统电子体温计芯片采用大量复杂模拟模块,功耗和成本都较高.文章提出了一种适合电子体温计芯片采用的温度测量算法,基于上华(CSMC)1.0μm MGLVCMOS标准工艺,设计出实用化的数字体温测量电路,并绘制了整个电路的版图.利用Spectre、Verilog_XL及Matlab对系统电路进行仿真测试,结果显示所设计的数字体温测量电路在+32.0℃~+42.0℃(+90.0°F ~+108.0°F)的温度范围内可以实现摄氏和华氏两种模式的测量,具有0.1℃(0.2°F)的精度,1.5V电源电压下系统平均电流仅为100μA,整个电路呈现低功耗和高集成度的特点.  相似文献   

15.
Real-time implementation of the transposition operation is particularly interesting in signal and image processing applications as they are dominated by matrix-based techniques. This paper presents a low-power transpose register array architecture that provides both row-wise and column-wise accesses. Reduction of power is achieved minimizing the switching activities of registers by means of a clock gating scheme without a significant extra logic overhead. Simulations demonstrate a power saving range of 40–70%, which is highly dependent on dimension and register size, all with a variable area cost from −2% up to 9%.  相似文献   

16.
This paper presents improved design of low power adder and analysis based on power reduction technique. Using example of adder and multiplier, low leakage power CMOS digital circuit is verified by respective benchmark suite for each example and compared with conventional design of adder and multiplier.Using various supply voltages and fault coverage as parameters, reduction in power was measured. Simulation result and validation by example foresee implementation of proposed design as an essential part of high performance circuit design.The proposed technique offer power reduction up to 20.2% and fault coverage of 99.65%.  相似文献   

17.
Fabrication cost of application-specific integrated circuits (ASICs) is exponentially rising in deep submicron region due to rapidly rising non-recurring engineering cost. Field programmable gate arrays (FPGAs) provide an attractive alternative to ASICs but consume an order of magnitude higher power. There is a need to explore ways of reducing FPGA power consumption so that they can also be employed in ultra low power (ULP) applications instead of ASICs. Subthreshold region of operation is an ideal choice for ULP low-throughput FPGAs. The routing of an FPGA consumes most of the chip area and primarily determines the circuit delay and power consumption. There is a need to design moderate-speed ULP routing switches for subthreshold FPGA. This article proposes a novel subthreshold FPGA routing switch box (SB) that utilises the leakage voltage through transistor as biasing voltage which shows 69%, 61.2% and 30% improvement in delay, power delay product and delay variation, respectively, over conventional routing SB.  相似文献   

18.
This paper introduces a new low-voltage, low-power FVF current mirror circuit. The bulk-driven (BD) technique is employed to achieve extended input voltage swing and low supply voltage. Besides, the quasi-floating gate (QFG) is used to achieve high frequency performance. The merging of (BD) and (QFG) appear as a good and attractive solution to improve the circuit performance with reduced supply voltage. Benefiting from the interesting properties of (BD-QFG) MOSFET (MOST) technique, the proposed FVF current mirror circuit exhibits superior performance compared to other previously reported works. The workability of the proposed circuit has been verified through ELDO simulator based on a 0.18 μm USMC process. It achieves an enhanced bandwidth (2.7 GHz), low power consumption (79.33 μW), a low input impedance (130 Ω), and high output impedance (9.5 G Ω) from a low supply voltage (0.8 V). Monte Carlo simulation is also carried out, which proves the robust performance of the proposed circuit against mismatches. An application of the proposed current mirror is presented in the form of the current comparator to ensure the workability of the proposed BD-QFG current mirror.  相似文献   

19.
曾几何时,要验证FPGA的逻辑设计,可以先编译、写入,然后按下评估板上的复位按钮.  相似文献   

20.
文章在分析目标数据存储控制单元工作原理的基础上,提出了用FPGA芯片设计该单元的具体思路和方法,以及在设计中应考虑的问题,最后,给出了实验结果。  相似文献   

设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司    京ICP备09084417号-23

京公网安备 11010802026262号