Superconducting sigma-delta analog-to-digital converters

The sigma-delta architecture is the method of choice for designers and manufacturers of analog-to-digital converters (ADCs) for high dynamic range applications. This architecture uses oversampling and precise feedback to generate a shaped spectral distribution of the quantization noise. Subsequent digital filtering suppresses out of band quantization noise, yielding a large signal to in-band noise ratio. This permits the use of quantizers with only a few bits of resolution, most applications use single-bit quantizers. A unique advantage of superconducting electronics is the availability of the flux quantum which can be used to provide quantum mechanically accurate feedback at GHz rates. Josephson digital technology extends the realm of sigma-delta ADCs from MHz sampling rates to GHz sampling rates, from kHz signal bandwidths to MHz signal bandwidths, with comparable or better dynamic range when compared to semiconductor implementations. This paper presents circuits for Josephson sigma-delta ADCs, including single-loop, and double-loop modulators, circuits for quantized feedback, and digital data processing. Experimental results of a double-loop modulator sampling at 1.28 GHz are reported.     

A CMOS oversampling D/A converter with a current-mode semidigitalreconstruction filter

Oversampling digital-to-analog (D/A) converters employing sigma-delta modulation noise shaping and single-bit quantization are attractive for use in digital audio applications because of their relaxed reconstruction filtering requirements and their tolerance of component mismatch. However, the use of a two-level D/A interface results in a large amount of out-of-band quantization noise that typically must be attenuated by a carefully designed analog reconstruction filter. This paper introduces a means of simplifying the reconstruction filter design through the use of a semidigital finite-impulse-response (FIR) filter. In particular, it describes an oversampling D/A converter wherein a current-mode semidigital reconstruction filter is used to implement a multilevel D/A interface that attenuates the out-of-band quantization noise without requiring precise component matching. An experimental implementation of the converter achieves a dynamic range of 94 dB and 72 dB attenuation of out-of-band quantization noise for a baseband of 20 kHz. The prototype converter, which consists of a linear interpolator, a second-order noise shaper, and a 128-tap semidigital FIR filter, dissipates 59 mW from a 5-V supply and occupies an active area of 3 mm² when integrated in a 1.2-μm digital CMOS technology     

A monolithic ΣΔ A/D and D/A converter with filter forbroad-band speech coding

The authors present a 5-V-only 14-b, 16 ksamples/s linear codec suitable as the audio part of a CCITT G722 codec. The device uses second-order sigma-delta modulation for both analog/digital (A/D) and digital/analog (D/A) conversion at 2.048 Msamples/s. A time-continuous modulator with integrated antialias filtering is used at the A/D side, obviating the need for an external antialiasing filter. The digital filters for decimation and interpolation are implemented with both a custom digital signal processor (DSP) and specialized hardware. The device was realized with 74000 transistors on a 31-mm² die in a 3-μm SACMOS technology. A dynamic range of more than 80 dB and a passband ripple of 0.3 dB were attained with A/D and D/A paths in cascade     

A frequency agile monolithic QPSK modulator with spectral filteringand 75 Ω differential line driver

This monolithic modulator combines both digital signal processing and analog techniques to realize a high bit-rate quadrature phase-shift keyed (QPSK) modulator. It includes a digital baseband pulse shaping network, analog quadrature modulator, agile carrier generator, spectral shaping, and transmit power control for interfacing to wireline transmission media. Nominal data rates are 256 kbit/s with a carrier range of 8.096-20.128 MHz in 32 kHz steps. Maximum output level is 62 dBmV into a 75 Ω load. The features of 1.2 μm mixed signal BiCMOS technology permit both signal processing and power line drivers to be collocated while achieving better than 85 dB cross-talk isolation     

Digital DPCM Codec for TV Signals Based onDeltaM/DPCMDigital Conversions

A digital differential pulse-code modulation (DPCM) codec based on ΔM/DPCM and DPCM/ΔM digital conversions is presented as an equivalent replacement of a conventional DPCM codec for TV signals by using digital processing technology. A generalized model and equivalent circuit are shown for the digital DPCM codec, and transfer characteristics and quantizing noises are analyzed. The digital DPCM codec is designed for 1-MHz TV signals and the performance is verified by experiments. By the use of double integration ΔM and digital filter technology, it is shown that at the ΔM sampling rate of 16 MHz the overall SNR performance is sufficiently good for use as a conventional DPCM codec, and the digital code converters can be realized with commercially available transistor-transistor-logic (TTL) medium-scale-integrated (MSI) circuits and low-power emitter-coupled-logic (ECL) integrated circuits (IC's).     

Experimental implementation of $$\Delta \Sigma $$AD modulator with dynamic analog components

This paper presents an experimental prototype of 2nd-order multi-bit \(\Delta \Sigma \)AD modulator with dynamic analog components for low power and high signal to noise and distortion (SNDR) application. The integrators in the modulator are realized by ring amplifier without static current. Multi-bit quantizer and analog adder in the feed-forward modulator is realized by a passive-adder embedded successive approximation register analog to digital converter which consists of capacitor array and a dynamic comparator. The dynamic comparator does not dissipate static power at all when a pre-amplifier is not used. Proposed modulator is fabricated in TSMC 90 nm CMOS technology. Measurement results of the modulator dynamic range is over 84 dB. Measured peak SNDR = 77.51 dB, SNR = 80.08 dB are achieved for the bandwidth of BW = 94 kHz while a sinusoid differential \(-1\) dBFS input is sampled at 12 MS/s. The total analog power consumption of the modulator is 0.37 mW while the supply voltage is 1.1 V.     

A CMOS ADSL codec for central office applications

A CMOS central office codec that supports Full Rate and G.Lite asymmetric digital subscriber line (ADSL) transmission is described. The transmit channel consists of application-dependent digital filters, a 14-bit, 8.832-MSample/s current steering DAC, a 1.104-MHz analog filter, and a programmable attenuator. Due to extensive on-chip digital signal processing, the codec complies with the ADSL transmit power spectral density standards without external filtering. The receive channel contains -17.5 to 33.5 dB of programmable gain staggered strategically across three stages, a 138-kHz analog low-pass filter, a 14-bit, 2.208-MSample/s pipeline ADC, and a digital 138-kHz low-pass filter. The receive channel has a wide input range that can accommodate large line voltages present at the line hybrid circuit. The IC occupies 55.2 mm² and dissipates 450 mW from a 3.3-V supply     

A Wideband ΔΣ Digital-RF Modulator for High Data Rate Transmitters

A wideband software-defined digital-RF modulator targeting Gb/s data rates is presented. The modulator consists of a 2.625-GS/s digital DeltaSigma modulator, a 5.25-GHz direct digital-RF converter, and a fourth-order auto-tuned passive LC RF bandpass filter. The architecture removes high dynamic range analog circuits from the baseband signal path, replacing them with high-speed digital circuits to take advantage of digital CMOS scaling. The integration of the digital-RF converter with an RF bandpass reconstruction filter eliminates spurious signals and noise associated with direct digital-RF conversion. An efficient passgate adder circuit lowers the power consumption of the high-speed digital processing and a quadrature digital-IF approach is employed to reduce LO feedthrough and image spurs. The digital-RF modulator is software programmable to support variable bandwidths, adaptive modulation schemes, and multi-channel operation within a frequency band. A prototype IC built in 0.13-mum CMOS demonstrates a data rate of 1.2 Gb/s using OFDM modulation in a bandwidth of 200 MHz centered at 5.25 GHz. In-band LO and image spurs are less than -59 dBc without requiring calibration. The modulator consumes 187 mW and occupies a die area of 0.72 mm².     

A 1.8 V CMOS fourth-order Gm-C bandpass sigma-delta modulator dedicated to front-end ultrasonic receivers

A 4th order bandpass sigma-delta modulator for ultrasound applications is presented. By cascading two second-order identical Gm-C bandpass filters, a 4th-order modulator was designed with high power-efficiency, stability, tunability and programmability. The modulator is dedicated for application with intermediate frequency of 3 MHz and bandwidth of 200 kHz. Implemented in a standard 0.18 μm CMOS technology, the post-layout simulation of the modulator gives a dynamic range of 78 dB. Chip measurements are reported after successfully tuning the modulator to operate at four-time of its folded specifications. The final SNR achieves 58 dB at 0.75 MHz with 50 kHz bandwidth. The modulator consumes 2.5 mW from 1.8 V power supply. Moreover, a programming method is introduced and corresponding circuit is designed to change the central frequency of the modulator between 3 and 20 MHz for scanning different regions of the body. However the 200 kHz bandwidth limits the modulator only for Dobbler mode applications, the effective facilities of programmability are valuable property to expand this application to other wide band applications in future. Lisheng Qin received the B.Sc. degree in electrical engineering from Tianjin University, China in 1992. He was with Polystim Neurotechnologies Laboratory from 2001 to 2005 and received the M.Sc. degree in electronics engineering from Ecole Polytechnique de Montreal, Canada in 2005. He is now with Apexone Microelectronics Inc. as Analog/Mixed-Signal Design Engineer. Kamal El-Sankary received the B.Sc. degree in electrical engineering from the Lebanese University, Lebanon in 1997 and the M.Sc. degree in electronics engineering from University of Quebec in Trois Rivieres, Canada, in 2001. He is currently pursuing the Ph.D. degree in microelectronics at Ecole Polytechnique de Montreal, Canada. His research interests include analog/mixed-signal circuits design and signal processing. Mohamad Sawan received the B.Sc. degree in electrical engineering from Université Laval, Canada in 1984, the M.Sc. and Ph.D. degrees, both in electrical engineering, from Université de Sherbrooke, Canada, in 1986 and 1990 respectively, and postdoctorate training from McGill University, Canada in 1991. He joined Ecole Polytechnique de Montréal in 1991 where he is currently a Professor in Microelectronics. His scientific interests are the design and test of mixed-signal (analog, digital and RF) circuits and systems, the digital and analog signal processing, the modeling, design, integration, assembly and validation of advanced wirelessly powered and controlled monitoring and measurement techniques. These topics are oriented toward the biomedical implantable devices and telecommunications applications. Dr. Sawan is a holder of a Canadian Research Chair in Smart Medical Devices. He is leading the Microelectronics Strategic Alliance of Quebec (Regroupement stratégique en microélectronique du Québec - ReSMiQ). He is founder of the Eastern Canadian IEEE-Solid State Circuits Society Chapter, the International IEEE-NEWCAS conference, and Polystim neurotechnologies laboratory at the Ecole Polytechnique de Montreal. He is cofounder of the International Functional Electrical Stimulation Society (IFESS), and the IEEE International conference on Electronics, Circuits and Systems (ICECS). Dr. Sawan is involved in the committees of many national and international conferences and other scientific events. He published more than 300 papers in peer reviewed journals and conference proceedings and is awarded 6 patents. He is editor of the Springer Mixed-signal Letters, Distinguished Lecturer for the IEEE CAS Society, President of the biomedical circuits and systems (BioCAS) technical committee of the IEEE CAS Society, and he is representative of IEEE-CAS in the International Biotechnology council. He received the Barbara Turnbull 2003 award for spinal cord research, the Medal of Merit from Lebanon, and the Bombardier Medal from the French Association for the advancement of sciences. Dr. Sawan is Fellow of the Canadian Academy of Engineering, and Fellow of the IEEE.     

A third-order /spl Sigma//spl Delta/ modulator in 0.18-/spl mu/m CMOS with calibrated mixed-mode integrators

This paper describes a third-order sigma-delta (/spl Sigma//spl Delta/) modulator that is designed and implemented in 0.18-/spl mu/m CMOS process. In order to increase the dynamic range, this modulator takes advantage of mixed-mode integrators that consist of analog and digital integrators. A calibration technique is applied to the digital integrator to mitigate mismatch between analog and digital paths. It is shown that the presented modulator architecture can achieve a 12-dB better dynamic range than conventional structures with the same oversampling ratio (OSR). The experimental prototype chip achieves a 76-dB dynamic range for a 200-kHz signal bandwidth and a 55-dB dynamic range for a 5-MHz signal bandwidth. It dissipates 4 mW from 1.8-V supply voltages and occupies 0.7-mm/sup 2/ silicon area.     

A SAR-based ΣΔ modulator using shared DAC

In this paper a new successive approximation (SA) quantizer based on the elimination of the digital to analog converter (DAC) from the quantizer structure is presented. Instead; the feedback DAC block of the ΣΔ modulator is shared by SA quantizer. Using an efficient decoding algorithm in the proposed structure in conjunction with the above SA quantizer DAC elimination method, results in a reduction of the level number of the feedback DAC, and hence, a significant drop in power and area consumption is achieved. In order to study the performance of the proposed structure, a third order discrete-time ΣΔ modulator is designed and simulated in 0.18 μm CMOS technology with the following performance characteristics; a signal to noise ratio of 79.2 dB, dynamic range of 84.8 dB, power consumption of 3.75 mW and a figure of merit of 0.66 pJ/conv from a 1.8 V supply with an input signal of 200 kHz bandwidth.     

Signal-to-Noise Analysis of a PCM Voice System Based on Analog/Digital Filtering

In the field of communications, an ever-increasing number of system functions is realized in digital form. In this context, the problem of economical analog/digital conversion becomes an important issue. The cost of analog/digital conversion, however, is often dominated by the associated filters required for the prevention of foldover distortion. For this reason, an approach characterized by analog filtering (with relaxed requirements) before A/D conversion, and additional, digital, time-shared filtering after A/D conversion, becomes an attractive solution. In this paper, the signal-to-noise ratio of such a system is analyzed. The analysis includes quantization noise and overload distortion from the analog/digital conversion process, additional noise due to codec imperfections and round-off noise from the digital filters and interpolators. A design example, that was also implemented in hardware, demonstrates that the specifications of the CCITT can be easily met.     

一种稳定的高阶∑—△模／数转换器

文章提出了一种稳定的高阶∑-△模数转换器的设计方法。结合实例，简要说明了多级数字抽取滤波器的设计，并讨论了调制器基内零点优化的方法。设计的∑-△A/D转换器可以满足无线通信应用中大动态范围A/D转换的要求。     

A novel analog/digital reconfigurable automatic gain control with a novel DC offset cancellation circuit

An analog/digital reconfigurable automatic gain control(AGC) circuit with a novel DC offset cancellation circuit for a direct-conversion receiver is presented.The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips.What’s more,a novel DC offset cancellation(DCOC) circuit with an HPCF(high pass cutoff frequency) less than 10 kHz is proposed.The AGC is fabricated by a 0.18μm CMOS process.Under analog control mode,the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz.Under digital control mode,through a 5-bit digital control word,the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB.The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV,while the offset voltage of 40 mV is introduced into the input.The overall power consumption is less than 3.5 mA,and the die area is 800×300μm~2.     

A 5-mW sigma-delta modulator with 84-dB dynamic range for GSM/EDGE

A sigma-delta modulator designed as part of a complete GSM/EDGE (enhanced data rate for GSM evolution) transceiver is described. High-resolution wide-band analog-to-digital converters enable the receiver to rely on digital processing, rather than analog filtering, to extract the desired signal from blocking channels. High linearity and low power consumption are the most stringent requirements for the converters in this wireless application. A single-bit 2-2-cascaded modulator operating at 13 MHz has been adopted for high linearity and stability. Low-power low-voltage techniques have been applied along with a top-down design approach in order to minimize the power dissipation. The ΣΔ modulator achieves 13.5 bits of resolution over a bandwidth of 180 kHz while dissipating 5 mW from 1.8-V and 2.4-V supplies. The circuit has been implemented in the CMOS portion of a 0.4-μm (drawn) BiCMOS technology and occupies an active area of 0.4 mm²     

A 270-kb/s 35-mW modulator IC for GSM cellular radio hand-heldterminals

The modulator IC is a mixed analog/digital transceiver component in a chip set that is designed for the hand-held terminals of the pan-European 900-MHz Groupe Special Mobile (GSM) digital cellular radio network. The concept of the radio-frequency environment in which the circuit is used is explained, focusing on the differences in existing systems. The architecture and different functions of the modulator circuit and details of the digital and analog processing in the transmission mode are discussed. The receiving mode, which is mostly based on analog processing, is highlighted. The device generates Gaussian minimum-shift-keying (GMSK) modulation and converts the received signal to 8-b words after filtering. The modulator IC uses digital waveform generation and a quadrature signal representation. This device is implemented in a 1.5-μm CMOS technology. The power consumption is less than 35 mW from a 5-V supply     

Improved digital-IF transmitter architecture for highly integrated W-CDMA mobile terminals

An improved digital intermediate frequency (IF) transmitter architecture for wide-band code-division multiple-access (W-CDMA) mobile terminals is proposed. Based on the heterodyne design but without requiring any off-chip IF filter, the transmitter enjoys the advantages of a homodyne architecture (such as circuit simplicity, low power consumption, and a high level of integration) while avoiding the performance problems associated with direct upconversion. By implementing the quadrature modulation in the digital domain and requiring only a single path of analog baseband circuits, inherently perfect I/Q matching and good error vector magnitude (EVM) performance can be achieved. The IF is chosen to be a quarter of the clock rate for a very simple and low-power digital modulator design. The difficulties of on-chip IF filtering were greatly alleviated by 1) performing a careful frequency planning and 2) employing a special-purpose digital-to-analog converter to produce high-order sin(x)/x rolloff. System-level simulation demonstrates that spurious-emission requirements are met with virtually no dedicated reconstruction filter circuits. This architecture takes full advantage of complimentary metal-oxide-semiconductor technology scaling by employing digital processing to ease analog complexities.     

Current-Mode Multiplier/Divider Circuits Based on the MOS Translinear Principle

In this paper, novel current-mode analog multiplier/divider circuits based on a pair of voltage-translinear loops are presented, featuring simplicity, precision and wide dynamic range. They are suitable for standard CMOS fabrication and can be successfully employed in a wide range of analog signal processing applications. Two versions, based on stacked and up-down voltage-translinear loops, respectively, are described. Experimental results are provided in order to verify their correct operation.     

A 65-nm low-noise low-costΣ△modulator for audio applications

正This paper introduces a low-noise low-costΣA modulator for digital audio analog-to-digital conversion. By adopting a low-noise large-output swing operation amplifier,not only is the flicker noise greatly inhibited,but also the power consumption is reduced.Also the area cost is relatively small.The modulator was implemented in a SMIC standard 65-nm CMOS process.Measurement results show it can achieve 96 dB peak signal-to-noise plus distortion ratio(SNDR) and 105 dB dynamic range(DR) over the 22.05-kHz audio band and occupies 0.16 mm~2. The power consumption of the proposed modulator is 4.9 mW from a 2.5 V power supply,which is suitable for high-performance,low-cost audio codec applications.     

Digital extraction of quantization error and its applications to successful design of sigma-delta modulator

A new technique to evaluate the quantization error of cascaded sigma-delta modulators in digital domain is presented. It avoids the complications associated with analog extraction of the quantization error in multistage noise shaping (MASH) modulators before feeding the error to the proceeding stage. Instead, the quantization error is estimated and cancelled out by adding a digital subtractor and by injecting a purely analog signal from the preceding stage to the next stage. In comparison to conventional MASH modulator structure, analog circuit requirements of the modulator are therefore relaxed, and the number of switched-capacitor digital-to-analog converters and the associated switching energy are lowered. In the absence of extra switching blocks, less flicker and thermal noise would be also injected into the circuit. Different implementations of MASH modulator are presented and analyzed based on the proposed digital quantization error extraction technique. Behavioral-level simulation results prove the mathematical equivalence of the proposed structures with successful MASH designs found in the literature, and confirm the effectiveness of the idea. For a ? 1.4 dB, 19.8 kHz input and an oversampling ratio of 16, a modified 1-V 20-MS/s 2 + 2 MASH modulator achieves a signal-to-noise-and-distortion ratio (SNDR) of 78 dB, when the input of the first quantizer is fed to the second stage. The second design based on digital extraction of quantization error achieves a 71 dB SNDR for a ? 8.0 dB, 19.8 kHz input, when the second stage is fed by the output of the first integrator.