Enhanced active‐feedback frequency compensation with on‐chip‐capacitor reduction feature for amplifiers with large capacitive load

A large capacitive load amplifier with enhanced active‐feedback frequency compensation is proposed in this paper. The enhancement is achieved through using a wide‐bandwidth scalar circuit to increase the transconductance of the output stage so that the overall bandwidth of the amplifier can be extended considerably. Implemented in a standard CMOS 130‐nm technology, with a supply of 0.7 V and consuming 27 μA of current, the amplifier drives a load capacitor of 15 nF. No on‐chip resistor is needed; only a 0.91‐pF compensation capacitor is used to maintain stability. The achieved gain‐bandwidth product and phase margin are 1.28 MHz and 66.9°, respectively. Moreover, the slew rate is 0.263 V/μs. The active chip area is 0.0056 mm². Copyright © 2017 John Wiley & Sons, Ltd.     

A new frequency compensation technique for three stages OTA by differential feedback path

A new single Miller capacitor for frequency compensation of three‐stage amplifier is proposed in this paper. In this scheme, a differential stage in which its negative and positive inputs are connected to the output and input nodes of third stage with a cascade capacitor forms the compensation block of a conventional three‐stage amplifier. Analysis shows that this configuration significantly improves the frequency domain performances of total circuit such as phase margin (PM) and gain‐bandwidth product (GBW) with just a very small amount of compensation capacitor. A three‐stage amplifier has been simulated with and without a differential feedback path in a 0.18 µm complementary metal–oxide–semiconductor (CMOS). The simulated amplifier with a 100 pF capacitive load achieved more than 9 MHz GBW and 83° PM while the compensation is less than 0.2% of load capacitor. An amplifier based on conventional nested Miller compensation can just achieve less than 0.23 MHz GBW with the same load, while using more than 100 pF as compensation capacitor. So this method shows an improvement of a factor of 40 in GBW and reduction of a factor of 550 in the size of compensation capacitor. It is a suitable strategy for ON‐CHIP compensation in comparison to other methods. Copyright © 2014 John Wiley & Sons, Ltd.     

Single Miller capacitor frequency compensation with nulling resistor for three‐stage amplifiers

A frequency compensation technique for three‐stage amplifiers is introduced. The proposed solution exploits only one Miller capacitor and a resistor in the compensation network. The straightness of the technique is used to design, using a standard CMOS 0.35‐µm process, a 1.5‐V OTA driving a 150‐pF load capacitor. The dc consumption is about 14µA at DC and a 1.8‐MHz gain–bandwidth product is obtained, providing significant improvement in both (MHzpF)/mA and ((V/µs)pF)/mA performance parameters. Copyright © 2007 John Wiley & Sons, Ltd.     

Dual loop cascode-Miller compensation with damping factor control unit for three-stage amplifiers driving ultralarge load capacitors

An area-efficient amplifier topology is presented for three-stage amplifiers driving ultralarge load capacitor with reduced power consumption. It contains two high-speed ac feedback loops made from embedded current buffers and small-size compensation capacitors, which pushes the nondominant complex poles to very high frequencies. To further improve the stability, a local impedance damping block is embedded. At the higher frequencies, it suppresses the high resistive property at the second-stage output, thereby increasing the damping factor of the complex poles and improving the overall gain margin. For identical bandwidth, the overall silicon area of the on-chip compensation capacitor is therefore decreased, leading to enhanced small-signal and large-signal performance metrics. Coined dual loop cascode-Miller compensation with damping factor control unit, the effectiveness of the proposed approach is investigated through simulation results in 90-nm complementary metal-oxide-semiconductor (CMOS) technology. An implementation based on the proposed technique consumes a quiescent current of 17 μA from a 1.2 V voltage supply. For a load capacitance equal to 560 pF, it achieves a gain-bandwidth frequency of 4.34 MHz, an average slew-rate of 1.72 V/μs, and an average settling time of 0.52 μs, when the overall compensation capacitance is set to 1.55 pF. The proposed design can supply the load capacitors up to 35 nF.     

Adaptive frequency compensation for maximum and constant bandwidth feedback amplifiers

We present an adaptive frequency compensation technique providing maximum bandwidth closed‐loop amplifiers. The approach exploits an auxiliary variable gain amplifier to implement an electrically tunable compensation capacitor proportional to the feedback factor. In this manner, the closed‐loop bandwidth is kept ideally constant irrespective of the closed‐loop gain. The proposed method can be applied to any amplifier adopting dominant‐pole compensation. As an example, we designed a CMOS amplifier providing 66‐dB direct current gain and 310‐MHz gain‐bandwidth product. For closed‐loop gains ranging from 1 to 10, the closed‐loop bandwidth was found never lower than 401 MHz (noinverting configuration) and 229 MHz (inverting configuration). A similar amplifier with equal gain‐bandwidth product, but adopting the traditional fixed compensation approach, would exhibit a closed‐loop bandwidth reduced to 33 MHz (noninverting) and 30 MHz (inverting) when the gain magnitude is set to 10. The enhanced frequency performance is obtained with a 48% increase in current consumption, whereas the other main operational amplifier performance parameters remain almost unchanged compared with the standard solution. Copyright © 2011 John Wiley & Sons, Ltd.     

A low‐dropout voltage regulator with active current amplifier frequency compensation

This paper presents a new compensation scheme of low‐dropout regulator (LDO) design over the conventional methodology. With only 0.3 pF on‐chip compensation capacitor, a left‐half‐plane zero is realized within the regulation loop unity‐gain bandwidth and over 56 ^° phase margin is achieved under the full range of the load current. The LDO thus achieves stability without using the equivalent series resistance of the capacitor. It is proven experimentally that the proposed LDO has many attractive features such as high accuracy, low quiescent current, and smaller compensation capacitor. The measurement results show that the excellent performance can be comparable with the state of the art LDOs. Copyright © 2010 John Wiley & Sons, Ltd.     

±0.18‐V supply voltage gate‐driven PGA with 0.7‐Hz to 2‐kHz constant bandwidth and 0.15‐μW power dissipation

A simple gate‐driven scheme to reduce the minimum supply voltage of AC coupled amplifiers by close to a factor of two is introduced. The inclusion of a floating battery in the feedback loop allows both input terminals of the op‐amp to operate very close to a supply rail. This reduces essentially supply requirements. The scheme is verified experimentally with the example of a PGA that operates with ±0.18‐V supply voltages in 0.18‐μm CMOS technology and a power dissipation of about 0.15 μW. It has a 4‐bit digitally programmable gain and 0.7‐Hz to 2‐kHz true constant bandwidth that is independent on gain with a 25‐pF load capacitor. In addition, simulations of the same circuit in 0.13‐μm CMOS technology show that the proposed scheme allows operation with ±0.08‐V supplies, 7.5‐Hz to 8‐kHz true constant bandwidth with a 25‐pF load capacitor, and a total power dissipation of 0.07 μW.     

Micropower high current‐drive class AB CMOS current‐feedback operational amplifier

A novel CMOS current‐feedback operational amplifier (CFOA) aimed to low‐power applications is proposed. The use of a compact class AB implementation allows high current‐drive capability and simultaneously very low quiescent power consumption. Measurement results of a fabricated prototype show for an inverting configuration a closed‐loop bandwidth of 1 MHz independent of gain setting, and a slew rate of 2V/µs for a load capacitance of 30 pF and a quiescent power consumption of 264µW. Copyright © 2010 John Wiley & Sons, Ltd.     

A novel feed-forward compensation technique for single-stage fully-differential CMOS folded cascode rail-to-rail amplifier

This paper presents a novel active and passive mixed feed-forward compensation technique for single-stage CMOS folded-cascode rail-to-rail operational trans-conductance amplifiers (OTA). Simulations using 0.5 μm Agilent CMOS process parameters indicate a phase margin of around 82° with an unity gain bandwidth of 320 MHz (@1.17 pF capacitive load including the device parasitics). Also, the compensated OTA provided over 60 dB DC-gain with rail-to-rail output voltage swing as well as wide input common-mode range. This ensures optimum step response (fast and accurate settling without ringing) for the feedback amplifier in switched-capacitor signal processing applications. An improved ``fast sensing' common-mode feedback circuit with high common-mode gain is also used for the single-stage cascode OTA.     

Design approach for high‐bandwidth low‐power three‐stage operational amplifiers

A new design approach to optimize the frequency compensation network of three‐stage operational amplifiers (op‐amps) is presented. The proposed criterion is aimed at maximizing the bandwidth of well‐established three‐stage op‐amps using Nested‐Miller Compensation with feedforward tranconductance stage and nulling resistor (NMCFNR). As shown by design examples in a commercial 0.35‐µm CMOS technology, the proposed approach allows the amplifier bandwidth to be enhanced significantly with respect to that resulting from using existing design strategies for NMCFNR op‐amps. It is also demonstrated that NMCFNR op‐amps, designed according to the proposed method, even guarantee larger values of the gain‐bandwidth product than three‐stage amplifiers using more complicated frequency compensation techniques, such as AC boosting compensation or damping‐factor control frequency compensation. Copyright © 2010 John Wiley & Sons, Ltd.     

Bessel‐like compensation of three‐stage operational transconductance amplifiers

In this paper, we introduce a simple and well‐defined approach for the design of fast settling amplifiers suitable for switched‐capacitor circuits and characterized by low capacitive loads, in the order of few pico‐farad. In the specific, the design is based on a new Bessel‐like compensation that sets the phase of the closed‐loop amplifier to be linearly related to the frequency, thus emulating the behavior of an ideal delay, like in a Bessel filter. The proposed Bessel‐like approach is validated through the design and the simulation of two 3‐stage amplifiers in a 65‐nm CMOS process.     

0.3‐V bulk‐driven programmable gain amplifier in 0.18‐µm CMOS

A new solution for an ultra low voltage bulk‐driven programmable gain amplifier (PGA) is described in the paper. While implemented in a standard n‐well 0.18‐µm complementary metal–oxide–semiconductor (CMOS) process, the circuit operates from 0.3 V supply, and its voltage gain can be regulated from 0 to 18 dB with 6‐dB steps. At minimum gain, the PGA offers nearly rail‐to‐rail input/output swing and the input referred thermal noise of 2.37 μV/Hz^1/2, which results in a 63‐dB dynamic range (DR). Besides, the total power consumption is 96 nW, the signal bandwidth is 2.95 kHz at 5‐pF load capacitance and the third‐order input intercept point (IIP₃) is 1.62 V. The circuit performance was simulated with LTspice. Copyright © 2016 John Wiley & Sons, Ltd.     

Graphical analysis and design of multistage operational amplifiers with active feedback Miller compensation

Frequency compensation of a multistage operational amplifier (op‐amp) is normally performed through solving nodal equations of an equivalent circuit to obtain the op‐amp's final transfer function. The process is often very tedious and offers little insight into the roles of the selected compensation scheme. In this paper, we present a graphical design approach for two‐stage and three‐stage op‐amps with active feedback Miller compensation. By viewing frequency compensation as a standard feedback problem, we can utilize the well‐known graphical tools such as the root locus and Bode plot to understand the effects of the compensation and to estimate the locations of the closed‐loop poles and zeros of the op‐amp. Intuitive graphical design procedures for two‐stage and three‐stage op‐amps are also formulated. To show its effectiveness, we illustrate our design approach through the design of a three‐stage op‐amp in a standard 0.18‐μm complementary metal‐oxide‐semiconductor (CMOS) process. With a load capacitance of 500 pF, post‐layout simulations show that the op‐amp achieves a low‐frequency gain of 144 dB, a phase margin of 58^°, and a unity‐gain frequency of 1.38 MHz while consuming a total bias current of 31 μA from a 1.8‐V supply voltage. Comparisons with the published amplifiers show that our op‐amp achieves the figure of merits comparable to those of the state of the art. Copyright © 2015 John Wiley & Sons, Ltd.     

A 0.8‐V supply bulk‐driven operational transconductance amplifier and Gm‐C filter in 0.18 µm CMOS process

A low voltage bulk‐driven operational transconductance amplifier (OTA) and its application to implement a tunable Gm‐C filter are presented. The linearity of the proposed OTA is achieved by nonlinear terms cancelation technique, using two paralleled differential topologies with opposite signs in the third‐order harmonic distortion term of the differential output current. The proposed OTA uses 0.8 V supply voltage and consumes 31.2 μW. The proposed OTA shows a total harmonic distortion of better than ?40 dB over the tuning range of the transconductance, by applying 800 mV_ppd sine wave input signal with 1 MHz frequency. The OTA has been used to implement a third‐order low‐pass Gm‐C filter, which can be used for wireless sensor network applications. The filter can operate as the channel select filter and variable gain amplifier, simultaneously. The gain of the filter can be tuned from ?1 to 23 dB, which results in power consumptions of 187.2 to 450.6 μW, respectively. The proposed OTA and filter have been simulated in a 0.18 µm CMOS technology. Simulations of process corners and temperature variations are also included in the paper. Copyright © 2014 John Wiley & Sons, Ltd.     

Low‐voltage low‐power CMOS receiver front‐end for gigabit short‐reach optical communications

This article presents a new CMOS receiver analog front‐end for short‐reach high‐speed optical communications, which compensates the limited product bandwidth length of 1‐mm step‐index plastic optical fiber (SI‐POF) channels (45 MHz · 100 m) and the required large‐diameter high‐capacitance Si PIN photodetector (0.8 mm–3 pF). The proposed architecture, formed by a transimpedance amplifier and a continuous‐time equalizer, has been designed in a standard 0.18‐µm CMOS process with a single supply voltage of only 1 V, targeting gigabit transmission for simple no‐return‐to‐zero modulation consuming less than 23 mW. Experimental results validate the approach for cost‐effective gigabit SI‐POF transmission. Comparative analysis with previously reported POF receivers has been carried out by introducing a useful figure of merit. Copyright © 2012 John Wiley & Sons, Ltd.     

Global impedance attenuation network for multistage OTAs driving a broad range of load capacitor

Advanced multistage amplifiers suffer from load-dependent stability issues, which limit the load capacitor range they can drive. In this work, the concept of global impedance attenuation (GIA) network is introduced to improve an amplifier's stability in the presence of significant load capacitor variations. Composed of multiple parallel resistor-capacitor (RC) branches, the equivalent high-frequency output impedance of gain stages is shaped by the GIA network such that a desired frequency spectrum is obtained over a wide range of load capacitor. The parasitic poles at the output of the gain stages are nullified by the proposed network, thereby simplifying the amplifier's transfer function and reducing the minimum load capacitor it can drive. The idea is applied to design a three-stage operational transconductance amplifier (OTA) with cascode global impedance attenuation (CGIA). Small-signal analysis shows that the OTA is stable regardless of the load capacitor, and it can drive very small to ultra-large load capacitors. This feature is verified by the post-layout simulations of a CGIA amplifier in 0.18-μm complementary metal-oxide semiconductor (CMOS) process. The core occupies a die area of 0.0053 mm² while consuming a static current of 10.97 μA from 1.8-V voltage supply. The unity-feedback configuration is unconditionally stable for any load capacitor higher than 10 pF. To the best of our knowledge, this corresponds to the widest range of load capacitance reported for prior-art three-stage amplifiers.     

Analytical comparison of reversed nested Miller frequency compensation techniques

In this paper, novel and previously proposed reversed nested Miller compensation (RNMC) networks are analyzed and compared, and their design equations are also presented. Hence, this paper is the natural extension of a previous paper by the authors (Int. J. Circ. Theor. Appl. 2008; 36 (1):53–80), where only the nested Miller compensation topologies were treated. In particular, a coherent and comprehensive analytical comparison of the RNMC topologies, including two new networks presented for the first time, is performed by means of the figure of merit that expresses a trade‐off among gain‐bandwidth product, load capacitance and total transconductance, for equal values of phase margin (Int. J. Circ. Theor. Appl. 2008; 36 (1):53–80). The analysis shows that there is no unique optimal solution among the RNMC topologies, as this depends on the load condition as well as on the relative transconductance magnitude of each amplifier stage. From this point of view, the proposed comparison also outlines useful design guidelines for the optimization of large‐signal and small‐signal performance. Simulations confirming the effectiveness of the proposed design methodology and analytical comparison are also included. Copyright © 2009 John Wiley & Sons, Ltd.     

A 7.5‐μW 0.08‐mm2 single‐ended SC delta‐sigma ADC for acoustic sensor applications

This study presents an ultra‐low‐power, small‐size, 1‐bit, single‐ended, and switched‐capacitor (SC) delta‐sigma analog‐to‐digital converter (ADC) for wireless acoustic sensor nodes. This wireless sensor node has a delta‐sigma ADC that converts the sensed signal to a digital signal for convenient data processing and emphasizes the features of small size and low‐power consumption. The chip area of the delta‐sigma ADC is dominated by the capacitor; therefore, a novel common‐mode (CM) controlling technique with only transistors is proposed. This ADC achieves an extremely small size of 0.08 mm² in a 130‐nm CMOS process. The conventional operational transconductance amplifiers (OTAs) are replaced by inverters in the weak inversion region to achieve high power efficiency. At 4‐MHz sampling frequency and 0.7‐V power supply voltage, the delta‐sigma ADC achieves a 55.8‐dB signal‐to‐noise‐plus‐distortion ratio (SNDR) and a 298‐fJ/step figure‐of‐merit (FOM) in a signal bandwidth of 25 kHz, while consuming only 7.5 μW of power. Copyright © 2015 John Wiley & Sons, Ltd.     

0.5‐V bulk‐driven differential amplifier

A new 0.5‐V fully differential amplifier is proposed in this article. The structure incorporates a differential bulk‐driven voltage follower with conventional gate‐driven amplification stages. The bulk‐driven voltage follower presents differential gain equal to unity while suppressing the input common‐mode voltage. The amplifier operates at a supply voltage of less than 0.5 V, performing input transconductance almost equal to a gate transconductance and relatively high voltage gain without the need for gain boosting. The circuit was designed and simulated using a standard 0.18‐µm CMOS n‐well process. The low‐frequency gain of the amplifier was 56 dB, the unity gain bandwidth was approximately 3.2 MHz, the spot noise was 100 nV/√Hz at 100 kHz and the current consumption was 90 μΑ. Copyright © 2012 John Wiley & Sons, Ltd.     

A common‐mode replica compensated inductor–capacitor voltage‐controlled oscillator for mixed‐signal system‐on‐chip applications

A novel 1.57 GHz complementary metal–oxide semiconductor inductor–capacitor voltage‐controlled oscillator with the common‐mode replica compensation is introduced for mixed‐signal system‐on‐chip applications. In order to alleviate power line disturbances, the center tap node of differential symmetric inductor and the replica biasing circuit are adopted in the differential voltage regulating unit to reduce power supply sensitivity. In addition, this proposed design also leads to low tuning gain and low power dissipation. The post‐layout simulation results under the Taiwan Semiconductor Manufacturing Company's mixed‐signal 0.18 µm 1P6M process show that the proposed design achieves power supply rejection of ?68.6 dB at low frequencies and 1.2 MHz/V pushing sensitivity. It exhibits phase noise of ?130.6 dBc/Hz at a 1 MHz offset from a 1.57 GHz carrier yet dissipates only 5.58 mW under a 1.8 V power supply. Copyright © 2011 John Wiley & Sons, Ltd.