Explicit design formulas for current‐mode leap‐frog OTA‐C filters and 300 MHz CMOS seventh‐order linear phase filter

The leap‐frog (LF) configuration is an important structure in analogue filter design. Voltage‐mode LF OTA‐C filters have recently been studied in the literature; however, general explicit formulas do not exist for current‐mode LF OTA‐C filters and there is also need for current‐mode LF‐based OTA‐C structures for realization of arbitrary transmission zeros. Three current‐mode OTA‐C structures are presented, including the basic LF structure and LF filters with an input distributor or an output summer. They can realize all‐pole characteristics and functions with arbitrary transmission zeros. Explicit design formulas are derived directly from these structures for the synthesis of, respectively, all‐pole and arbitrary zero filter characteristics of up to the sixth order. The filter structures are regular and the design formulas are straightforward to use. As an illustrative example, a 300 MHz seventh‐order linear phase low‐pass filter with zeros is presented. The filter is implemented using a fully differential linear operational transconductance amplifier (OTA) based on a source degeneration topology. Simulations in a standard TSMC 0.18µm CMOS process with 2.5 V power supply have shown that the cutoff frequency of the filter ranges from 260 to 320 MHz, group delay ripple is about 4.5% over the whole tuning range, noise of the filter is 420nA/√Hz, dynamic range is 66 dB and power consumption is 200 mW. Copyright © 2008 John Wiley & Sons, Ltd.     

A 0.8‐V supply bulk‐driven operational transconductance amplifier and Gm‐C filter in 0.18 µm CMOS process

A low voltage bulk‐driven operational transconductance amplifier (OTA) and its application to implement a tunable Gm‐C filter are presented. The linearity of the proposed OTA is achieved by nonlinear terms cancelation technique, using two paralleled differential topologies with opposite signs in the third‐order harmonic distortion term of the differential output current. The proposed OTA uses 0.8 V supply voltage and consumes 31.2 μW. The proposed OTA shows a total harmonic distortion of better than ?40 dB over the tuning range of the transconductance, by applying 800 mV_ppd sine wave input signal with 1 MHz frequency. The OTA has been used to implement a third‐order low‐pass Gm‐C filter, which can be used for wireless sensor network applications. The filter can operate as the channel select filter and variable gain amplifier, simultaneously. The gain of the filter can be tuned from ?1 to 23 dB, which results in power consumptions of 187.2 to 450.6 μW, respectively. The proposed OTA and filter have been simulated in a 0.18 µm CMOS technology. Simulations of process corners and temperature variations are also included in the paper. Copyright © 2014 John Wiley & Sons, Ltd.     

Analytical synthesis and comparison of voltage‐mode Nth‐order OTA‐C universal filter structures

Complementary single‐ended‐input operational transconductance amplifier (OTA)‐based filter structures are introduced in this paper. Through two analytical synthesis methods and two transformations, one of which is to convert a differential‐input OTA to two complementary single‐ended‐input OTAs, and the other to convert a single‐ended‐input OTA and grounded capacitor‐based one to a fully differential OTA‐based one, four distinct kinds of voltage‐mode nth‐order OTA‐C universal filter structures are proposed. TSMC H‐Spice simulations with 0.35µm process validate that the new complementary single‐ended‐input OTA‐based one holds the superiority in output precision, dynamic and linear ranges than other kinds of filter structures. Moreover, the new voltage‐mode band‐pass, band‐reject and all‐pass (except the fully differential one) biquad structures, all enjoy very low sensitivities. Both direct sixth‐order universal filter structures and their equivalent three biquad stage ones are also simulated and validated that the former is not absolutely larger in sensitivity than the latter. Finally, a very sharp increment of the transconductance of an OTA is discovered as the operating frequency is very high and leads to a modified frequency‐dependent transconductance. Copyright © 2010 John Wiley & Sons, Ltd.     

Analysis and implementation of a fourth‐order bandpass filter for R‐wave detection of an implantable cardiac microstimulator

This paper presents an ultra‐low‐power fourth‐order bandpass operational transconductance amplifier‐C (OTA‐C) filter for an implantable cardiac microstimulator used to detect the R‐wave of intracardiac electrograms. The OTA‐C filter fabricated by TSMC 0.35‐µm complementary metal–oxide–semiconductor (CMOS) technology is operated in the subthreshold region to save power under a supply voltage of 1 V. The current cancellation technique is adopted to reduce the transconductance of the amplifier. Through this, the low‐frequency OTA‐C filter can be realized by ultra‐low transconductance with on‐chip capacitors. Direct comparison to conventional RLC ladders replaced by OTA‐C circuits shows that the method of reducing the number of OTAs further diminishes power consumption. Design issues, including ultra‐low transconductance, linearity, and noise, are also discussed. Measurement results show that the low‐voltage, low‐power filter has a bandwidth between 10 and 50 Hz, third inter‐modulation distortion of ?40 dB, dynamic range of 43 dB, and power consumption of only 12 nW. The real electrocardiography signal is fed into the bandpass filter to verify the function of signal processing with the distribution of the R‐wave. Copyright © 2012 John Wiley & Sons, Ltd.     

Analysis and design of highly linear triode‐mode based OTA and its application to a wide tunable Gm‐C filter

In this paper, a new highly linear operational transconductance amplifier (OTA) based on triode‐mode input transistors is introduced. An analysis based on theoretical relations and simulation results is presented that aims to obtain the best operating points of triode‐mode and cascode transistors to achieve the highest linearity. The proposed analysis is utilized to design a linear pseudo‐differential OTA, benefiting a linear common mode feedforward and an appropriate common mode feedback circuit. The common mode feedforward circuit is also regulated in the same manner as main the transconductor to stabilize the output common mode voltage during tuning action and achieve higher common mode rejection ratio. Proposed OTA is used to implement a tunable low‐power linear Gm‐C filter. The cutoff frequency of the filter is tunable from 2.7 to 44 MHz while its power consumption changes from 3.5 to 8.5 mW in the entire tuning range. By applying input voltages up to 1.1 Vp‐p, the filter's IM3 remains less than −48 dB for various cutoff frequencies. The proposed OTA and filter are simulated in 0.18‐μ m CMOS technology with Hspice simulator. Copyright © 2017 John Wiley & Sons, Ltd.     

Multiple output differential OTA with linearizing bulk‐driven active‐error feedback loop for continuous‐time filter applications

A CMOS circuit realization of a highly linear multiple‐output differential operational transconductance amplifier (OTA) has been proposed. The presented approach exploits a differential pair as an input stage with both the gate and the bulk terminals as signal ports. For the proposed OTA, improved linearity is obtained by means of the active‐error feedback loop operating at the bulk terminals of the input stage. SPICE simulations of the OTA show that, for 0.35 µm AMS process, total harmonic distortion at 1.36Vpp is less than 1% with dynamic range equal to 60.1 dB at power consumption of 276 μW from 3.3 V supply. As an example, both single output and dual differential OTAs are used to design third‐order elliptic low‐pass filters. The cut‐off frequency of the filters is 1 MHz. The power consumption of the OTA‐C filter utilizing the dual output differential OTA is reduced to 1.24 mW in comparison to 2.2 mW consumed by the single output differential OTA‐C filter counterpart. Copyright © 2014 John Wiley & Sons, Ltd.     

0.5‐V fractional‐order companding filters

Novel configurations of fractional‐order filter topologies, realized through the employment of the concept of companding filtering, are introduced in this paper. As a first step, the design procedure is presented in a systematic algorithmic way, while in the next step, the basic building blocks of sinh‐domain and log‐domain integrators are presented. Because of the employment of metal–oxide–semiconductor (MOS) transistors operated in the subthreshold region, the derived filter structures offer the capability for operation in an ultra‐low‐voltage environment. In addition, because of the offered resistorless realizations, the proposed topologies are reconfigurable, in the sense that the order of the filter could be chosen through appropriate bias current sources. The performance of the derived fractional‐order filters has been evaluated through simulation and comparison results using the Analog Design Environment of the Cadence software and MOS transistor parameters provided by the Taiwan Semiconductor Manufacturing Company (TSMC) 180‐nm complementary MOS (CMOS) process. Copyright © 2014 John Wiley & Sons, Ltd.     

Design for testability of high‐order OTA‐C filters

A study of oscillation‐based test for high‐order Operational Transconductance Amplifier‐C (OTA‐C) filters is presented. The method is based on partition of a high‐order filter into second‐order filter functions. The opening Q‐loop and adding positive feedback techniques are developed to convert the second‐order filter section into a quadrature oscillator. These techniques are based on an open‐loop configuration and an additional positive feedback configuration. Implementation of the two testability design methods for nth‐order cascade, IFLF and leapfrog (LF) filters is presented, and the area overhead of the modified circuits is also discussed. The performances of the presented techniques are investigated. Fourth‐order cascade, inverse follow‐the‐leader feedback (IFLF) and LF OTA‐C filters were designed and simulated for analysis of fault coverage using the adding positive feedback method based on an analogue multiplexer. Simulation results show that the oscillation‐based test method using positive feedback provides high fault coverage of around 97%, 96% and 95% for the cascade, IFLF and LF OTA‐C filters, respectively. Copyright © 2016 John Wiley & Sons, Ltd.     

On the input common‐mode voltage range of CMOS bulk‐driven input stages

In this paper the response of a bulk‐driven MOS Metal‐Oxide‐Semiconductor input stage over the input common‐mode voltage range is discussed and experimentally evaluated. In particular, the behavior of the effective input transconductance and the input current is studied for different gate bias voltages of the input transistors. A comparison between simulated and measured results, in standard 0.35‐µm CMOS Complementary Metal‐Oxide‐Semiconductor technology, demonstrates that the model of the MOS transistors is not sufficiently accurate for devices operating under forward bias conditions of their source‐bulk pn junction. Therefore, the fabrication and the experimental evaluation of any solution based on this approach are highly recommended. A technique to automatically control the gate bias voltage of a bulk‐driven differential pair is proposed to optimize the design tradeoff between the effective input transconductance and the input current. The proposed input stage was integrated as a standalone block and was also included in a 1.5‐V second‐order operational transconductance amplifier (OTA)‐C lowpass filter. Experimental results validate the effectiveness of the approach. Copyright © 2010 John Wiley & Sons, Ltd.     

1‐V continuous‐time equalizers for multi‐gigabit short‐haul optical fiber communications

Two new CMOS analog continuous‐time equalizers for high‐speed short‐haul optical fiber communications are presented in this paper. The proposed structures compensate the limited bandwidth‐length product of 1‐mm step‐index polymer optical fiber channels (45 MHz, 100 m) and have been designed in a standard 0.18‐µm CMOS process. The equalizers are aimed for multi‐gigabit short‐range applications, targeting up to 2 Gb/s through a 50‐m step‐index polymer optical fiber. The prototypes operate with a single supply voltage of only 1 V and overcome the severe limitations suffered by the widely used degenerated differential pair caused by the low supply voltage. Copyright © 2012 John Wiley & Sons, Ltd.     

Ultra‐low voltage fractional‐order circuits using current mirrors

Fractional‐order blocks, including differentiators, lossy and lossless integrators as well as filters of order 1 + a (0 < a < 1), are presented in this paper. The proposed topologies offer the benefit of ultra low‐voltage operation; in addition, reduced circuit complexity is achieved compared to the corresponding companding schemes, which have been already introduced in the literature. The ultra‐low voltage operation is performed through the employment of metal oxide semiconductor transistors biased in the subthreshold region. The reduction of circuit complexity is achieved through the utilization of current mirrors as active elements for realizing the required building blocks. The performance of the proposed fractional‐order circuits has been evaluated through the Analog Design Environment of the Cadence software and the design kit provided by the Taiwan Semiconductor Manufacturing Company (TSMC) 180 nm complementary metal oxide semiconductor process. Copyright © 2015 John Wiley & Sons, Ltd.     

Balanced Gm‐C filters with improved linearity and power efficiency

A novel G_m‐C filter design technique is presented. It is based on floating‐gate metal oxide semiconductor (FGMOS) transistors and consists in a topological rearrangement of conventional fully differential G_m‐C structures without modifying the employed transconductors at transistor level. The proposed method allows decreasing the number of active elements (transconductors) of the filter. Moreover, high linearity is obtained at low and medium frequencies of the pass band. Drawbacks inherent to the use of FGMOS transistors are analyzed, such as large occupied area, high sensitivity to mismatch, or parasitic zeros in transfer functions. The features of the proposed technique are fully exploited in all‐pole G_m‐C filter design, specially implementing unity gain Butterworth transfer functions. Thus, two low‐power second‐order Butterworth G_m‐C filters have been designed and fabricated to compare the proposed FGMOS technique with their equivalent topologies obtained by a conventional design method. Measurement results for a test chip prototype in a 0.5‐µm standard complementary MOS process are presented, confirming the advantages of the proposed FGMOS design technique. Copyright © 2014 John Wiley & Sons, Ltd.     

1.2 V Sinh‐Domain allpass filter

A first‐order Sinh‐Domain allpass filter topology is introduced in this paper. It is constructed from a class‐AB current mirror and appropriately configured non‐linear transconductor cells. Due to the inherent class‐AB nature of Sinh‐Domain filters, the proposed topology offers the capability for handling currents at levels greater than that of the dc bias current level. Also, it offers the well‐known features of companding filters such as electronic adjustment of its frequency characteristics and the capability for operation in a low‐voltage environment. In addition, a four‐phase sinusoidal oscillator design example has been provided. The behaviour of the proposed topology has been evaluated and compared with other already known configurations, where the most important performance factors have been considered. Copyright © 2013 John Wiley & Sons, Ltd.     

Time‐mode circuits for analog computation

We introduce time‐mode circuits, a set of basic circuit building blocks for analog computation using a temporal step function representation for the inputs and outputs. These novel time‐mode circuits are low power, provide good noise performance and offer improved dynamic range. The design, IC implementation and detailed theoretical signal‐to‐noise ratio (SNR) analysis of a prototype time‐mode circuit—a weighted average computation circuit—are discussed. This new way of computation is studied with respect to existing conventional voltage‐mode and current‐mode circuits. Two possible applications of these time‐mode circuits are presented: an edge detection circuit for 16 pixels and a 3‐tap FIR filter that provides an SNR of 64 dB. Copyright © 2008 John Wiley & Sons, Ltd.     

FDCCII‐based electronically tunable voltage‐mode biquad filter

In this work, a voltage‐mode biquad filter realizing low‐pass, band‐pass and high‐pass characteristics is presented. The proposed filter, which employs two FDCCIIs, two grounded capacitors and two NMOS transistors, provides electronic tunability with the control voltage applied to the gate. NMOS transistors act as linear resistor. Furthermore, the proposed circuit still enjoys realization using a low number of active and passive components, no requirement with the component choice conditions to realize specific filtering functions, high input impedance, and low active and passive sensitivities performance. Simulation results using SPICE program are given to show the performance of the filter and verify the theory. Copyright © 2010 John Wiley & Sons, Ltd.     

Three‐stage nested‐Miller‐compensated operational amplifiers: Analysis,design, and optimization based on settling time

In analog signal‐processing applications, settling performance of the employed operational amplifiers (opamps) is usually of great matter. Under low‐voltage environment of modern technologies where only a few transistors are allowed to be stacked, three‐stage amplifiers are gaining more interest. Unfortunately, design and optimization of three‐stage opamps based on settling time still suffer from lack of a comprehensive analysis of the settling behavior and closed‐form relations between settling time/error and other parameters. In this paper, a thorough analysis of the settling response of three‐stage nested‐Miller‐compensated opamps, including linear and non‐linear sections, is presented. This analysis leads to a design methodology which determines the circuit requirements for desired settling time/error. Based on settling time, it allows optimizations in power consumption and area. Copyright © 2010 John Wiley & Sons, Ltd.     

Square‐root domain linear transformation filters

A new systematic method for designing square‐root domain (SRD) linear transformation (LT) filter is introduced in this paper. For this purpose, a substitution table containing the SRD LT equivalent of each passive element has been introduced. The proposed equivalents have been realized by employing appropriate SRD building blocks with low‐voltage operation capability. As a design example, a 3rd‐order SRD LT filter has been realized and its performance has been evaluated through simulation results. In addition, the most important performance factors of the SRD filter have been compared with those achieved by the SRD filters derived according to the leapfrog, wave, and topological emulation methods. Copyright © 2010 John Wiley & Sons, Ltd.     

A 0.5 V bulk‐driven voltage follower/DC level shifter and its application in class AB output stage

A simple realization of a 0.5 V bulk‐driven voltage follower/direct current (DC) level shifter designed in a 0.18 µm CMOS technology is presented in the paper. The circuit is characterized by large input and output voltage swings and a DC voltage gain close to unity. The DC voltage shift between input and output terminals can be regulated in a certain interval around zero, by means of biasing current sinks. An application of the proposed voltage follower circuit for realization of a low‐voltage class AB output stage has also been described in the paper. Finally, the operational amplifier exploiting the proposed output stage has been presented and evaluated in detail. Copyright © 2014 John Wiley & Sons, Ltd.