共查询到19条相似文献,搜索用时 132 毫秒
1.
随着系统芯片(SoC)集成更多的功能并采用更先进的工艺,它所面临的高性能与低功耗的矛盾越来越突出.动态电压调整(DVS)技术可以在不影响处理器性能的前提下,通过性能预测软件根据处理器的繁忙程度调整处理器的工作电压和工作频率,达到降低芯片功耗的目的.文中讨论了DVS技术降低功耗的可能性,介绍了如何利用两种不同的DVS技术让处理器根据当前的工作负荷运行在不同的性能水平上,以节省不必要的功耗. 相似文献
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综述了片上系统(SoC)低功耗多电压设计方法的研究进展.介绍了低功耗多电压设计方法的研究背景和国内外的研究现状.重点探讨了低电压、多电源电压、电源门控、动态电压频率缩减(DVFS)和自适应电压缩减(AVS)等多电压低功耗设计方法.最后,对低功耗多电压设计方法未来的发展趋势进行了预测和分析,认为DVFS和AVS等新颖的低功耗设计方法将成为未来学术界和工业界研究的热点. 相似文献
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对便携式系统设备而言,在采用目前90 nm和130 nm工艺进行新的系统级芯片(SoC)设计中,对整个系统功耗的优化变得与性能和面积的优化同等重要.为此,简单介绍了涵盖静态功耗和动态功耗的低功耗技术,同时提供了一种能够通过使用前向预测反馈的动态电压频率调节(DVFS)系统,并对该技术的可行性进行了建模分析,验证了自适应DVFS方式的有效性,同时也给出了评估DVFS仿真的有效途径. 相似文献
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SoC越来越成为设计的主流趋势,而应用系统对低功耗无止境的需求,使得SoC低功耗设计技术变得日益重要。本文首先介绍了低功耗的基本概念,包括原理、优化技术等,着重介绍了面向SoC的系统级功耗优化技术,最后展望了SoC低功耗设计的一些发展方向。 相似文献
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Juha Pennanen 《电子设计技术》2007,14(4):102-102
转换效率和调节质量这两方面的要求推动着电源管理从最初的LDO发展到今天效率超过90%的高精度、多模式DC/DC转换器.由于稳压器的效率已经达到了极限,现在的研究已经转向如何优化系统的效率,以满足电池供电和能量限制的便携设备的要求. 相似文献
6.
SoC在不同应用场景的频率不同,导致关键路径的时序余量会有较大的差异,在芯片设计阶段,为了保证芯片最坏情况下依然能够正常运行,增加了较大的电压余量,所以固定电压供电会造成不必要的功耗损失.基于最大程度节约功耗的需求,介绍了一种基于线下校准和延时链实时监测的自适应电压调节系统,实时监测电路时序,结合数字低压差线性稳压器(... 相似文献
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当今的设计师面对无数的挑战:一方面他们必须满足高技术产品不断扩展的特性需求,另一方面却不得不受到无线和电池装置的电源限制。没有任何技术在这方面的要求比SoC的设计更为明显,在这种设计中,高级工艺比从前复杂的多。然而,上述技术造成了新的电源问题。现代SoC系统的关键之一 相似文献
8.
在一些复杂的SoC中,往往要使用嵌入式存储器,而双边访问的嵌入式存储器(DARAM)常用于许多低功耗的场合。这样,用时钟的双边沿来控制存储器的读写数据是不可避免的。这种时钟用作数据(clock as data)的情况通常会在SoC设计的逻辑物理综合阶段产生很多时序收敛的棘手问题,时钟隔离电路恰好能解决这个问题。实践证明,这种改进的时钟电路结构大大减少了设计的时序收敛时间和设计流程的复杂度。 相似文献
9.
《电子与封装》2018,(2):40-45
为降低芯片功耗,提升性能,从系统级、结构级和RTL级3个层次提出了一种片上系统(System on Chip,SoC)芯片的低功耗设计方法,并在样片中得以验证。在系统级层面,根据SoC芯片的不同工作场合,在正常运行模式的基础之上,设计了睡眠、停止和待机3种低功耗模式。在结构级层面,将整个芯片划分为VDD、VDDA和VBAT3个电压域,以降低系统功耗。在RTL级,针对不同的模式切换,设计了时钟管理技术,实现了对不同模式下不同时钟的控制。仿真和实验结果证明了设计的合理性,实测数据表明,睡眠模式最多降低59.1%的功耗,停止和待机模式降低了3~4个数量级。 相似文献
10.
低功耗方法在SoC芯片设计中的应用 总被引:1,自引:0,他引:1
SOC芯片设计在集成电路设计中占据重要位置,低功耗设计是SoC设计过程中的重要环节。本文首先全面分析了CMOS电路的功耗组成和功耗估计的相关理论,随后从各个设计层次详细分析了SOC芯片低功耗设计的理论及其实现方法。 相似文献
11.
Hangbiao Li Bo Zhang Shaowei Zhen Pengfei Liao Yajuan He 《International Journal of Electronics》2013,100(9):1520-1534
A miniature high-efficiency fully digital adaptive voltage scaling (AVS) buck converter is proposed in this paper. The pulse skip modulation with flexible duty cycle (FD-PSM) is used in the AVS controller, which simplifies the circuit architecture (<170 gates) and greatly saves the die area and the power consumption. The converter is implemented in a 0.13-μm one-poly-eight-metal (1P8 M) complementary metal oxide semiconductor process and the active on-chip area of the controller is only 0.003 mm2, which is much smaller. The measurement results show that when the operating frequency of the digital load scales dynamically from 25.6 MHz to 112.6 MHz, the supply voltage of which can be scaled adaptively from 0.84 V to 1.95 V. The controller dissipates only 17.2 μW, while the supply voltage of the load is 1 V and the operating frequency is 40 MHz. 相似文献
12.
本文首先概述了TD-SCDMA终端的耗电特性,接着对动态电压与频率调节技术进行了分析,最后运用动态管理技术提出了一种基于动态电压与频率调节技术的终端省电方案,有效地延长了终端的工作时间. 相似文献
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14.
This paper presents an up-conversion mixer for 2.4-2.4835 GHz wireless sensor networks (WSN) in 0.18 μm RF CMOS technology. It was based on a double-balanced Gilbert cell type, with two Gilbert cells having quadrature modulation applied. Current-reuse and cross positive feedback techniques were applied in the mixer to boost conversion gain; the current source stage was removed from the mixer to improve linearity. Measured results exhibited that under a 1 V power supply, the conversion gain was 5 dB, the input referred 1 dB compression point was -11 dBm and the IIP3 was -0.75 dBm, while it only consumed 1.4 mW. 相似文献
15.
The impacts of aging and process variations on the performance of VLSI systems is increasing with each process generation. The conventional way to counteract them are extensive guard bands, which are calculated at system design time. Hence, they are necessarily worst case guard bands, i.e., most often too pessimistic. Current research tries to mitigate this by means of in-situ performance measurement based adaptive voltage scaling (AVS). The performance measurement is typically determined by means of dedicated sensors or canary logic. The parametrization of such AVS systems relies on assumptions regarding the relative behavior of the sensor and the application logic. Most published approaches use manually gained empirical data for this purpose. However, an automatic calibration procedure is needed for the practical application of these approaches. We propose such an automated calibration procedure and evaluate it on multiple FPGAs to consider the effects of aging and process variation. Furthermore, we use two designs to cover leakage power and dynamic power dominated scenarios. We achieve average power savings of 67% for a leakage dominated design and 48% for a test case with dominant dynamic power. Furthermore, we investigate the limitations of AVS systems regarding their capability to counteract fast disturbances, e.g., voltage drop. 相似文献
16.
In this paper we propose two dynamic voltage scaling (DVS) policies for a GALS NoC, which is designed based on fully asynchronous switch architectures. The first one is a history-based DVS policy, which exploits the link utilization and adjusts the voltages of different parts of the router among a few voltage levels. The second one is a FIFO-adaptive DVS, which uses two FIFO threshold levels for decision making. It judiciously adjusts supply voltage of each switch among only three voltage levels. The introduced architecture is simulated in 90 nm CMOS technology with accurate Spice simulations. Experimental results show that the FIFO-adaptive DVS not only lowers the implementation cost, but also in a 86 % saturated network achieves 36 % energy-delay product (ED) saving compared to the DVS policy based on link utilization. 相似文献
17.
高压电力线载波通信已有近百年的历史,它在电力调度话音通信、电力系统远动装置数据采集等方面取得了卓有成效的应用,但是利用一个台区的低压电力线建立Internet接入网是近几年来国际上刚刚兴起的技术。本文论述的电力线通信(Power Line Communications)计算机网络(以下简称PLC网络)是以电力线为通信介质实现数据传输或建立计算机网络的相关技术研究。由于低压电力线的普及程度比其他任何通信介质都广泛,研究电力线作为信息传输介质在技术和经济方面都有十分重要的意义。 相似文献
18.
Patrice Russo Firas Yengui Gael Pillonnet Sophie Taupin Nacer Abouchi 《Microelectronics Journal》2013
We present an optimization of the voltage scaling algorithm in low power audio class-G amplifier for headphones application to allow longer playback time. The optimization approach minimizes the voltage difference between the internal audio amplifier power supply and its output signal over a large range of operating conditions. The modeling is based on a behavioral model enabling accurate and rapid evaluation of efficiency and audio quality with realistic input stimuli. The model validated in practice is used to optimize the voltage scaling using only few power supply levels. Thanks to a global search algorithm followed by a local one, the optimization gives the better parameters for voltage scaling algorithm while keeping a good audio quality. The proposed configuration increases the efficiency up to 48% at nominal operation. 相似文献