UHF RFID标签芯片模拟射频前端设计

对射频识别标签芯片系统结构及工作原理进行分析,设计应用于符合ISO18000—6C／B两种标准的UHFRFID标签芯片的模拟射频前端,主要包括整流电路、稳压电路、调制／解调电路、上电复位及时钟产生电路。模拟射频前端芯片采用TSMC0．18μm CMOS混合信号工艺流片验证。测试结果表明,所研制的模拟射频前端性能满足UHF RFID标签芯片系统要求。     

ISO15693非接触式IC卡射频前端电路的设计

介绍了ISO15693非接触式IC卡射频前端电路,采用一种巧妙的整流电路,提高了整流效率。同时,使用了一种适用于ISO15693非接触式卡片的简单稳压电路结构,有助于信号的解调,并且使卡片在接收到的信号为10%ASK和100%ASK两种调制模式时都能正常工作。芯片测试结果显示,电源产生电路能够产生一个2.2~3.8 V的直流电压,解调电路能够在2.0~3.8 V电压下可靠稳定地工作;在ISO15693规定的最小场强0.15 A/m处,整个芯片的电源电压为3.3V,且功耗小于60μW。     

无源超高频RFID标签的模拟前端电路设计

设计完成了一款无源超高频RFID标签的低功耗模拟前端电路。采用了一种新的阈值消除技术,整流电路的能量转换效率可以达到30%以上;使用一种低功耗的稳压电路,为数字电路提供稳定的1 V电源电压的同时功耗为500 nA。此外提出了一种等效灵敏度的测试方法,可以简便地获得标签芯片的激活功率水平。该设计采用TSMC 0.18μm工艺,整个芯片面积为700μm×800μm。测试结果显示:稳压电路可以输出稳定的0.95 V电压,解调模块可以正确调解幅度大于150 mV的天线信号。根据等效灵敏度测试方法,测得本设计的灵敏度约为-14.9 dBm。     

ISO15693非接触式IC卡射频前端电路的设计

介绍了ISO15693非接触式IC卡射频前端电路,采用了一种巧妙的整流电路,提高了整流效率。同时使用了一种适用于ISO15693非接触式卡片的简单的稳压电路结构,有助于信号的解调,并且使卡片在接收到的信号为10％ASK和100％ASK两种调制模式时都能正常工作。芯片测试结果显示：电源产生电路能够产生2．2V-3．8V的直流电压,解调电路能够在2．0V-3．8V电压下可靠稳定的工作;在ISO15693规定的最小场强0．15A／M处,整个芯片的电源电压为3．3V,且功耗小于60μW。     

一种无源植入式神经刺激器中模拟前端的设计

设计了一种可应用于超高频无源植入式神经刺激器的模拟前端电路。对无源植入式芯片模拟前端的系统架构进行了论述,简述了前端架构中各个模块的工作原理,通过优化系统结构,减小了系统复杂度和版图面积。模块包括整流电路、电源管理电路、调制解调电路、上电复位电路和时钟产生电路。其中,整流电路工作时,效率可达到45%以上,并且能提供两种不同的工作电压。使用Cadence Spectre对设计电路进行仿真,并通过TSMC 0.35 μm BCD工艺进行流片验证。结果显示,该模拟前端的直流功耗为0.06 mW,芯片面积为0.4 mm²,可以满足植入式神经刺激器的要求。     

一种13.56MHz无源射频识别模拟前端的设计

提出了一种基于ISO/IEC18000-3协议的高频13.56MHz射频识别(RFID)标签芯片的模拟前端电路结构,采用Chartered 0.35μm EEPROM工艺进行流片验证。该芯片实现了无源RFID标签芯片通信时所需的整流、稳压供电、时钟恢复、信号解调以及副载波调制的全部功能。     

超高频无源射频标签的射频接口设计

对射频标签能量供应原理进行了详细的理论分析,设计了一个超高频远距离无源射频标签芯片的射频接口电路,包括电源恢复电路、稳压电路及解调整形电路。解决了超高频无源射频标签远距离能量供应和信号获取的问题。射频接口电路采用UMC 0.18μm混合信号工艺流片验证。测试结果表明,射频接口电路的性能可满足超高频远距离无源射频标签芯片的要求。     

基于EPC Class0协议无源电子标签射频前端设计

分析了RFID系统的组成和基本原理,针对超高频EPC Class0协议,提出电子标签前端结构及参考电路,包括整流器、稳压源、能量开启、脉宽解调、反向调制、振荡器、时钟校准等部分。采用Chartered 0.35μm CMOS工艺进行流片,整个前端模块工作电压(不包括整流电路)3.3V,电流13.8μA。最后给出芯片照片及测试结果。     

2.45GHz电子射频标签模拟前端芯片的研制

分析了RFID系统的组成和基本原理,针对超高频EPC C1G2协议,提出半无源及有源电子标签前端结构及参考电路,包括整流器、偏置单元、上电复位、解调、反向散射调制、振荡器等部分.采用多种方法,极大程度上实现了电路整体的低功耗,并且采取了限幅、ESD电路,保障了电路的稳定性.采用标准CMOS工艺,设计出了低功耗、低电压工作的2.45 GHz射频模拟前端芯片电路,芯片在0.8～1.8 V电压内均可正常工作.芯片的静态工作电流为2μA,芯片工作时,平均工作电流约为65μA.     

无源UHF RFID电子标签模拟前端设计

提出了一种符合ISO/IEC 18000-6B标准的高性能无源UHF RFID电子标签模拟前端,在915MHz ISM频带下工作时其电流小于8μA.该模拟前端除天线外无外接元器件,通过肖特基二极管整流器从射频电磁场接收能量.该RFID模拟前端包括本地振荡器、时钟产生电路、复位电路、匹配网络和反向散射电路、整流器、稳压器以及AM解调器等.该芯片采用支持肖特基二极管和EEPROM的Chartered 0.35μm 2P4M CMOS工艺进行流片,读取距离大于3m,芯片面积为300μm×720μm.     

低压低功耗无源UHF RFID标签芯片模拟前端电路的设计

本文从设计符合EPCTM C1G2协议的超高频无源射频识别标签芯片的角度出发,对RFID标签芯片模拟前端电路进行设计.通过对各个关键电路的功耗与电源进行优化,实现了一个符合协议要求的低电压、低功耗的超高频无源RFID标签芯片的模拟前端.该UHF RFID标签模拟前端设计采用SMIC 0.18 μm EEPROM CMOS工艺库.仿真结果表明,标签芯片模拟前端的整体功耗控制在2.5 μW以下,工作电源可低至1 V,更好地满足了超高频无源射频识别标签芯片应用需求.     

A fully integrated analog front-end circuit for 13.56 MHz passive RFID tags in conformance with ISO/IEC 18000-3 protocol

A fully integrated analog front-end circuit for 13.56 MHz passive RFID tags is presented in this paper. The design of the RF analog front-end and digital control is based on ISO/IEC 18000-3 MODE 1 protocol. This paper mainly focuses on RF analog front-end circuits. In order to supply voltage for the whole tag chip, a high efficiency power management circuit with a rather wide input range is proposed by utilizing 15.5 V high voltage MOS transistors. Furthermore, a high sensitivity, low power consumption 10% ASK demodulator with a subthreshold-mode hysteresis comparator is introduced for reader-to-tag communication. The tag chip is fabricated in 0.18-μm 2-poly 5-metal mixed signal CMOS technology with EEPROM process. An on-chip 1 kb EEPROM is used to support tag identification, data writing and reading. The core size of the analog front-end is only 0.94×0.84 mm² with a power consumption of 0.42 mW. Measured results show that the power management circuit is able to maintain a proper working condition with an input antenna voltage range of 5.82–12.3 V; the maximum voltage conversion ratio of the rectifier reaches 65.92% when the tag antenna voltage is 9.42 V. Moreover, the power consumption of the 10% ASK demodulator is only 690.25 nW.     

用于射频标签的低功耗上电复位电路

介绍了一种用于射频标签芯片中数字逻辑部分的上电复位电路。该上电复位电路适应于低电源电压的芯片,改变MOS晶体管的参数以及延迟时间可以调节脉冲的宽度和数字门电路加宽脉冲的宽度,通过反馈管,电路能够抵抗比较大的电源电压噪声影响。电路产生上电复位信号脉冲后,通过反馈控制使能端信号关断整个电路,实现低功耗。电路采用华虹NEC公司0.13μm标准CMOS工艺流片,测试结果表明,此电路能够输出有效的脉冲信号;脉冲过后的导通电流基本为0。FPGA平台的验证表明,芯片输出的POR信号能够正确启动标签中的数字基带芯片,输出信号有效。     

A precision low-power analog front end in 180 nm CMOS for wireless implantable capacitive pressure sensors

This paper presents a new capacitance to voltage analog-front end (AFE) designed in 180 nm CMOS technology for wireless implantable applications. This AFE consists of a Low-dropout regulator (LDO), bandgap reference (BGR), switched-capacitor (SC) sampler, SC op-amp and oscillator. The LDO regulates the wireless power supply coming from an off-chip rectifier and provides a stable and accurate DC voltage. Capacitance is converted to a discrete voltage by a SC sampling circuit and then amplified by a SC op-amp. Both of SC sampling and SC op amp circuits form a correlated double sampling scheme. This AFE is designed to sense a capacitance range from 6 pF to 7 pF (300–1000 mmHg) corresponding to a 0.68 V–1.07 V discrete output voltage with a sampling frequency of 1.63 KHz. This AFE has a sensitivity of 0.39 mV/fF, average power consumption of 201 μW and 3.25% accuracy operating over a 2.1 V–3.3 V rectified wireless supply voltage and −40 °C ~125 °C temperature range.     

A Passive UHF RF Identification CMOS Tag IC Using Ferroelectric RAM in 0.35-μm Technology

A passive UHF RF identification (RFID) tag IC with embedded 2-KB ferroelectric RAM (FeRAM) for rewritable applications enables a 2.9 times faster read-and-write transaction time over EEPROM-based tag ICs. The resulting FeRAM-based tag has a nominally identical communication range for both read and write operations, which is indispensable for data write applications. The evaluated tag communication range with a folded dipole antenna is from 0 m to 4.3 m, at the 953-MHz carrier frequency with 4-W transmitting Effective Isotropic Radiated Power (EIRP) from a reader/writer. The developed tag IC features two circuit blocks to maximize the communication range in 0.35-mum CMOS/FeRAM technology. First is a CMOS-only full-wave rectifier, which can improve the measured efficiency by up to 36.6% by reducing the input parasitic capacitances and optimization of multiplier structure. This efficiency is more than twice that of previously-published results. Second is a low-voltage current-mode ASK demodulator to accommodate a low-breakdown voltage of FeRAM, which converts the ASK power modulation into a linearly modulated current over an incoming power range of 27 dB, corresponding to the entire communication range. The developed demodulator can thus resolve the primary design tradeoff issue between device protection and detection sensitivity in the conventional voltage-mode demodulator     

Switched-capacitor FSK modulator and demodulator in CMOS technology

A switched-capacitor FSK modulator/demodulator built in silicon-gate CMOS technology is described. The modulator is based on a programmable harmonic oscillator using two stray-insensitive integrators. The centerpiece of the FSK demodulator is a switched-capacitor voltage-controlled oscillator. A simple post-detection processor restores the digital data. Both circuits have been designed for the 600-baud modem channel with 1500 Hz center frequency and /spl plusmn/200 Hz frequency shifts, but the demodulator operates in the 1200-baud channel as well. Due to dynamic biasing the operational amplifiers feature high slew rate, high voltage gain, and low power for capacitive loads.     

Low leakage and high CMRR CMOS differential amplifier for biomedical application

In order to increase user experience in using near field communication smartcard, analog front-end (AFE) module is required to provide a sufficient and a well-regulated voltage regardless the distance between the card and the reader. A highly stable AFE design for energy harvesting purpose is introduced in this paper. The design consists of antenna, rectifier, voltage limiter, bandgap reference, and low-dropout (LDO) voltage regulator circuit. The antenna is designed to resonate at 13.56 MHz as regulated by ISO/IEC 14443-2. In order to simplify the implementation using 0.18 μm CMOS process, a full-wave rectifier circuit is built of all low-threshold-voltage diode-connected PMOS transistors. To protect the system from undesired excessive input voltages, a voltage limiter circuit is included in the module. Moreover, control and maintain a stable supply voltage for the whole system, a robust LDO voltage regulator and bandgap circuits are specially designed for this purpose. The LDO is able to provide a stable 1.8 V of supply voltage with a sub-1% ripple factor even under a low input current as low as 20 mA.     

A Long-Range UHF-Band Passive RFID Tag IC Based on High- $Q$ Design Approach

We present a fully integrated long-range UHF-band passive radio-frequency-identification tag chip fabricated in 0.35-$muhbox{m}$ CMOS using titanium (Ti/Al/Ta/Al)–silicon Schottky diodes. The diodes showed low turn-on voltages of 95 and 140 mV for diode currents of 1 and 5 $muhbox{A}$, respectively. In addition, the Schottky diodes exhibited low-resistive loss, and a high-$Q$ -factor design approach was exploited to achieve a long read range for the tag integrated circuit (IC). An optimized voltage multiplier resulted in an excellent sensitivity of $-$ 14.8 dBm and corresponding power-conversion efficiency of 36.2% for generating an output voltage of 1.5 V at 900 MHz. The range analysis of the measured multiplier performance indicated an operating range of more than 9 m at 4-W Effective Isotropically Radiated Power reader power. The subthreshold-mode operation of an ASK demodulator allowed ultralow power operation. Under power consumption as low as 27 nW, the demodulator supported a data rate of 150 kb/s and a modulation depth of 40%. A new architecture for generating a stable system clock (2.2 MHz) for the tag IC was employed to deal with supply voltage and temperature variations. Measurements showed that the clock generator had an error of 0.91% from the center frequency owing to an 8-b digital calibration scheme.      

基于电流模式的ASK解调器

设计了一种工作在电流模式下的ASK解调器,电路首先将电压信号转换为电流信号,并对电流信号进行延时,然后将延时电流与原始电流进行比较,获取信号的边沿位置,最后用RS触发器还原出最终数据。该解调器可以在一个比较宽的供电电压范围内解调出深度更浅的ASK信号,可以应用到不同标准的RFID标签中,而且电路受工艺变化的影响非常低。电路采用HHNEC 0.35μm5 V CMOS工艺设计,仿真结果表明,供电电压在2.6~5 V之间,在此电压范围内解调器至少可以解调深度为5%的ASK信号。     

超高频无源RFID标签的一些关键电路的设计

本文针对超高频无源RFID标签芯片的设计,给出了一些关键电路的设计考虑。文章从UHFRFID标签的基本组成结构入手,先介绍了四种电源恢复电路结构,以及在标准CMOS工艺下制作肖特基二极管来组成倍压电路的解决方案。然后针对电源稳压电路,提出了串联型和并联型两种稳压电路。文章针对ASK包络解调电路,提出了新的泄流源的设计。最后,文章介绍了启动信号产生电路的设计考虑。