移位寄存器的Multisim仿真

介绍用Multisim仿真软件分析移位寄存器逻辑功能的方法,验证了4-D触发器构成的移位寄存器的逻辑功能。用Multisim仿真软件中的字组产生器产生的信号作为移位寄存器的时钟脉冲和输入数据,字组内容反映移位寄存器的输入信号和控制信号,用Multisim中的逻辑分析仪多踪同步显示各输入信号、控制信号和输出信号波形,直观地描述移位寄存器的工作过程。所述方法创新地解决了移位寄存器工作过程无法用实验仪器验证的问题。     

2-phase circulating shift register for switched-capacitor N-path filters

A novel circulating shift register for switched-capacitor N-path filters is presented. The configuration affords a means of increasing the allowable discharge time for the shift register capacitors and eliminates clock feedthrough at the signal frequency. The shift register employs a simple 2-phase clock signal for any number of paths.     

环形移位计数器在彩灯控制电路中的应用

双向移位寄存器是一种中规模集成电路,可构成移位寄存器型计数器。文中介绍了双向移位寄存器的功能．以及由其构成的环形移位计数器的电路结构和输出状态。设计并论述了由环形移位计数器控制的单灯单向和双灯反向两种彩灯控制电路,说明对于较简单的彩灯控制要求,可以实现结构简单、稳定可靠、经济适用的控制电路。     

A 512-bit shift register using compact two-phase single fluxquantum clock generators with large margins and low power

A 512-b shift register was built and tested up to 14.5 GHz. The shift register uses a two-phase clock which is generated by coupling a master control line over many asymmetrically biased two-junction SQUIDs. Compared with other shift registers with Josephson transmission lines to deliver clock, this new clock system provides short delay, low power dissipation, and large DC bias margins. The shift register uses about 3000 Nb/AlO_x/Nb Josephson junctions and consumes about 0.1 mW     

一种新型低功耗准动态移位寄存器的模拟

提出一种低功耗准动态移位寄存器电路 ,这种电路静态功耗几乎为 0 ,仅仅存在动态功耗 ;是一种无比电路 ,所有的开关和反相器晶体管按最小尺寸进行设计 ,电路简单 ,面积小 ;该种电路不存在电荷的再分配 ,漏电流损失的电荷可从电源补充。采用 1 .2μm的 CMOS工艺 ,用 PSPICE8.0对该电路进行仿真验证。这种低功耗准动态移位寄存器电路已成功用作 CMOS图像传感器的读出扫描电路。     

Nonsingularity of Feedback Shift Registers of Degree at Most Three over a Finite Field

As a kind of generators of pseudo-random sequences, the Feedback shift register (FSR) is widely used in channel coding, cryptography and digital communication. A necessary and sufficient condition for the nonsingularity of a feedback shift register of degree at most three over a finite field is established. Using the above result, we can easily determine the nonsingularity of a feedback shift register from the algebraic normal form of the corresponding feedback function.     

适用于三值线性反馈移位寄存器的CMOS触发器

为了省免多值线性反馈移位寄存器中存在的常量乘运算电路，本文以三值逻辑为例，提出了具有Q-2Q双轨输出的三值CMOS触发器的设计，它可与传统的三值模和电路配合，即可实现三值线性反馈移位寄存器。这不仅简化了电路结构，并可提高电路的工作速度，PSPICE模拟证实了Q-2Q触发器设计具有正确的逻辑功能，此设计思想可推广至基数更高的多值线性反馈移位寄存器电路的设计。     

A nonvolatile charge-addressed memory (NOVCAM) cell

A nonvolatile charge-addressed memory (NOVCAM) cell is described in a 64-bit shift register configuration. The charge address is performed by a charge-coupled device (CCD) shift register and the information is stored in metal-nitride-oxide-silicon (MNOS) nonvolatile sites located in parallel with the CCD shift register. The tunneling electric field strength across the thin-oxide MNOS structure is controlled by the magnitude of the charge transferred from the CCD register. The write, erase, and read modes of operation are discussed with typical /spl plusmn/20 V 10 /spl mu/s write/erase, and 2 V 2 /spl mu/s read conditions. Readout is accomplished by parallel stabilized charge injection from a diffused p/n junction to minimize access time to the first bit.     

一种基于查找表的移位寄存器链的设计

提出了一种基于查找表的移位寄存器链的设计,以查找表的配置存储单元作为移位模块,以查找表的输入信号作为移位地址选择信号,通过对时钟和写使能的控制进行移位操作。1个查找表最大实现32个时钟周期的移位操作,4个查找表通过配置,可实现4条相互独立的32位移位寄存器链,或首尾级联实现一个128位的移位寄存器链。基于28 nm工艺,对所设计的结构进行了仿真和优化,并对电路进行了多项目晶圆流片。测试结果与仿真匹配良好,实现了32×4和128×1的移位功能,且最高工作频率达到500 MHz,与参考芯片相比,性能提高了10%。     

一种用于SAR A/D转换器的高速移位寄存器

基于65 nm标准 CMOS工艺,提出了一种单次触发的动态D型触发器。基于这种D型触发器,设计了一种用于逐次逼近型(SAR)A/D转换器的高速移位寄存器。在传统的SAR A/D转换器转换过程中,比较器每比较1次,逻辑模块就进行1次移位和1次锁存,每1次移位延迟约为2个D触发器的工作时间,因此,限制了整个系统的转换速度。相比于传统的移位寄存器,本文设计的高速移位寄存器兼具移位和锁存的特点,仅需要传统结构一半数量的D触发器就能实现输出移位和锁存功能。这种寄存器结构能够将A/D转换器的转换速度提升45%,且功耗更小。     

一种有效的RGPO干扰鉴别算法及性能分析

本文研究目标跟踪时的距离门后拖(RGPO)干扰鉴别问题,分析了现有χ²检验算法的不足,在χ²检验算法的基础上,提出了一种采用信号似然比预处理和移位寄存器后处理相结合的鉴别算法,称之为Chi+SLR+register算法.该算法在最佳寄存器长度下,能使误判概率最小.在相当宽的寄存器长度范围内,该算法都有很好的鉴别性能.此外,该算法在有SOJ干扰时,也能保持高的鉴别率,因而是一种更有效的RGPO干扰鉴别算法.     

Analog performance limitations of charge-transfer dynamic shift registers

Charge transfer dynamic shift register operation is described and a linearized analysis presented to relate the charge transfer properties to the performance of an n-stage register. An approximate small signal equivalent circuit is also derived to illustrate the similarities to a matched transmission line and the reactive and resistive elements of the line are related to charge transfer and loss characteristics of each stage of the register. The results are expected to be applicable to charge coupled devices and shift registers based on bucket brigade electronics.     

Fibonacci and Galois representations of feedback-with-carry shiftregisters

A feedback-with-carry shift register (FCSR) with "Fibonacci" architecture is a shift register provided with a small amount of memory which is used in the feedback algorithm. Like the linear feedback shift register (LFSR), the FCSR provides a simple and predictable method for the fast generation of pseudorandom sequences with good statistical properties and large periods. In this paper, we describe and analyze an alternative architecture for the FCSR which is similar to the "Galois" architecture for the LFSR. The Galois architecture is more efficient than the Fibonacci architecture because the feedback computations are performed in parallel. We also describe the output sequences generated by the d-FCSR, a slight modification of the (Fibonacci) FCSR architecture in which the feedback bit is delayed for d clock cycles before being returned to the first cell of the shift register. We explain how these devices may be configured so as to generate sequences with large periods. We show that the d-FCSR also admits a more efficient "Galois" architecture     

Experimental SFQ interferometer shift register prototype with Josephson junctions

A shift register prototype has been implemented with lead-alloy technology. Single-flux quanta have been shifted in both directions by local magnetic fields with a maximum repetition frequency of 250 MHz. The absence or presence of a flux quantum at a given position is read out nondestructively. The speed and the miniaturisation potential of the proposed shift register is discussed.     

Linear equivalence of certain BRM shift-register sequences

A theorem given by Albert is used to show that if a shift register of length m is used to clock another shift register of length n through a binary rate-multiplier, then it can easily be arranged that the output has a linear equivalence of (2m ? 1)n and a period of (2m ? 1)(2n ? 1).     

一种可重构线性反馈移位寄存器设计

提出了一种可重构线性反馈移位寄存器的设计。在设计中,针对Fibonacci和Galois两种类型的反馈结构分别采用了可重构的设计,并且支持混合反馈结构,线性反馈移位寄存器反馈抽头和插入点可选,长度可变并且可以通过链接支持超长线性反馈移位寄存器。在XC5VLX30器件上实现延时为4.808ns,LUT和触发器的个数为2279和1575。能够用于伪随机序列生成等应用。     

Fast reconstruction of clock-control sequence

Two fast techniques for reconstructing the initial state of the clock-control shift register in the shrinking generator, one based on list decoding and the other on information set decoding, are investigated. Both start from computing the a posteriori probabilities for the clock-control bits from a known segment of the output sequence, under the assumption that the initial state of the clock-controlled shift register is already recovered     

Transform decoding of BCH codes over Zm

For BCH codes with symbols from rings of residue class integers modulo m, denoted by Z_m , we introduce the analogue of Blahut's frequency domain approach for codes over finite fields and show that the problem of decoding these codes is equivalent to the minimal shift register synthesis problem over Galois rings. A minimal shift register synthesis algorithm over Galois rings is obtained by straightforward extention of the Reeds-Sloane algorithm which is for shift register synthesis over Z_m .     

Design and testing of data-driven self-timed RSFQ shift register

We report design, implementation and testing of a superconductive rapid single flux quantum (RSFQ) shift register based on a data-driven self-timed (DDST) architecture, and demonstrated the validity of this asynchronous design approach. In the DDST architecture, a clock signal is localized within the basic modules, and complementary data signals are used between the modules to transmit timing information. A larger system is simply an array of the basic modules and no extra timing consideration is required. Monte Carlo analysis on a 4-bit DDST shift register has shown that a 40-kbit shift register operating at 20 GHz can be built by using the present Nb Josephson technology. We have observed fully correct operation of a cascade of two 4-bit DDST shift registers with dc bias voltage margin of ±15% at low frequency and ±10% at 20 GHz.     

二元给定序列非线性移位寄存器的综合与产生

依据非线性移位寄存器的原理，文中讨论二元给定序列非线性反馈移位寄存器的综合算法，用C语言编程．找到了产生该序列的非线性移位寄存器。借助EDA技术，以FPGA为硬件基础，经过设计优化构成定长序列和给定周期序列的伪随机序列发生器，并进行了仿真实验，用硬件实验证实了设计的合理性。