Compact Modeling of MOSFET Wearout Mechanisms for Circuit-Reliability Simulation

The integration density of state-of-the-art electronic systems is limited by the reliability of the manufactured integrated circuits at a desired circuit density. Design rules, operating voltages, frequencies, and temperatures are precisely chosen to ensure correct product functional operation over its intended lifetime. Thus, in order to obtain the overall performance and functionality bounded by various design and manufacturing constraints, the integrated circuit reliability must be modeled and analyzed at the very beginning of design stages. This paper reviews some of the most important intrinsic wearout mechanisms of MOSFETs (including hot-carrier injection, time-dependent dielectric breakdown, and negative bias temperature instability) and introduces new accelerated-lifetime and SPICE compact models of these wearout mechanisms. Based on these circuit-aging models, a new SPICE reliability simulation approach is proposed and demonstrated with a simplified SRAM design on a commercial 90-nm technology to help designers understand device-failure behaviors, predict circuit reliability, and improve product robustness.     

Reliability of pFET EEPROM with 70-/spl Aring/ tunnel oxide manufactured in generic logic CMOS Processes

We investigate the reliability of pFET-based EEPROMs with 70-/spl Aring/ tunneling oxides fabricated in standard foundry 0.35-/spl mu/m, 0.25-/spl mu/m, and 0.18-/spl mu/m logic CMOS processes. The floating-gate memory cell uses Fowler-Nordheim tunneling erase and impact-ionization generated hot-electron injection for programming. We show that charge leakage is dominated by the leakage through interlayer dielectrics. We propose a retention model and show the data retention lifetime exceeds 10 years. These results demonstrate the feasibility of producing nonvolatile memory using standard logic processes that have a 70-/spl Aring/ oxide.     

Wafer level reliability and lifetime analysis of InGaAsP/InP quantum-well Fabry-Perot laser diode

This paper investigated the reliability of semiconductor 1.3-/spl mu/m multiquantum-well (MQW) Fabry-Perot laser diodes (LDs) in a quarter 2-in wafer level that are measured to have uniform threshold currents, slope efficiencies, and wavelengths within 4% of the maximum deviation. By performing the accelerated aging test under a constant optical power of 3 mW at 85/spl deg/C for 2100 h, the lifetime of the fabricated optoelectronic devices was estimated, where the failure rate was matched on the fitted line of the lognormal distribution model resulting in the mean-time-to-failure (MTTF) of 2/spl times/10/sup 6/ h operating at room temperature.     

New SRAM design using body bias technique for low‐power and high‐speed applications

In this paper, a new SRAM cell with body‐bias actively controlled by a control circuit and word line is introduced to realize low‐power and high‐speed applications. The cell uses two word lines, which vary between positive and negative voltage levels to control the body bias of cell's transistors. In this design, using a peripheral control circuit with the least possible number of transistors, the access time is decreased and also a trade‐off between static and dynamic power consumption is provided. Compared to a conventional SRAM cell, the proposed cell reduces the static power consumption by 82% and improves the read performance by 40% and the write performance by 27%. Copyright © 2013 John Wiley & Sons, Ltd.     

BTI characteristics and mechanisms of metal gated HfO/sub 2/ films with enhanced interface/bulk process treatments

Significant deviations in BTI characteristics for metal gate HfO/sub 2/ films compared to silicon oxide based films prove that conventional reliability models based on SiO/sub 2/ films can no longer be directly applied to HfO/sub 2/ based MOSFETS. This study shows the use of conventional accelerated reliability testing in the Fowler-Nordheim tunneling regime to extrapolate time to failure at operating voltages (direct tunneling regime) overestimates device lifetimes. Additionally, unlike conventional gate oxides, the slope of /spl Delta/V/sub t/ versus time (or the rate of charge trapping) in HfO/sub 2/ MOSFETS is dependent on stress voltage. The HfO/sub 2/ based metal gated nMOSFETS show poor PBTI characteristics and do not meet the 10 year lifetime criterion for threshold voltage stability. On the other hand, HfO/sub 2/ based pMOSFETS show superior NBTI behavior and meet the 10 year lifetime criterion. These results are contrary to the observations with conventional gate dielectrics. This paper explores the anomalous charge trapping behavior and provides a comprehensive study of the PBTI characteristics and recovery mechanisms in metal gated HfO/sub 2/ films.     

Design of improved‐reliability nanocircuits with mixed NBTI‐ and HCI‐aware gate‐sizing formulation

Negative bias temperature instability (NBTI) and hot carrier injection (HCI) are two important processes of reliability concern in nano‐scale integrated circuits. A circuit‐level design technique to combat NBTI degradation is gate oversizing. This paper presents a new technique based on PMOS and NMOS resistance variation for the NBTI‐ and HCI‐aware gate‐sizing problem for the first time. In this technique, the area of the circuit is minimized with constraints on degraded delay due to NBTI and HCI and the transitor size. Expreimental results for several gates and ISCAS'85 benchmark circuits show that this technique imposes an area overhead of less than 1% with respect to baseline design in most cases. © 2013 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

TDDB Data Generation for Fast Lifetime Projections Based on V-Ramp Stress Data

Reduced failure rates required by the industry lead to increased costs and time loss for the chip manufacturer since the efforts for continuous process improvements, qualification, screening, and increased test coverage are generally not paid by the customer. However, related costs can be reduced by improved/accelerated reliability testing methods and an approach to a knowledge-based and application-specific qualification and process monitoring strategy. One example of saving time (and costs) during gate oxide reliability testing is given in this paper, showing that time-dependent dielectric breakdown (TDDB) data for lifetime extrapolation and quality assessment can be generated from linear ramped voltage test (RVT) data with high accuracy. Given the parameter of the RVT stress profile, the concept of equivalence is successfully applied to convert stress time data at each ramp stress level to corresponding accumulated equivalent ages at any one stress level. Taking into account these ages until breakdown, failure probabilities with the model parameters of the stress-life relationship being the only fitting parameters can directly be computed and converted to TDDB failure distributions.     

One-sided 10T static-random access memory cell for energy-efficient and noise-immune internet of things applications

This paper presents a one-sided 10-transistors static-random access memory (SRAM) cell appropriate for the internet of things (IoT) applications in which energy-efficient SRAM cells are necessary to raise the battery lifetime. The bit-cell core of the proposed SRAM cell is composed of two inverters with different structures based on the gate-wrap-around (GWA) carbon nanotube (CNT)-gate-diffusion input (GDI) technique and only one-bit line to perform both read and write operations to minimize active power consumption. The proposed bit-cell uses a transmission gate network and write-assist schemes to significantly improve the write-ability and stack read-decoupling technique to enhance hold-/read-stability. Moreover, a memory mini-array has been implemented using the proposed cell along with all the principal circuitries. Extensive Monte Carlo (MC) simulations show that write/hold/read static noise margins (SNMs) are improved by about 1.252, 1.196, and 1.152 times, respectively. Also, the results of evaluating the write- and read-yield parameters for the proposed SRAM bit-cell are about 22% and 13% better than counterpart bit-cell designs, respectively. In addition, the bit error rate (BER) and energy dissipation parameters for the proposed memory cell are almost 61% and seven times higher than the studied SRAM bit-cell in the same simulation process. Finally, to evaluate the effectiveness of the proposed SRAM bit-cell in the real-world application, a memory array architecture with an online (or off-chip) adaptive power supply voltage based on a hardware algorithm for storing digital images at a minimum energy dissipation is proposed. Our simulation results emphasize that the proposed memory array can be a good candidate for energy-efficient and noise-immunity IoT platforms.     

A FinFET SRAM cell design with BTI robustness at high supply voltages and high yield at low supply voltages

In this paper, a SRAM cell structure which uses pMOS access transistors and predischarged bitlines is presented. By using the strained pMOS transistor technology, the degradation of the read static noise margin (SNM) at high supply voltages due to the aging, especially in the presence of symmetric stress, is suppressed. In contrast to conventional cell, the write margin of the proposed cell does not degrade considerably at low supply voltages. To assess the efficacy, the proposed cell is compared with conventional cell for two cases of unstrained and strained pMOS. A comparative study is performed using mixed mode device/circuit simulations for a gate length of 22 nm. The results show that the read SNM degradation due to the symmetric aging at the supply voltage of 1 V is about 6% after three years for the proposed strained structure, while degradations are 14%, 12%, and 11% for the unstrained proposed structure, unstrained, and strained conventional structures, respectively. In addition, the proposed cell has both read and write cell sigma yields higher than six for supply voltages ranging from 1 V down to 0.5 V while the other structures have read or write yields less than six at the minimum supply voltage. Through some work function tuning, the cell sigma yields of the other structures reach above six for both read and write while being still lower than those of the proposed structure. Copyright © 2015 John Wiley & Sons, Ltd.     

Statistical forecasting algorithm on circuit level gain transformation due to negative bias temperature instability for the microwave frequency spectrum

Negative Bias Temperature Instability (NBTI) is a critical reliability issue for CMOS technology, as this directly impacts the CMOS circuit performance parameters causing system failure. Moreover, NBTI behavior for radio frequency (RF) signals needs more understanding. On the device level, there has been much research on the relation between NBTI and RF. Many of those works contradict each other on the question of RF dependency with NBTI. Hence, the behavior of NBTI must be analyzed at the circuit level using a prediction technique. In this article, we analyzed the circuit level impact of NBTI for microwave frequency and developed a gain transformation technique for RF circuits in the microwave frequency range. To do this, we employed a 65 nm conventional ring oscillator as an RF block and carried out an aging simulation on it. A compatibility analysis was performed on low and high bandwidth microwave signals. The implemented statistical technique can determine the actual operable frequency range, so that the RF circuit can perform with minimal NBTI effect.     

Impact of self-heating effect on long-term reliability and performance degradation in CMOS circuits

As the technology feature size is reduced, the thermal management of high-performance very large scale integrations (VLSIs) becomes an important design issue. The self-heating effect and nonuniform power distribution in VLSIs lead to performance and long-term reliability degradation. In this paper, we analyze the self-heating effect in high-performance sub-0.18-/spl mu/m bulk and silicon-on-insulator (SOI) CMOS circuits using fast transient quasi-dc thermal simulations. The impact of the self-heating effect and technology scaling on the metallization lifetime and the gate oxide time-to-breakdown (TBD) reduction are also investigated. Based on simulation results, an optimized clock-driver design is proposed. The proposed layout reduces the hot-spot temperature by 15/spl deg/C and by 7/spl deg/C in 0.09-/spl mu/m SOI and bulk CMOS technologies, respectively.     

Reliability of VLSI-level chip assembly for evaluating the development of back-end technologies using a test chip with a top two-level metal structure

This paper investigates the effects of area and location of a chip, the material from which it is encapsulated, the geometry of the test structures, accelerated stressing operations and process technologies on the reliability of a VLSI-level chip assembly by using a 12 mm /spl times/ 12 mm large-die-size test chip with various top two-level metal test structures. The test chip is fabricated in a generic 0.18-/spl mu/m six-level AlCu-HSQ interconnect process and using specific dual-damascene Cu-FSG technology for top two-level metal. The proposed model is applied to analyze the failure distribution and identify the failure mechanism. The experimental results indicate that the mechanical and electrical performance of the assembled test chip, both of which depend strongly on back-end processes, can significantly impact the failure distribution and the failure mechanism in testing of the reliability of the chip assembly.     

A Finite-Oxide Thickness-Based Analytical Model for Negative Bias Temperature Instability

Negative bias temperature instability (NBTI) in PMOS transistors has become a serious reliability concern in present-day digital circuit design. With continued technology scaling, and reducing oxide thickness, it has become imperative to accurately determine its effects on temporal circuit degradation, and thereby ensure reliable operation for a finite period of time. A reaction–diffusion (R–D)-based framework is developed for determining the number of interface traps as a function of time, for both the dc (static NBTI) and the ac (dynamic NBTI) stress cases. The effects of finite oxide thickness, and the influence of trap generation and annealing in polysilicon, are incorporated. The model provides a good fit with experimental data and also provides a satisfying explanation for most of the physical effects associated with the dynamics of NBTI. A generalized framework for estimating the impact of NBTI-induced temporal degradation in present-day digital circuits, is also discussed.      

Circuits simulation of switch devices furnished with gain cell combined to FeRAM

Abstract

This paper has described a new concept on programmable switch device furnished with gain cell combined to FeRAM. Compared with memories but ferroelectric memories under many aspects, they have even been favorably labeled the ideal memory because of their non-volatility, ease of programming and operation by low voltage. As the programming switch, which is very attractive for logic application, SRAM, anti-fuse, flash type devices are well known. They have been required that satisfy non-volatility and low-voltage programming simultaneously. Some structures with ferroelectric material have been proposed and studied as solution of these problems. However, it seemed hard that these type devices are realized now from a viewpoint of fabrication process and low voltage operation. Therefore, we propose a new switch device furnished with gain cell combined to FeRAM. We have studied and simulated this switch device by SPICE. This basic circuit is composed of two blocks. One is switching block that includes gain cell, and the other is memory block that is FeRAM. Circuits, which we designed, amplify bit line's voltage up to Vdd or ground at sense amplification according to FeRAM data. The bit line voltage determines the logic state for gate electrode of switch transistor. The way to read is destructive read out. However, we can transfer information of bit line voltage during plate line is low-level voltage. The way to write FeRAM is similar to conventional way. It is revealed that the basic circuit with FeRAM connected gain cell could work correctly in simulation. In addition, this kind of device is hopeful of many logic applications.     

Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology

Negative bias temperature instability (NBTI) and channel hot carrier (CHC) are the leading reliability concerns for nanoscale transistors. The de facto modeling method to analyze CHC is based on substrate current I_sub, which becomes increasingly problematic with technology scaling as various leakage components dominate I_sub. In this paper, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions for both NBTI and CHC effects. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65-nm technology. By benchmarking the prediction of circuit performance degradation with the measured ring oscillator data and simulations of an amplifier, we demonstrate that the proposed method very well predicts the degradation. For 65-nm technology, NBTI is the dominant reliability concern, and the impact of CHC on circuit performance is relatively small.     

Low‐leakage sub‐threshold 9 T‐SRAM cell in 14‐nm FinFET technology

A novel sub‐threshold 9 T Static Random Access Memory (SRAM) cell designed and simulated in 14‐nm FinFET technology is proposed in this paper. The proposed 9 T‐SRAM cell offers an improved access time in comparison to the 8 T‐SRAM cell. Furthermore, an assist circuit is proposed by which the leakage current of the proposed SRAM cell is reduced by 20% when holding ‘0’ and an equal leakage current during hold ‘1’ in comparison to the 8 T‐SRAM cell. The proposed circuit improves the access time by 40% in comparison to the 8 T‐SRAM cell without any degradation in write and read noise margins, as well. The maximum operating frequency of the proposed SRAM cell is 1.53 MHz at V_DD = 270 mV. Copyright © 2016 John Wiley & Sons, Ltd.     

Thin-Gate-Oxide Breakdown and CPU Failure-Rate Estimation

Gate-oxide breakdown is a key mechanism limiting IC lifetime. Lifetime is typically extrapolated from accelerated tests on test capacitors, but estimating product reliability from such results requires making a number of often-untested assumptions. This paper details a capacitor-based model and compares the predictions of the model to results from accelerated lifetest of actual logic CPU products, discussing the assumptions which make such a comparison necessary. For the technology studied, lifetest failure rate was somewhat lower than model prediction, and failure analysis indicated that important factors included the different sensitivities of logic circuits versus cache cells and of and transistors in the cache. Analysis of the factors involved in determining oxide-breakdown reliability and of the statistical uncertainties in capacitor-based models indicates that it is important to calibrate models to product data, including these effects. Once a model is validated, this paper discusses how it can be used to assess the reliability impact of changes in silicon processing and product use conditions.     

Mechanism of Increase in SRAM Vmin Due to Negative-Bias Temperature Instability

Negative-bias temperature instability (NBTI) has been identified as a problem for static random-access-memory (SRAM) reliability since variations in the PMOS threshold voltages have been shown to correlate with rising V_min over time. The effect is greater than what would be expected from the relatively low sensitivity of the static-noise margin to PMOS device parameters reported in the literature. This paper investigates the mechanism of V_min increases due to NBTI. It is shown that the sensitivity to PMOS threshold voltages increases at low voltages, and furthermore, this sensitivity can be exacerbated by process variations in other SRAM devices. For the design of an array with many cells, the most probable combination of parameter variations to set a given V_min is identified and shown to change to a more probable combination with NBTI. Statistical designs must therefore consider NBTI as an additional source of variation, with increasing significance at low voltages.     

Special reliability features for Hf-based high-/spl kappa/ gate dielectrics

Several special reliability features for Hf-based high-/spl kappa/ gate dielectrics are highlighted, including: 1) trapping-induced threshold voltage (V/sub th/) shift is much more of a concern than TDDB in determining the operating lifetime; 2) n-channel MOSFETs (nMOSFETs) are more vulnerable than p-channel MOSFETs (pMOSFETs); and 3) MOSFETs with polySi gates are more vulnerable than those with metal gates. These will be discussed in the context of existing electron/hole traps and trap generation by high-field stress. A novel technique to probe traps in ultrathin gate dielectrics, inelastic electron tunneling spectroscopy (IETS), will be shown to be capable of revealing the energies and locations of traps in high-/spl kappa/ gate dielectrics.     

Reliability of InGaAs waveguide photodiodes for 40-Gb/s optical receivers

The reliability of 1.55-/spl mu/m wavelength InGaAs waveguide photodiodes (WGPDs) fabricated by metal-organic chemical vapor deposition is investigated for 40-Gb/s optical receiver applications. Reliability for both high-temperature storage and accelerated life tests obtained by monitoring both the dark current and the breakdown voltage is examined. The median device lifetime and the activation energy of the degradation mechanism are extracted for WGPD test structures. The device lifetimes are examined via statistical analysis which is highly reliable in predicting the device lifetime under practical conditions. The degradation mechanism for the WGPD test structures can be explained by the formation of leakage current path by ionic impurities in the passivation layer on the exposed p-n junction. Nevertheless, it can be concluded that the WGPD test structures exhibit sufficient reliability for practical 40-Gb/s optical receiver applications.