A 1.8-GHz Spur-Cancelled Fractional-N Frequency Synthesizer With LMS-Based DAC Gain Calibration

A 1.8-GHz wideband DeltaSigma fractional-N frequency synthesizer achieves the phase noise performance of an integer-N synthesizer using a spur-cancellation digital-to-analog converter (DAC). The DAC gain is adaptively calibrated with a least-mean-square (LMS) sign-sign correlation algorithm for better than 1% DAC and charge pump (CP) gain matching. The proposed synthesizer phase-locked loop (PLL) is demonstrated with a wide 400-kHz loop bandwidth while using a low 14.3-MHz reference clock, and offers a better phase noise and bandwidth tradeoff. Using an 8-bit gain-calibrated DAC, DeltaSigma-shaped divider ratio noise is suppressed by as much as 30 dB. The second-order DeltaSigma fractional-N PLL exhibits in-band and integrated phase noises of -98 dBc/Hz and 0.8deg. The chip, fabricated in 0.18-mum CMOS, occupies 2 mm², and consumes 29 mW at 1.8-V supply. The spur cancellation and correlation function consumes 30% additional power     

一种应用于GNSS接收机常数环路带宽的小数频率合成器

提出了一种应用于手持式民用GNSS接收机常数环路带宽的小数频率合成器,并在0.13μm 1P6M 的CMOS工艺中实现。通过离散的工作区域,LC-VCO用简单的结构获得宽的调节范围和小的压控灵敏度。提出的杂散抑制技术来最小化由于鉴频鉴相器和电荷泵引入的相位偏移。当PLL输出频率改变或温度变化时,通过自动环路校正模块自适应调整电荷泵电流保持优化的环路带宽不变。测试结果显示,该频率合成器带内相位噪声小于-93dBc（10 kHz 频率偏移处）,杂散小于-70 dBc, 环路带宽变化小于?3%;在1V的电源供电下,整个合成器（不包括本振测试buffer）消耗4.5mA电流,面积为0.5mm2。     

A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35-$mu$m CMOS

A wideband frequency synthesizer architecture is presented. The proposed topology employs a direct digital frequency synthesizer (DDFS) to control the output frequency of an offset-PLL. In this way, the synthesizer features a very fine frequency resolution, 24 Hz, as in delta-sigma fractional-N PLLs, but without being affected by the quantization-induced phase noise. This, in turn, allows enlarging the loop bandwidth. The frequency synthesizer is designed to be employed as a direct modulator for Bluetooth transmitter in a low-cost 0.35-mum CMOS technology. At 2.5GHz it achieves 1.8-MHz bandwidth, while the settling time within 30ppm for an 80-MHz step is 3 mus. The integrated phase noise gives less than 1 degree of rms phase error and the worst-case spur is 48dBc at 1 MHz, well below the specifications. Power dissipation is 120 mW for the PLL core, 50 mW for the DDFS plus DACs, and 19 mW for the GFSK modulator.     

A CMOS monolithic ΔΣ-controlled fractional-N frequencysynthesizer for DCS-1800

A monolithic 1.8-GHz ΔΣ-controlled fractional-N phase-locked loop (PLL) frequency synthesizer is implemented in a standard 0.25-μm CMOS technology. The monolithic fourth-order type-II PLL integrates the digital synthesizer part together with a fully integrated LC VCO, a high-speed prescaler, and a 35-kHz dual-path loop filter on a die of only 2×2 mm². To investigate the influence of the ΔΣ modulator on the synthesizer's spectral purity, a fast nonlinear analysis method is developed and experimentally verified. Nonlinear mixing in the phase-frequency detector (PFD) is identified as the main source of spectral pollution in ΔΣ fractional-N synthesizers. The design of the zero-dead zone PFD and the dual charge pump is optimized toward linearity and spurious suppression. The frequency synthesizer consumes 35 mA from a single 2-V power supply. The measured phase noise is as low as -120 dBc/Hz at 600 kHz and -139 dBc/Hz at 3 MHz. The measured fractional spur level is less than -100 dBc, even for fractional frequencies close to integer multiples of the reference frequency, thereby satisfying the DCS-1800 spectral purity constraints     

一个自调谐,自适应的1.9GHz分数/整数频率综合器

本文提出了一个具有自调谐,自适应功能的1.9GHz的分数/整数锁相环频率综合器.该频率综合器采用模拟调谐和数字调谐相结合的技术来提高相位噪声性能.自适应环路被用来实现带宽自动调整,可以缩短环路的建立时间.通过打开或者关断 ΣΔ 调制器的输出来实现分数和整数分频两种工作模式,仅用一个可编程计数器实现吞脉冲分频器的功能.采用偏置滤波技术以及差分电感,在片压控振荡器具有很低的相位噪声;通过采用开关电容阵列,该压控振荡器可以工作在1.7GHz~2.1GHz的调谐范围.该频率综合器采用0.18 μ m,1.8V SMIC CMOS工艺实现.SpectreVerilog仿真表明:该频率综合器的环路带宽约为100kHz,在600kHz处的相位噪声优于-123dBc/Hz,具有小于15 μ s的锁定时间.     

Behavioral modeling and simulation of fractional-N frequency synthesizer

A set of behavioral voltage-domain verilogA/verilog models is proposed in the paper, based on mathematical models of building blocks and some simulation strategies. The models include nonlinear effects of building blocks and can accurately predict the dynamic or stable characteristic of the closed loop. A three-order ΣΔ fractional-N PLL based frequency synthesizer with a 1.9 GHz central output frequency is implemented with the presented way. Cadence SpectreVerilog simulation results show that the behavioral modeling can provide a great speed-up over the transistor-level simulation. Correspondingly, the phase noise, spurious tones and loop locked time can also be accurately predicted, so it is helpful to optimization design based on system-level.     

一种宽带低相噪频率合成器的设计方法研究

提出了一种宽带低相噪频率合成器的设计方法.采用了数字锁相技术,该锁相技术主要由锁相环（phase locked loop,PLL）芯片、有源环路滤波器、宽带压控振荡器和外置宽带分频器等构成,实现了10~20 GHz范围内任意频率输出,具有输出频率宽、相位噪声低、集成度高、功耗低和成本低等优点.最后对该PLL电路杂散抑制和相位噪声的指标进行了测试,测试结果表明该PLL输出10 GHz时相位噪声优于-109 dBc/Hz@1 kHz,该指标与直接式频率合成器实现的指标相当.     

A 0.13μm CMOS △∑ fractional-N frequency synthesizer for WLAN transceivers

A fractional-N frequency synthesizer fabricated in a 0.13 μm CMOS technology is presented for the application of IEEE 802.11 b/g wireless local area network (WLAN) transceivers.A monolithic LC voltage controlled oscillator (VCO) is implemented with an on-chip symmetric inductor.The fractional-N frequency divider consists of a pulse swallow frequency divider and a 3rd-order multistage noise shaping (MASH) △ ∑ modulator with noise-shaped dithering techniques.Measurement results show that in all channels,phase noise of the synthesizer achieves -93 dBc/Hz and -118 dBc/Hz in band and out of band respectively with a phase-frequency detector (PFD) frequency of 20 MHz and a loop bandwidth of 100 kHz.The integrated RMS phase error is no more than 0.8°.The proposed synthesizer consumes 8.4 mW from a 1.2 V supply and occupies an area of 0.86 mm2.     

A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation

A phase noise cancellation technique and a charge pump linearization technique, both of which are insensitive to component errors, are presented and demonstrated as enabling components in a wideband CMOS delta-sigma fractional-N phase-locked loop (PLL). The PLL has a loop bandwidth of 460 kHz and is capable of 1-Mb/s in- loop FSK modulation at center frequencies of 2402 + k MHz for k = 0, 1, 2, ..., 78. For each frequency, measured results indicate that the peak spot phase noise reduction achieved by the phase noise cancellation technique is 16 dB or better, and the minimum suppression of fractional spurious tones achieved by the charge pump linearization technique is 8 dB or better. With both techniques enabled, the PLL achieves a worst-case phase noise of -121 dBc/Hz at 3-MHz offsets, and a worst-case in-band noise floor of -96 dBc/Hz. The PLL circuitry consumes 34.4 mA from 1.8-2.2-V supplies. The IC is realized in a 0.18-/spl mu/m mixed-signal CMOS process, and has a die size of 2.72 mm /spl times/ 2.47 mm.     

A constant loop bandwidth fractional-N frequency synthesizer for GNSS receivers

正A constant loop bandwidth fractional-TV frequency synthesizer for portable civilian global navigation satellite system(GNSS) receivers implemented in a 130 nm 1P6M CMOS process is introduced.Via discrete working regions,the LC-VCO obtains a wide tuning range with a simple structure and small VCO gain.Spur suppression technology is proposed to minimize the phase offset introduced by PFD and charge pumps.The optimized bandwidth is maintained by an auto loop calibration module to adjust the charge pump current when the PLL output frequency changes or the temperature varies.Measurement results show that this synthesizer attains an in-band phase noise lower than -93 dBc at a 10 kHz offset and a spur less than -70 dBc;the bandwidth varies by±3%for all the GNSS signals.The whole synthesizer consumes 4.5 mA current from a 1 V supply,and its area(without the LO tested buffer) is 0.5 mm~2.     

A 1.41–1.72 GHz sigma-delta fractional-N frequency synthesizer with a PVT insensitive VCO and a new prescaler

A 1.41–1.72 GHz fractional-N phase-locked loop (PLL) frequency synthesizer with a PVT insensitive voltage-controlled oscillator (VCO) is presented. In this PLL, a VCO with process, voltage, and temperature (PVT) insensitive bias circuit, and a divided-by-7/8 prescaler with improved multi-phase frequency divider are adopted. A novel multi-stage noise shaping (MASH) sigma-delta modulator (SDM) is adopted here. A new combination of low-current-mismatch charge pump (CP) and a phase/frequency detector (PFD) is proposed in this paper. Using Hejian Technology CMOS 0.18 μm analog and digital mixed-mode process, a fractional-N PLL prototype circuit is designed, the VCO in the prototype circuit can operate at a central frequency of 1.55 GHz, and its phase noise is −121 dBc/Hz at 1.0 MHz, the variety of phase noise is depressed by about 1.4 dB with the help of PVT insensitive bias. Under a 1.8-V supply voltage, the phase noise of the PLL is −113 dBc/Hz at 1.0 MHz.     

S频段锁相频率合成器的设计

介绍了小数式锁相频率合成器的设计方法及相关理论,分析了影响锁相环相位噪声的主要因素并设计了环路滤波器和Wilkinson功率分配器。由实验结果可知,小数式锁相频率合成器具有很好的相位噪声和较高的频率分辨率。     

A voltage-controlled oscillator with an ultra-low supply voltage and its application to a fractional-N phase-locked loop

With feature size scaling, the supply voltage of digital circuits is becoming lower and lower. As a result, the supply voltage of analogue and RF circuits must also be reduced for system on chip (SoC) realisation. This article proposes an ultra-low-supply voltage-controlled oscillator (ULSVCO) and designs a sigma–delta fractional-N frequency synthesiser which adopts such ULSVCO. A mathematical phase-noise model is built here to describe the noise performance of the low-supply voltage-controlled oscillator (VCO). The substrate of the cross-coupled NMOSFETs in the proposed ULSVCO is not grounded but connected to the supply to further reduce the supply voltage. Implemented in 0.18 μm CMOS technology, the proposed ULSVCO can be operated at a supply voltage as low as 0.41 V, the central frequency is set to 1.55 GHz, the phase noise is ?116 dBc/Hz@1.0 MHz. The minimum supply voltage is decreased by about 11% after our idea is adopted and the power consumption of the ULSVCO is only 1.04 mW. With the proposed ULSVCO, we design a sigma–delta-modulator (SDM) fractional-N phase-locked loop frequency synthesiser, which has a 1.43–1.75 GHz frequency tuning range. When the loop bandwidth is set to 100 KHz, the phase noise of our PLL is ?110 dBc/Hz@1.0 MHz.     

S/U双波段小数分频锁相环型频率合成器设计

提出了一种覆盖S/U双波段的小数分频锁相环型频率合成器.该频率合成器采用一种新型多模分频器,与传统的小数分频频率合成器相比具有稳定速度快、工作频率高和频率分辨率高的优点.该锁相环采用了带有开关电容阵列(SCA)的LC-VCO实现了宽频范围,使用3阶MASH△-∑调制技术进行噪声整形,降低了带内噪声.设计基于TSMC 0.25 μm 2.5 V 1P5M CMOS工艺实现.测试结果表明,频率合成器频率范围达到2.450～3.250 GHz;波段内偏离中心频率10 kHz处的相位噪声低于-92.5 dBc/Hz,1 MHz处的相位噪声达到-120 dBc/Hz;最小频率分辨率为13 Hz;在2.5 V工作电压下,功耗为36 mW.     

A Quantization Noise Pushing Technique for $DeltaSigma$ Fractional- $N$ Frequency Synthesizers

This paper demonstrates our proposed quantization noise pushing technique, which moves the quantization noise to higher frequencies and utilizes the low-pass characteristic of the phased-lock loop (PLL) to further suppress the quantization noise. In addition, it can separate the operating frequency of the DeltaSigma modulator and the comparison frequency of the phase/frequency detector (PFD) so as to reduce the loop gain of the PLL and lower the in-band phase noise. This synthesizer was fabricated using the UMC 0.18-mum CMOS process. The chip area measures 0.85 mm². The supply voltage is 2 V, corresponding to a total power consumption of 26.8 mW. The experimental results show that, with this technique, the in-band phase noise can be lowered by 12 dB, while the out-of-band phase noise can be reduced by more than 15 dB, compared to a synthesizer with the same PFD comparison frequency.     

A high-precision spread spectrum clock generator based on a fractional-N phase locked loop

A low jitter Spread Spectrum Clock Generator (SSCG) based on a fractional-N Phase Locked Loop (PLL) capable of generating various Electromagnetic Interference (EMI) reduction levels is proposed. A digital compensation filter is fully integrated in the design to prevent various triangular modulation profiles from being distorted by the prohibitively small PLL loop bandwidth. A simple but comprehensive logic design included in the digital filter provides independently controllable modulation frequency, f _m, and modulation ratio, δ_m within all modulation modes (up, down, center). The proposed SSCG is designed in a 0.18 μm CMOS standard cell library and operates at 72 MHz with f _m ranging from 58 to 112.5 kHz and δ_m ranging from 0.75 to 2 %.     

Analysis and minimization of substrate spurs in fractional-N frequency synthesizers

This paper analyses substrate-related spurious tones in fractional-N phase-locked loops with integrated VCOs. Spur positions are calculated and experimentally verified as a function of the divider ratios of prescaler and programmable divider. For an integrated wideband PLL in SiGe BiCMOS technology the spur power levels are measured and compared with theoretical expectations. The power in these spurs is minimized by layout techniques shielding the reference input buffer. Spur minimization by using a variable reference frequency is experimentally demonstrated. Based on this observation, a programmable integer-N PLL for driving the fractional-N synthesizer is suggested to reduce the worst-case spur level significantly.     

使用三位三阶Δ∑调制器的集成1GHz小数频率合成器

本文实现了一个采用三位三阶Δ∑调制器的高频谱纯度集成小数频率合成器.该频率合成器采用了模拟调谐和数字调谐组合技术来提高相位噪声性能,优化的电源组合可以避免各个模块之间的相互干扰,并且提高鉴频鉴相器的线性度和提高振荡器的调谐范围.通过采用尾电流源滤波技术和减小振荡器的调谐系数,在片压控振荡器具有很低的相位噪声,而通过采用开关电容阵列,该压控振荡器达到了大约100MHz的调谐范围,该开关电容阵列由在片数字调谐系统进行控制.该频率合成器已经采用0.18μm CMOS工艺实现,仿真结果表明,该频率频率合成器的环路带宽约为14kHz,最大带内相位噪声约为-106dBc/Hz;在偏离载波频率100kHz处的相位噪声小于-120dBc/Hz,具有很高的频谱纯度.该频率合成器还具有很快的反应速度,其锁定时间约为160μs.     

A Novel Hybrid Phase-Locked-Loop Frequency Synthesizer Using Single-Electron Devices and CMOS Transistors

This paper proposes a novel phase-locked loop (PLL) frequency synthesizer using single-electron devices (SEDs) and metal-oxide-semiconductor (MOS) field-effect transistors. The PLL frequency synthesizer mainly consists of a single-electron transistor (SET)/MOS hybrid voltage-controlled oscillator circuit, a single-electron (SE) turnstile/MOS hybrid phase-frequency detector (PFD) circuit and a SE turnstile/MOS hybrid frequency divider. The phase-frequency detection and frequency-division functions are realized by manipulating the single electrons. We propose a SPICE model to describe the behavior of the MOSFET-based SE turnstile. The authors simulate the performance of the PLL block circuits and the whole PLL synthesizer. Simulation results indicated that the circuit can well perform the operation of the PLL frequency synthesizer at room temperature. The PLL synthesizer is very compact. The total number of the transistors is less than 50. The power dissipation of the proposed PLL circuit is less than 3 uW. The authors discuss the effect of fabrication tolerance, the effect of background charge and the SE transfer accuracy on the performance of the PLL circuit. A technique to compensate parameter dispersions of SEDs is proposed.     

Current-mode phase-locked loop with constant-Q active inductor CCO and active transformer loop filter

This paper presents a current-mode phase-locked loop (PLL) with a constant-Q CMOS active inductor current-controlled oscillator (CCO) and a CMOS current-mode active-transformer loop filter. The constant-Q active inductor provides a large and swing-independent quality factor such that the phase noise of the CCO utilizing the constant-Q active inductor is comparable to that of CCO with spiral inductors. The current-mode active-transformer loop filter offers the advantage of a large and tunable inductance and low silicon consumption such that the loop bandwidth of the PLL can be made small and tunable. The PLL was designed in TSMC-0.18 μm 6-metal 1.8V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM3v3 device models. The phase noise of the PLL was analyzed using Cadence’s Verilog-AMS behavioral modeling. The phase noise of the CCO with the constant-Q active inductor is ?123.1 dBc/Hz at 1 MHz frequency offset, over 10 dB better as compared with that of the CCO with conventional active inductors, and is only a few dB higher than that of the CCO with spiral inductors. The phase noise of the PLL with an active-transformer loop filter and a constant-Q CCO is ?116 dBc/Hz at 1 MHz frequency offset, nearly 20 dB lower than that of the PLL with the same active-transformer loop filter and a conventional active-inductor CCO. The lock time, power consumption, and phase noise of the PLL are 60 ns, 34 mW, and ?116 dBc/Hz at 1 MHz frequency offset, respectively. The total silicon consumption of the PLL excluding bond pads is 0.013 mm².