1／f噪声源及MOS器件中的1／f噪声

１／ｆ噪声，由于其反映了器件的质量、可靠性等参数，其研究越来越为人们所重视，本文首先较为系统地介绍了１／ｆ噪声源两种较为成熟的理论：载流子数涨落和迁移率涨落模型，最后将研究ＭＯＳ晶体管中１／ｆ噪声的现象。在ｎ管中，较为成功地用ΔＮ模型；而在ＰＭＯＳ晶体管中，Δμ模型可较为成功地解释其１／ｆ噪声特性。     

心电图机专用IC－CMOS低噪声前置放大器的设计

ＣＭＯＳ低噪声、低漂移、低失调运放是为＂心电图机专用集成电路＂而设计的，要求具有高输入阻抗、高ＣＭＲＲ、低漂移、低失调、尤其是低的１／ｆ噪声。ＣＭＯＳ器件与双极型器件和ＪＦＥＴ器件相比，通常有较大的１／ｆ噪声电压。由于采用特殊的设计技术，使我们研制的ＣＭＯＳ运放具有较低的１／ｆ噪声，且功耗较低。经研制及投片，实例得０．０５Ｈｚ～２５０Ｈｚ等效输入噪声电压峰峰值小于２．５μＶ，±２．５Ｖ到±１０Ｖ电源电压下输入失调小于１ｍＶ，共模抑制比１１０ｄＢ以上，完全达到设计指标。该运放可广泛用于生物医学电子学及其他需要低噪声运放的场合，在±２．５Ｖ工作时亦可作为微功耗运放使用。     

MOS结构低温负偏压温度不稳定性

本文报道了在氧等离子体中暴露过的热生长二氧化硅ＭＯＳ结构，置于－１７０至１００℃的环境中，经受－０．３至－１０ＭＶ／ｃｍ电场作用１ｍｓ至１００ｓ的时效处理后，仍然表现出不稳定性的实验结果．１至１０ｍｓ的时效时间是常规负偏压温度不稳定性试验时间的几百，乃至几十万分之一，用这样短的低温负偏压应力，研究了光照对ＭＯＳ结构负偏压温度不稳定性的影响，实验与预想一致，Ｎ型ＭＯＳ结构应力处理时，若无光照，时效时间短于１０ｍｓ，处理后Ｃ－Ｖ曲线不位移，若有光照，Ｃ－Ｖ曲线向左位移０．１５Ｖ左右．对于Ｐ型ＭＯＳ结构，Ｃ－Ｖ     

衬底正偏的MOSFET的近似模型

本文针对衬底正偏的ＭＯＳＦＥＴ的解析模型进行了讨论．在已有ＭＯＳＦＥＴ理论基础上，仅引入一个参数ξ，便得到了全偏压范围的ＭＯＳＦＥＴ的解析表达式的通式．当ξ＝１时，该表达式与已知的衬底负偏的ＭＯＳＦＥＴ的表达式相同；当ξ＝０．８时，可得到衬底正偏的ＭＯＳＦＥＴ的近似解析式．实验结果验证了该模型的正确性．     

采用扩频实现OQAM系统

ＯＱＡＭ系统数字化实现一般采用ＦＦＴ加多相网络，提出了一种相邻载频间隔２ｆ０的ＯＱＡＭ等效复系统，并采用样值为Ｗ＾ｋ２Ｎ＝ｅｘｐｊ２πｋ＾２／Ｎ的扩谱调制器（ＳＳＭ）数字实现，ＳＳＭ取代ＦＦＴ，使系统运算复杂性显下降，计算机模拟结果表明，采用ＳＳＭ实现ＯＱＡＭ，可提高系统抗干扰能力。     

双极型器件慢界面陷阱能量分布的1／f噪声分析方法

位于Ｓｉ／ＳｉＯ２界面附近的具有长时间常数的载流子陷阱对于半导体器件的可靠性有重要影响．根据笔者建立的双极晶体管表面１／ｆ噪声分析模型，通过测量栅控晶体管１／ｆ噪声的栅压特性，可获得这种慢界面陷阱密度在禁带中心附近的能量分布．本文给出了该方法的模型推导、参数提取、分析步骤和应用实例．     

耗尽态SIMOX MOS晶体管的低频噪声

耗尽态ＳＩＭＯＸＭＯＳ晶体管的低频噪声＝Ｌｏｗ－ｆｒｅｑｕｅｎｃｙｎｏｉｓｅｉｎｄｅｐｌｅｔｉｏｎ－ｍｏｄｅＳＩＭＯＸＭＯＳｔｒａｎｓｉｓｔｏｒｓ［刊．英］／Ｅｌｅｗａ，Ｔ．…∥ＩＥＥＥＴｒａｎｓ．ＥｌｅｃｔｒｏｎＤｅｖ．－１９９１．３８（２）．－３...     

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ROHM公司CD／CDROM用集成电路一览表（续）

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MOSFET1/f噪声相似性的子波鉴别方法

基于傅里叶分析的功率谱密度只能反映1/f噪声的整体频率特性,子波变换模极大值能够反映1/f噪声的奇异性和非规整性,而后者才是1/f噪声最本质的特征所在.本文将这一特性用于MOSFET 1/f噪声的相似性分析.从子波变换模极大值匹配原理出发,定义了一个1/f噪声的相似系数,利用它对不同形成机制、不同微观缺陷状态、不同偏置应力作用下的MOSFET 1/f噪声进行了相似性分析,发现它可作为鉴别1/f噪声的物理起源,分析1/f噪声的微观动力学机制,筛选有潜在缺陷或损伤的MOS器件的有效手段.     

1/f noise and radiation effects in MOS devices

An extensive comparison of the 1/f noise and radiation response of MOS devices is presented. Variations in the room-temperature 1/f noise of unirradiated transistors in the linear regime of device operation correlate strongly with variations in postirradiation threshold-voltage shifts due to oxide trap charge. A simple number fluctuation model has been developed to semi-quantitatively account for this correlation. The 1/f noise of irradiated n-channel MOS transistors increases during irradiation with increasing oxide-trap charge and decreases during postirradiation positive-bias annealing with decreasing oxide-trap charge. No such correlation is found between low-frequency 1/f noise and interface-trap charge. The noise of irradiated p-channel MOS transistors also increases during irradiation, but in contrast to the n-channel response, the p-channel transistor noise magnitude increases during positive-bias annealing with decreasing oxide-trap charge. A qualitative model involving the electrostatic charging and discharging of border traps, as well as accompanying changes in trap energy, is developed to account for this difference in n- and p-channel postirradiation annealing response. The correlation between the low-frequency 1/f noise of unirradiated devices and their postirradiation oxide-trap charge suggests noise measurements can be used as a nondestructive screen of oxide trap charge related failures in discrete MOS devices and for small scale circuits in which critical transistors can be isolated. It also suggests that process techniques developed to reduce radiation-induced-hole trapping in MOS devices can be applied to reduce the low-frequency 1/f noise of MOS circuits and devices. In particular, reducing the number of oxygen vacancies and vacancy complexes in the SiO ₂ can significantly reduce the 1/f noise of MOS devices both in and outside a radiation environment     

The effect of LAC doping on deep submicrometer transistor capacitances and its influence on device RF performance

In this paper, we have systematically investigated the effect of lateral asymmetric doping on the MOS transistor capacitances and compared their values with conventional (CON) MOSFETs. Our results show that, in lateral asymmetric channel (LAC) MOSFETs, there is nearly a 10% total gate capacitance reduction in the saturation region at the 100-nm technology node. We also show that this reduction in the gate capacitance contributes toward improvement in f/sub T/, f/sub max/, and RF current gain, along with an improved transconductance in these devices. Our results also show that reduced short-channel effects in LAC devices improve the RF power gain. Finally, we report that the lateral asymmetric channel doping gives rise to a lower drain voltage noise spectral density compared to CON devices, due to the more uniform electric field and electron velocity distributions in the channel.     

Low-frequency noise measurements on submicrometre n-channel and p-channel MOSFETs at various operating regions

Silicon founders give in their MOS transistor card models some low-frequency noise parameters for SPICE-based circuit simulators corresponding to pure 1/f ^a or flicker noise, with a very close to unity. MOS transistors used in analogue circuit applications are usually devices with large channel length and width. In low-noise applications, methods such as correlated double sampling are used to suppress the low frequency noise generated by them. Nevertheless, the transistors presently are submicrometre devices exhibiting very different low-frequency noise behaviour. In this paper, experimental low-frequency noise results obtained at room temperature on NMOS and PMOS transistors fabricated using a 0.7 μm process are presented. Both large and small devices on the same process are considered. All regions of operation of transistors are considered. We show that the low-frequency noise behaviour of small area MOSFETs is very different from that of large area devices and that the spectrum is the summation of Lorentzian spectra generated by the switching of individual active traps.     

Impact of the interfacial layer on the low-frequency noise (1/f) behavior of MOSFETs with advanced gate stacks

The impact of the interfacial layer thickness on the low-frequency (LF) noise (1/f noise) behavior of n- and p-channel MOSFETs with high-/spl kappa/ gate dielectrics and metal gates is investigated. Decreasing the interfacial layer thickness from 0.8 to 0.4 nm affects the 1/f noise in two ways. 1) The mobility fluctuations mechanism becomes the main source of 1/f noise not only on pMOS devices, as usually observed, but also on nMOS devices. 2) A significant increase of the Hooge's parameter is observed for both types of MOSFETs. These experimental findings indicate that bringing the high-/spl kappa/ layer closer to the Si-SiO/sub 2/ interface enhances the 1/f noise mainly due to mobility fluctuations.     

The impact of device type and sizing on phase noise mechanisms

Phase noise mechanisms in integrated LC voltage-controlled oscillators (VCOs) using MOS transistors are investigated. The degradation in phase noise due to low-frequency bias noise is shown to be a function of AM-PM conversion in the MOS switching transistors. By exploiting this dependence, bias noise contributions to phase noise are minimized through MOS device sizing rather than through filtering. NMOS and PMOS VCO designs are compared in terms of thermal noise. Short-channel MOS considerations explain why 0.18-/spl mu/m PMOS devices can attain better phase noise than 0.18-/spl mu/m NMOS devices in the 1/f/sup 2/ region. Phase noise in the 1/f/sup 3/ region is primarily dependent upon the upconversion of flicker noise from the MOS switching transistors rather than from the bias circuit, and can be improved by decreasing MOS switching device size. Measured results on an experimental set of VCOs confirm the dependencies predicted by analysis. A 5.3-GHz all-PMOS VCO topology demonstrates measured phase noise of -124 dBc/Hz at 1-MHz offset and -100dBc/Hz at 100-kHz offset while dissipating 13.5 mW from a 1.8-V supply using a 0.18-/spl mu/m SiGe BiCMOS process.     

Hot carrier degradation mechanisms in sub-micron p channel MOSFETs: Impact on low frequency (1/f) noise behaviour

In this work we present new results which illustrate the impact of hot carrier (HC) degradation on the low frequency (1/f) noise behaviour of submicron p channel MOSFETs. Submicron p channel MOSFETs were subjected to HC stress at a range of gate bias conditions, and the response of the low frequency noise was recorded. The results obtained are in marked contrast to the reported influence of HC stress on nMOSFETs 1/f noise, and indicate that the measurement of 1/f noise is a useful tool for investigating HC induced aging effects in submicron p channel devices. The significance of these results to the use of pMOSFETs in analog applications is briefly discussed.     

Modeling of the 1/f noise overshoot in short-channel MOSFETs locally degraded by hot-carrier injection

On the basis of previous results concerning the 1/f noise in electrically stressed MOS transistors and the characterization of aged MOSFETs, the authors present a theoretical model for the flicker noise in nonhomogeneous short-channel MOS transistors operated in the ohmic region. When applied to hot-carrier-induced degradation, a simple two-region approximation of this model is shown to account for the existence of a noise peak (overshoot) near the threshold voltage, similar to the transconductance overshoot already observed. A two-dimensional simulation makes it possible to detail the influence of the gate bias, the distance over which the interface states (or traps) are generated, and their density. The 1/f noise overshoot appears to be more sensitive to aging conditions than transconductance overshoot.<>     

Noise in DMOS transistors in a BICMOS-technology

An experimental and theoretical study of the 1/f noise and the thermal noise in double-diffused MOS (DMOS) transistors in a BICMOS-technology has been carried out. By using an analytical model that consists of an enhancement MOS transistor in series with a depletion MOS transistor and a resistance, and by attributing noise sources to each device, the noise in DMOS devices is simulated accurately. Three distinct regions of operation are defined: enhancement transistor control, depletion transistor control and the linear region. In the first region, the noise is strictly determined by the enhancement transistor. It was found that the 1/f noise in this region is caused by mobility fluctuations and is very low. In the depletion transistor control region both transistors influence the total noise. Here the 1/f noise is dominated by the depletion transistor. The series resistance is only of importance in the linear region     

MOSFET 1/f noise model based on mobility fluctuation in linearregion

A new 1/f noise model for MOSFETs in the linear region, based on the Hooge mobility fluctuation noise expression, is presented. Simulation results for the new model are in good agreement with experimental results; thus, the new model can be used to predict and estimate the 1/f noise performance for p-MOSFET devices