Future directions in microprocessor technology

The application trends and key design tradeoffs involved in the design of high performance microprocessors are discussed. In particular the growing importance of improved human interface technology and the need for high-performance, highly-connected systems combined with the need to continue to drive costs lower make design choices very difficult. Technical innovation in the areas of high bandwidth processor-memory interfaces, low-cost multiprocessors and software compatibility are needed in order to continue move forward     

The impact of semiconductor technology scaling on CMOS RF and digital circuits for wireless application

The impact of CMOS technology scaling on the various radio frequency (RF) circuit components such as active, passive and digital circuits is presented. Firstly, the impact of technology scaling on the noise and linearity of the low-noise amplifier (LNA) is thoroughly analyzed. Then two new circuits, i.e., CMOS complementary parallel push-pull (CCPP) circuit and vertical-NPN (V-NPN) circuit for direct-conversion receiver (DCR), are introduced. In CCPP, the high RF performance of pMOS comparable to nMOS provides single ended differential RF signal processing capability without the use of a bulky balun. The use of parasitic V-NPN bipolar transistor, available in triple well CMOS technology, has shown to provide more than an order of magnitude improvement in 1/f noise and dc offset related problems, which have been the bottleneck for CMOS single chip integration. Then CMOS technology scaling for various passive device performances such as the inductor, varactor, MIM capacitor, and switched capacitor, is discussed. Both the forward scaling of the active devices and the inverse scaling of interconnection layer, i.e., more interconnection layers with effectively thicker total dielectric and metal layers, provide very favorable scenario for all passive devices. Finally, the impact of CMOS scaling on the various digital circuits is introduced, taking the digital modem blocks, the various digital calibration circuits, the switching RF power amplifier, and eventually the software defined radio, as examples.     

Assimilating information technology innovations: strategies andmoderating influences

This paper examines the process of new technology assimilation with an objective of understanding what specific organizational strategies facilitate the assimilation process. A four-cell conceptual framework is synthesized from prior research, which differentiates between two units of analysis responsible for assimilation-an individual or the organization. Depending on the specific location of an organization and a technology within this framework, as well as the desired location, a few “generic” assimilation strategies are described that allow an organization to move from one cell of the framework to another by influencing individual adoption behaviors. Recognizing that the outcomes of assimilation strategies are influenced by key moderating influences-such as the differences in the technology that is being assimilated, the characteristics of target adopters, and their perceptions toward that technology-prior research is again reviewed to study the impact of these moderating variables. The assimilation strategies, together with the effects of moderating variables, constitute a model of innovation assimilation. Adopting a process orientation, the model is used to perform a retrospective analysis of the efforts of nine major corporations as they attempted to assimilate new information technologies into their operations. The analyses yield a contingency framework for the choice of assimilation strategy that can be used as a guide for management action     

Modeling technology impact on cluster microprocessor performance

The growing speed gap between transistors and wire interconnects is forcing the development of distributed, or clustered, architectures. These designs partition the chip into small regions with fast intracluster communication. Longer latency is required to communicate between clusters. The hardware and/or software are responsible for scheduling instructions to clusters such that critical path communication occurs within a cluster. This paper presents GENEric SYstems Simulator (GENESYS), a technology modeling tool that captures a broad range of materials, device, circuit, and interconnect parameters across current and future semiconductor technology. This tool is used to explore the relationship between key technology parameters (intercluster wire delay and transistor switching delay) and key architecture parameters (superscalar versus multithreaded instruction dispatch, and value prediction support). GENESYS is used to predict intercluster latencies as VLSI technology advances. The study provides quantitative data showing how conventional superscalar performance is degraded with increasing wire latency. Threaded designs are more tolerant to wire delay. Optimal thread size changes with advancing VLSI technology, suggesting a highly adaptive architecture. Value prediction is shown to be useful in all cases, but provides more benefit to the multithreaded design.     

An advanced area scaling approach for semiconductor burn-in

In semiconductor manufacturing, early life failures are avoided by putting the produced items under accelerated stress conditions before delivery. The products’ early life failure probability p is assessed by means of a burn-in study, in which a sample of the stressed items is investigated for early failures. The aim is to prove a target failure probability of the produced devices and release stress testing of the whole population. Given the failure probability level on a reference product, the failure probabilities of so-called follower products with different chip sizes are then obtained by means of area scaling. Classically, area scaling is done with respect to the whole area of the chips. Nevertheless, semiconductors can be partitioned into different chip subsets, which can have different likelihoods of failures. In this paper, we propose a novel area scaling model for the chip failure probability p, which enables us to scale the chip subsets separately from each other. The main idea is to adapt the classical estimators of the failure probabilities of the chip partitions according to the number of failures on the different chip subsets. This leads to a more appropriate estimation of the failure probabilities of the follower products and helps to improve the efficiency of burn-in testing.     

Impedance boosting techniques based on BiCMOS technology

An impedance enhancement technique, based on a combination of bipolar and MOS devices, is presented. The technique uses negative active feedback action to boost the impedance level of a cascode circuit. This technique improves the gain of the conventional folded-cascode BiCMOS amplifier by the loop gain of the feedback loop. The BiCMOS-based impedance boosting circuit, compared to the CMOS version, offers the advantage of higher bandwidth together with higher output current capability. The SPICE simulations of a folded-cascode op amp based on this technique show that a 120 dB DC gain can be achieved. Application of the technique to a transducer resulted in a total harmonic distortion as low as 0.02% with 2 V_p-p input signals and an improvement of more than 10 dB in linearity, with respect to the case where no feedback was used     

A new scaling length for modeling semiconductor space-charge regions

Intrinsic and extrinsic Debye lengths have been extensively used in device modeling work. Recently Jindal and Warner [4], using extrinsic Debye length, have developed a unified solution applicable to all step junctions. They have further extended it to include the semiconductor surface problem [5]. As a result of these general analyses, the role of extrinsic Debye length in distance normalization in cases where mobile charges are dominant has been more clearly understood. A new scaling length, whose use is complementary to that of extrinsic Debye length is proposed for cases where fixed charge is dominant.     

Ethernet as a carrier grade technology: developments and innovations

Recent innovations in Ethernet networking technology are enhancing both the scalability and capability of Ethernet as a carrier-grade transport technology. This article explains four main innovations recently added to Ethernet, improvements related to scalability, OAM functionality, and enhanced forwarding capability in order to permit Ethernet to assume a much larger role in carrier networks with substantial economic and operational benefits.     

New semiconductor contact technology

Metals have been deposited on semiconductors from standard plating solutions, in defined areas which have been lightly damaged by ion bombardment. The contacts are either ohmic or rectifying, depending on bombardment dose and plating conditions. The process has been used to make gallium-arsenide f.e.t.s.     

An eight-channel 8 bit microprocessor compatible NMOS D/A converter with programmable scaling

A single-chip multiple-channel D/A converter is described. The NMOS chip contains a combination of digital and analog functions. Eight output channels with 8 bit accuracy are provided and each channel has programmable end points. The values for the data and the end points are stored in an internal RAM. Sample and-hold functions are completely on-chip. Only one multiplexed opamp is required for the analog functions. The entire control logic is incorporated in an easily testable PLA. The active chip area is 8 mm/SUP 2/. There are three power supplies (15,5,-5) with a total power dissipation of 120 mW. Updating of the eight channels occurs at a 16 kHz rate (5 MHz clock). The circuit aims at applications in microprocessor driven control systems in the industrial and consumer products field.     

突破现有CMOS工艺限制的晶体管技术

很多人都有过这样尴尬的经历,当有急事需要打电话时,却发现手机没电了,而身边又没有固定电话,如果Cornell大学的研究人员成功了,今后,你将不会再碰到这种尴尬事。Cornell大学的一个研究小组将放射材料与MEMS（微型机电系统）悬臂和电路结合在一起,将核能转变为电能,这种能量源的半衰期大约为100年,基于这种技术的新电池可谓是能“永久”供电的电池。近日,     

Information technology innovations: general diffusion patterns andits relationships to innovation characteristics

While many scholars of organizational innovations have examined characteristics of innovations such as relative advantage and complexity and how they facilitate the adoption of an innovation by organizations, others have used mathematical models to fit diffusion patterns. In this study, the authors attempt to integrate these two areas of inquiry and explore the possibilities to predict diffusion patterns based on characteristics of the innovation and the adopting entities. Based on a cross-sectional sample of 313 large American firms, 20 information technology (IT) innovations were examined and their diffusion patterns assessed with respect to models that espoused internal and external influence. The mixed influence model (Bass model) was chosen as a robust common representation for the set of diffusion patterns. However, the external influence as represented by the coefficient of innovation was found to be extremely small and the internal influence dominates for all innovations. The other two parameters of the model, the saturation level and the coefficient of imitation, which represents internal influence, were then used to perform a cluster analysis. Five clusters of technologies emerged, and the potential relationships between their innovation characteristics and diffusion patterns were explored. Rigorous examination of these potential relationships by future researchers may result in practical methods for predicting patterns of IT innovation diffusion based on innovation and technology characteristics     

Evolution of MOS-bipolar power semiconductor technology

A review of the innovations that have led to the evolution of a power transistor technology based on MOS gate control is provided. This technology offers the advantage of very high input impedance, which allows the control of the devices using low-cost integrated circuits. The physics of operation of the two types of devices in this category, power MOSFETs and power MOS-bipolar devices, are described. Trends in process technology and device ratings are analyzed. Based on the superior performance of these devices, it is projected that they will completely displace the power bipolar transistor in the future     

无线产品半导体工艺的选择

众多的无线标准以及它们在单芯片上相互组合的可能性为实现下一代产品的生产工艺提出了很多问题。数字CMOS、RFCMOS和SiGe BiCMOS之间在工艺、成本和性能三方面存在一定的权衡,但是人们的争论更倾向于采用数字CMOS工艺作为无线产品设计的可行性方案,因为生产规模是不完善的,需要针对功能上的扩展做进一步的分析,而功能上的扩展可能在技术标准上与基于CMOS的特殊工艺存在对立。     

Strange bedfellows [semiconductor technology]

Silicon is the stuff of memories and microprocessors. III-V semiconductors-compounds made of elements inhabiting the third and fifth columns of the periodic table, like gallium arsenide-are the stuff of high-frequency communications chips, LEDs, and solid-state lasers. But these two types of materials have never been able to live together on the same chip. Now, researchers in Europe have found that at the nanometer scale, they can get along just fine. The researchers grew indium phosphide and gallium phosphide nanowires on a silicon substrate, clearing the path for the manufacture of cheaper high frequency chips and silicon devices embedding LEDs and lasers.     

电力半导体模块及其工艺技术

回顾了电力半导体模块发展里程 ,指出了电力半导体模块今后发展的方向 ,描述了我国研制成功并已生产的智能晶闸管模块的特点及其应用领域。介绍了 IGBT模块的结构和工艺技术 ,提出了设计 IGBT模块各部件时应注意的问题和工艺技术特点。     

Development of magnetic semiconductor microsystems technology

The results of the development of technologies of magnetic semiconductor chips based on thinfilm magnetoresistive multilayer structures are presented. A brief overview of the main achievements in the field of magnetometric devices based on anisotropic and giant magnetoresistive effects is made.     

Research coordination for power semiconductor technology

The National Power Semiconductor Interagency/Utility Consortium has been formed to coordinate US research activities for development of materials and technologies related to high-power semiconductors. The history, activities, and investment strategy of this consortium are described briefly. The most promising power electronics devices considered by the consortium are discussed, leading to the conclusion that field-effect transistors and metal-oxide semiconductor (MOS) controlled thyristors (MCTs) will eventually dominate power-switching applications. New packaging techniques are also presented, in which silicon is used to replace bulky ceramic insulators and copper contacts, an arrangement that promises to lower costs and weight while improving device performance and life. Finally, the authors review policy issues related to power semiconductor research and recommend that R&D in this field be treated as a leading national priority