Rotary traveling-wave oscillator design using 0.18 μm CMOS

A rotary traveling-wave oscillator (RTWO) targeted at 5.8 GHz band operation is designed and fabricated using standard 0.18 μm CMOS technology. Both simulation and measurement results are presented. The chip size including pads is 1.5 × 1.5 mm2. The measured output power at a frequency of 5.285 GHz is 6.68 dBm, with a phase noise of-102 dBc/Hz at 1 MHz offset from the carrier.     

Measurement and modeling of on-chip transmission line effects in a400 MHz microprocessor

On-chip interconnect delays are becoming an increasingly important factor for high-performance microprocessors. Consequently, critical on-chip wiring must be carefully optimized to reduce and control interconnect delays, and accurate interconnect modeling has become more important. This paper shows the importance of including transmission line effects in interconnect modeling of the on-chip clock distribution of a 400 MHz CMOS microprocessor. Measurements of clock waveforms on the microprocessor showing 30 ps skew were made using an electron beam prober. Waveforms from a test chip are also shown to demonstrate the importance of transmission line effects     

Giga-hertz rate single slope conversion technique with 512-phase RTWO

In this paper, an 8-bit 1.2 Gsample/s single-slope ADC architecture is presented. The proposed technique utilizes the picosecond-accurate phases of a rotary traveling wave oscillator (RTWO). The proof-of-concept test chip is fabricated in a 0.18-μm CMOS process and occupies 1.3 mm  ×  1.3 mm of die area. Power consumption is 36 mW for the core and 135 mW for on-chip clocks.     

Analytical formulation of transient oscillation amplitude in rotary traveling wave oscillators

This paper presents an accurate analysis for deriving transient oscillation amplitude of Rotary Traveling Wave Oscillators (RTWOs) as a transmission-line based and high frequency circuit. The procedure of the paper is based on considering the nonlinear behavior of negative transconductors that are used for loss compensation of the transmission line. Finally, a closed-form expression for the time-domain amplitude of the RTWOs is obtained. The proposed useful and accurate expression could be used for designing the RTWOs for high performance-high speed systems. Also, it enables us to analyze and synthesize the oscillators with the desired transient behavior. This aspect of the RTWOs is not studied in previous works. The proposed theoretical results are then compared with accurate simulations. Simulations have been done in 0.18 μm CMOS technology with 1.8 V supply voltage. Results show less than 10% difference in steady state oscillation amplitude of theoretical expression and simulations. Considering the nonlinear equation of the RTWOs amplitude, complicated type of solving, simplifications and its numerical solution, the proposed derived expression has a good agreement with simulations.     

Intra-chip wireless interconnect for clock distribution implementedwith integrated antennas, receivers, and transmitters

A wireless interconnect system which transmits and receives RF signals across a chip using integrated antennas, receivers, and transmitters is proposed and demonstrated. The transmitter consists of a voltage-controlled oscillator, an output amplifier, and an antenna, while the receiver consists of an antenna, a low-noise amplifier, a frequency divider, and buffers. Using a 0.18-μm CMOS technology, each of these individual circuits is demonstrated at 15 GHz. Wireless interconnection for clock distribution is then demonstrated in two stages. First, a wireless transmitter with integrated antenna generates and broadcasts a 15-GHz global clock signal across a 5.6-mm test chip, and this signal is detected using receiving antennas. Second, a wireless clock receiver with an integrated antenna detects a 15-GHz global clock signal supplied to an on-chip transmitting antenna located 5.6 mm away from the receiver, and generates a 1.875-GHz local clock signal. This is the first known demonstration of an on-chip clock transmitter with an integrated antenna and the second demonstration of a clock receiver with an integrated antenna, where the receiver's frequency and interconnection distance have approximately been doubled over previous results     

Differential CMOS circuits for 622-MHz/933-MHz clock and datarecovery applications

This paper describes the architecture and components of a high-speed clock and data recovery (CDR) circuit. Fully differential CMOS circuits are presented for an integrated physical layer controller of a 622-Mb/s (OC-12) system, although the design can be used in other systems with clock speeds in the 622-933-MHz range. Simulations and experimental results are presented for the building blocks including novel designs for a current-controlled oscillator (CCO) and a differential charge pump. The CCO is based on a two-stage ring oscillator. It consists of parallel differential amplifier pairs which reliably generate the necessary phase shift and gain to fulfill the oscillation conditions over process and temperature variations. Two test chips are implemented in 0.35-μm CMOS. One contains partitioned building blocks of a phase-locked loop (PLL) which, together with an external loop filter, can be used for flexible testing and CDR applications. The other chip is a monolithic CDR with integrated loop filter. It exhibits a power consumption of 0.2 W and a measured rms clock jitter of 12.5 ps at 933 MHz     

A fully integrated 2.4-GHz LC-VCO frequency synthesizer with 3-psjitter in 0.18-μm standard digital CMOS copper technology

In this paper, we present a fully integrated frequency synthesizer, using an LC voltage-controlled oscillator (LC-VCO) as the core oscillator. The synthesizer is designed to provide various output clock signals for a transceiver chip. Sampling clocks for on-chip analog-to-digital and digital-to-analog conversion modules are also generated, where low jitter is required. The synthesizer also includes an additional digital phase-locked loop and programmable fractional dividers. We present the general concept, special issues related to low jitter, and test chip results. The synthesizer achieves 3-ps rms long-term jitter on a 200-MHz output with 20-mW power and an area of 0.7 mm²     

A Monolithic and Self-Referenced RF LC Clock Generator Compliant With USB 2.0

A monolithic and self-referenced radio frequency (RF) LC clock generator that is compliant with USB 2.0 is demonstrated in a system-on-chip (SoC). This work presents the first successful approach to replacing an external crystal (XTAL), the crystal oscillator (XO) and the phase-locked loop for clock generation in an IC supporting USB 2.0 using a standard CMOS fabrication process. It is shown that the primary design challenges with the implemented approach involve maintaining high frequency accuracy and low jitter. Techniques for addressing both are shown. In particular, the presented architecture exploits the effects of frequency division and low far-from-carrier phase noise to achieve low jitter. From a 1.536 GHz temperature-compensated LC reference oscillator, coherent clock signals are derived at 96MHz for the SoC logic and 12 MHz for an on-chip full-speed USB PHY. Though self-referenced, approximately plusmn400ppm total frequency accuracy is achieved over process variations, plusmn10% variation in the USB power supply voltage and temperature variation from -10 to +85degC. Measured period and cycle-to-cycle jitter are 6.78 ps_rms and 8.96 ps_rms, respectively. Fabricated in a 0.35 mum CMOS technology, the clock generator occupies 0.22 mm² and draws 9.5 mA from a 3.3-V supply, which is derived from the 5-V USB power supply     

高稳定度和宽电源电压范围晶体振荡器芯片设计

基于0.6μm CMOS混合信号工艺设计了一款高稳定度、宽电源电压范围的晶体振荡器芯片。该芯片片内集成具有优异频率响应的振荡器电容和反馈电阻,只需外接石英晶体即可提供高稳定时钟源。测试结果表明:芯片最高工作频率可达40MHz;在振荡频率12MHz、负载电容15pF、电源电压从2.7V到5.5V变化时其频率随电源电压变化率小于1×10-6;电源电压为5V时芯片消耗总电流小于4mA。     

A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS

We present a low-jitter digital LC phase-locked loop (PLL) in a standard digital 130-nm CMOS technology, aiming at, but not limited to, clock multiplication in high-speed digital serial interface transceivers. The PLL features a fully digital core and a digitally controlled LC oscillator. The use of an integrated programmable coil enables triple-band operation in multi-GHz range (2.2, 3.4, and 4.6 GHz) on a die area as small as 0.21 mm/sup 2/. A new architecture is proposed which improves the authors' previous work and allows to achieve an outstanding long-term jitter lower than 650 fs over the whole frequency range. The PLL consumes 13 mA of current at 1.5-V supply. Its performances compete favorably with the most advanced analog PLLs and are ahead of digital PLLs. Its digital nature makes it easily realizable in the mainstream digital CMOS technologies, robust against noise, and thus ideal for application as a low-jitter clock multiplying unit in digital intensive systems on chip.     

A 10-Gb/s CMOS CDR and DEMUX IC With a Quarter-Rate Linear Phase Detector

This paper presents a 10-Gb/s clock and data recovery (CDR) and demultiplexer IC in a 0.13-mum CMOS process. The CDR uses a new quarter-rate linear phase detector, a new data recovery circuit, and a four-phase 2.5-GHz LC quadrature voltage-controlled oscillator for both wide phase error pulses and low power consumption. The chip consumes 100 mA from a 1.2-V core supply and 205 mA from a 2.5-V I/O supply including 18 preamplifiers and low voltage differential signal (LVDS) drivers. When 9.95328-Gb/s 2³¹-1 pseudorandom binary sequence is used, the measured bit-error rate is better than 10^-15 and the jitter tolerance is 0.5UIpp, which exceeds the SONET OC-192 standard. The jitter of the recovered clock is 2.1 psrms at a 155.52MHz monitoring clock pin. Multiple bit rates are supported from 9.4 Gb/s to 11.3 Gb/s     

A CMOS oscillator for radiation-hardened,low-power space electronics

This article presents the design, manufacturing and test results of an on-chip CMOS oscillator, using a ring-oscillator, VCO based architecture. The oscillator generates a configurable square waveform clock signal to be used internally or externally to the IC that integrates it, with very low area (320 transistors, 112?×?148?µm) and power overhead (975?µW). The oscillator is integrated in a mixed signal IC which has been qualified for space applications, at a commercial 250?nm process. It enables the standalone operation of the IC without external oscillator and gives the possibility to clock other components and systems. In addition, it reduces the noise interference at PCB and chip level, optimising the performance of sensitive analogue parts. It was validated by radiation tests according to ESA standards’ procedures that the oscillator's functionality and characteristics do not deteriorate with TID levels up to 1Mrad. This approach can be easily adjusted to a wide range of frequencies, while significantly reducing the cost and power budget of space qualified systems with small design effort trade-off.     

A time digitizer CMOS gate-array with a 250 ps time resolution

A pipelined time digitizer CMOS gate-array has been developed using 0.5 μm Sea-of-Gate technology. Precise timing signals which are used to sample input signals are generated from 32 taps of an asymmetric ring oscillator. The frequency of the oscillator is controlled by a phase-locked loop (PLL) circuit which runs in the 10-50 MHz frequency range. A test chip has been developed and tested; a time resolution of 250 ps rms at 40 MHz clock was measured. The chip has 4 channels and encoding circuits for both the rising and the falling edges of the input signals. The chip has 128-word dual-port memories, allowing the histories of the input signals to be stored and causing no deadtime for the conversion     

CMOS Oscillators for Clock Distribution and Injection-Locked Deskew

The distribution and alignment of high-frequency clocks across a wide bus of links is a significant challenge in modern computing systems. A low power clock source is demonstrated by incorporating a buffer into a cross-coupled oscillator. Because the load is isolated from the tank, the oscillator can directly drive 50-Ohm impedances or large capacitive loads with no additional buffering. Using this topology, a quadrature VCO (QVCO) is implemented in 0.13 $mu hbox{m}$ digital CMOS. The QVCO oscillates at 20 GHz, consumes 20 mW and provides 12% tuning range. The measured phase noise is $-101~hbox{dBc}/hbox{Hz}$ @ 1 MHz frequency offset. A clock alignment technique based upon injection-locked quadrature-LC or ring oscillators is then proposed. Although injection-locked oscillators (ILOs) are known to be capable of deskewing and jitter filtering clocks, a study of both LC and ring ILOs indicates significant variation in their jitter tracking bandwidth when used to provide large phase shifts. By selectively injecting different phases of a quadrature-LC or ring VCO, this problem is obviated resulting in reduced phase noise. The technique is demonstrated using a LC QVCO at 20 GHz while burning only 20 mW of power and providing an 8 dB improvement in phase noise. A ring oscillator deskews a 2 to 7 $~$GHz clock while consuming 14 mW in 90 nm CMOS.      

A CMOS 10-gb/s SONET transceiver

This paper presents a single-chip SONET OC-192 transceiver (transmitter and receiver) fabricated in a 90-nm mixed-signal CMOS process. The transmitter consists of a 10-GHz clock multiplier unit (CMU), 16:1 multiplexer, and 10-Gb/s output buffer. The receiver consists of a 10-Gb/s limiting input amplifier, clock and data recovery circuit (CDR), 1:16 demultiplexer, and drivers for low-voltage differential signal (LVDS) outputs. Both transmit and receive phase-locked loops employ a 10-GHz on-chip LC voltage-controlled oscillator (VCO). This transceiver exceeds all SONET OC-192 specifications with ample margin. Jitter generation at 10.66-Gb/s data rate is 18 mUI/sub pp/ (unit interval, peak-to-peak) and jitter tolerance is 0.6 UI/sub pp/ at 4-MHz jitter frequency. This transceiver requires 1.2V for the core logic and 1.8 V for input/output LVDS buffers. Multiple power supply domains are implemented here to mitigate crosstalk between receiver and transmitter. The overall power dissipation of this chip is 1.65 W.     

基于电感电容振荡器的电荷泵锁相环的设计

设计并实现了一种采用电感电容振荡器的电荷泵锁相环,分析了锁相环中鉴频/鉴相器(PFD)、电荷泵(CP)、环路滤波器(LP)、电感电容压控振荡器(VCO)的电路结构和设计考虑。锁相环芯片采用0.13μm MS&RF CMOS工艺制造。测试结果表明,锁相环锁定的频率为5.6～6.9 GHz。在6.25 GHz时,参考杂散为-51.57 dBc;1 MHz频偏处相位噪声为-98.35 dBc/Hz;10 MHz频偏处相位噪声为-120.3 dBc/Hz;在1.2 V/3.3 V电源电压下,锁相环的功耗为51.6 mW。芯片总面积为1.334 mm2。     

Reliability assessment of CMOS differential cross-coupled LC oscillators and a novel on chip self-healing approach against aging phenomena

In this paper, reliability of CMOS differential cross-coupled LC oscillators is examined, and a novel on chip aging detection and healing technique is developed to increase the lifetime of oscillator circuits. Aging causes degradation in several transistor parameters, such as threshold voltage, mobility, and transconductance. While these changes cause irregular timing characteristics and increased power consumption in digital circuits, the case is quite different for their analog counterparts. Analog circuits, especially nonlinear ones, show more deviations at the output due to parameter changes. In order to evaluate the aging effects on nonlinear analog circuits, two different oscillator structures (n-type and p-type) with 5 GHz oscillation frequency were designed using 0.13 μm technology. The phase noise analysis of fresh and aged oscillators was performed analytically and through simulations. Based on these analyses the robustness of oscillators was discussed. Finally, an on chip aging sensor and self recovery mechanism are proposed to increase the robustness of the CMOS LC oscillators.     

A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-/spl mu/m CMOS

This paper demonstrates a low-jitter clock multiplier unit that generates a 10-GHz output clock from a 2.5-GHz reference clock. An integrated 10-GHz LC oscillator is locked to the input clock, using a simple and fast phase detector circuit that overcomes the speed limitation of a conventional tri-state phase frequency detector due to the lack of an internal feedback loop. A frequency detector guarantees PLL locking without degenerating jitter performance. The clock multiplier is implemented in a standard 0.18-/spl mu/m CMOS process and achieves a jitter generation of 0.22 ps while consuming 100 mW power from a 1.8-V supply.     

8GS/s-14bit RF-DAC中数字上变频器的ASIC实现

本文提出了一种内嵌于8GS/s-14bit RF-DAC中数字上变频器(DUC)的设计方案,该方案采用ASIC实现,能够得到采样频率达8 GHz的输出信号,并提供插值因子分别为2、4、8、16的上变频功能.基于CORDIC算法,提出16路时域交织的数控振荡器(NCO)结构,同时采用全半带滤波器(HB-FIR)折叠结构级联实现内插滤波器组.基于40 nm CMOS工艺,完成RTL级设计和GDSII版图设计,并将其内嵌于8 GS/s-14bit RF-DAC中完成混合SOC的电路设计与验证.测试结果显示,该设计可以在500 MHz的工作时钟频率下达到设计目标,数字部分的版图面积为2551*2580μm^2,仿真功耗约为1365.4 mW.在40 nm CMOS工艺下流片,流片测试结果显示该芯片设计能够完成预设目标,且在插值为16的模式下,测得芯片数字部分功耗为为1250 mW,符合设计预期.     

Jitter Characteristic in Charge Recovery Resonant Clock Distribution

This paper is focused on analysis and suppression of clock jitter in charge recovery resonant clock distribution networks. In the presented analysis, by considering the data-dependent nature of the generated jitter, the reason for the undesired jitter-peaking phenomenon is investigated. The analysis has been verified by measurements on a test chip fabricated in 0.13-mum standard CMOS process. The chip includes a fully integrated 1.5-GHz LC clock resonator with a passive (bufferless) clock distribution network, which directly drives the clocked devices in pipelined data path circuits. Furthermore, a jitter suppression technique based on injection locking is presented. Measurement results show about 50% peak-to-peak clock jitter reduction from 28.4 ps down to 14.5 ps after injection locking.