具有跟踪滤波及开关电容滤波的正弦波振荡器

对于总线控制的振荡器而言，往往是产生一个低失真10Hz至10kHz正弦输出。一般的低成本函数发生器采用二极管成形技术把方波转变成正弦波。而二阶和三阶谐波分别的典型值为-35dBm和-25．5dBm。此电路产生正弦输出，在整个输出范围内典型的二阶和三阶谐波分别为-76．1dBm和-74．2dBm。     

构成单片正弦波振荡器的可编程模拟电路

可编程逻辑器件为数字设计中复杂功能的实现提供了一种流行的方法。虽然制造商尚未提供能与VLSI数字电路复杂性相比拟的模拟电路,但现场可编程模拟电路正在信号调整和滤波应用中获得广泛采用。这些器件基于CMOS跨导及开关式电容放大器,可为相对复杂的设计问题提供一种便利的解决方案。Lattice     

A low-phase-noise 900-MHz CMOS ring oscillator with quadrature output

A 900-MHz two-stage CMOS voltage controlled ring oscillator (VCRO) with quadrature output is presented. The circuit is designed in a 0.18-um CMOS technology and operated on a 1.8-V supply voltage. The VCRO have a tuning range of 730 MHz to 1.43 GHz and good tuning linearity. Between 0 V and 1.1 V of control voltage, the gain of VCRO is around −620 MHz/V. At 900 MHz, the phase noise of the VCRO is −106.1 dBc/Hz at 600-KHz frequency offset with power consumption of 65.5 mW.     

CMOS level shifters from 0 to 18 V output

A design methodology for level shifters voltage translators, where the output voltage ranges from 0 to 18 V, and the input voltage ranges from 2 to 5.5 V in a 0.6 µm CMOS-HV technology, is presented. This family of circuits have a special interest in the case of implantable medical devices where is common to handle previously unknown voltages either positive or negative, above or below the control logic supply V_DD. Two application examples are presented: a composite switch to control negative stimuli voltage pulses, and a multi-channel programmable charge-pump voltage multiplier, aimed at charging the output capacitors of an IMD.

     

跳频发射机自动电平控制的实现方法

针对传统自动电平控制（ALC）在跳频发射机控制过程中存在功 率过冲、建立时间长的技术弊端,提出了一种改进的ALC电路的实现方法,即跳频时钟禁发法 。工程实践证明, 所提方法 是解决该瓶颈的有效方法,已成功应用于某跳频通信电台中。     

自动电平控制电路在电视发射机中的应用

１ 概述在电子设备中,人们经常利用反馈的方法来改善电路的工作性能,使电路输出量的变化反过来影响输入回路,从而控制输出端的变化,起到系统自动调节的作用。一部电视发射机由很多部分组成,它消耗一定的能源,在限定的空间内要产生大量的热量,这对半导体器件的影响很大,输出功率便受到影响。自动电平控制（ＡＬＣ）电路就是为了稳定发射机输出功率而在负反馈系统中设置的控制电路,发射机中ＡＬＣ负反馈系统的方框图如图１所示。图１中,由定向耦合器耦合出的射频信号送入ＡＬＣ电路,经检波、比较产生出误差信号,以控制变频器输出…     

基于模糊理论的料位自动控制技术分析

在现代工业的控制系统中,PLC/DCS控制系统具有广泛的应用,但是对于参与控制的模拟量,尤其是闭环控制,就要复杂得多,运用模糊控制理论设计模拟量的控制算法,使得控制由点控制变成区段控制,突破了计算机控制的局限性。以料位控制系统为例,由于采用了模糊控制理论,该系统电路结构简单、程序清晰、系统可靠性高,完全闭合地实现了根据设备中物料的量控制速度,对实现该类设备的自动化具有重要意义。     

PLC-based optical add/drop switch with automatic level control

A novel switch configuration for an optical add/drop multiplexer is proposed. By utilizing a certain Mach-Zehnder interferometer both as a component of a double-gate switch and as a level equalizer, we reduced the number of Mach-Zehnder interferometers from five in a conventional switch configuration to three. The add/drop switch simultaneously provides high-isolation switching and polarization-independent automatic level control. The use of planar lightwave circuit (PLC) technology enables this switch to be fabricated with three thermooptic switches (TOSWs) and a monitor tap. High isolation of more than 44 dB and automatic level control accuracy of better than 0.3 dB are achieved. Bit error rate (BER) measurements confirmed switch's usability in the optical add/drop multiplexer     

带高精度步进的输出幅度可配置的宽带自动增益控制器

本文介绍了一种用于全球导航接收机的带高精度步进的输出幅度可配置的宽带自动增益控制器。自动增益控制器的输出幅度可配置是为了配合基带芯片达到对干扰信号的抑制,同时配合适用于不同的满幅度的ADC。本文引入增益加强技术改进步进精度,同时加入由源级负反馈电阻和电容组成的零点抵消主电路的极点展宽电路带宽。本设计基于CMOS 0.18工艺。本设计提供高达62dB的动态范围,步进1dB,步进精度0.2dB。本设计电路提供高达80MHz的带宽,并且消耗低于1.8mA电流,整个设计芯片面积为800um*300um     

G.169自动电平控制装置标准及其实现

介绍ITU－T G．169自动电平控制装置标准及其性能要求，提出一种基于该协议的自动电平控制系统结构，并设计系统的实现算法，计算机仿真结果表明，笔者提出的ALC系统可行有效，能满足G．169的要求。     

A 1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM: with charge-recyclinginput/output buffers

This paper presents a high-speed and low-power SRAM for portable equipment, which is operated by a single battery cell of around 1 V. Its memory cells are made up of high-threshold-voltage (high-V_th) MOSFETs in order to suppress the power dissipation due to large subthreshold leakage currents. For designing peripheral circuitry, we use SRAM's special feature that input signals of each logic gate during the standby time can be predicted. Low-V_th MOSFETs are assigned for the critical paths of memory-cell access. The leakage current in each logic gate is reduced by high-V_th MOSFETs, which are cut off during standby. The high-V_th, MOSFET in one logic gate can be shared with another logic gate in order to enlarge effective channel width. To shorten the readout time, a step-down boosted-wordline scheme suitable for current-sense readout and a new half-swing bidirectional double-rail bus are used. The data-writing time is halved by means of a pulse-reset wordline architecture. To reduce the power dissipation, a 32-divided memory array structure is employed with a new redundant address-decoding scheme. Also, data transition detectors and a charge-recycling technique are employed for reducing the power dissipation of data-I/O buffers. A 64-K-words×16-bits SRAM test chip, which was fabricated with a 0.5-μm multithreshold voltage CMOS (MTCMOS) process, has demonstrated a 75-ns address access time at a 1-V power supply. The power dissipation during standby is 1.2 μW, and that at a 10-MHz read operation with the modified checkerboard test pattern is 3.9 mW for 30-pF loads     

A 400-MHz, 12-bit, 18-mW, IF digitizer with mixer inside asigma-delta modulator loop

A 0.8-μ BiCMOS, 400-MHz intermediate-frequency digitizer based on embedding a down-conversion mixer inside a sigma-delta modulator together with a reconstruction filter in the feedback path has been developed. The digitizer, when subsampled with a clock of 20 MHz, achieves a measured resolution of 12 bits for a 40-kHz bandwidth and dissipates 18 mW of power. The third harmonic distortion (HD₃) is less than -90 dBc for a -4-dB input, and the third-order intermodulation product (IM₃) is less than -70 dBc for a -8-dB input, with a full-scale voltage of 0.5 V. The chip area is 1.5 mm²