500 MS / s 12 位流水线 ADC 的设计研究

在超高速高精度模数转换器(ADC)设计中,低压运算放大器及其数字辅助校准算法至关重要。基于40 nm CMOS工艺、工作电压1.1 V,设计了一款500 MS/s、12位流水线ADC。系统采用前端无采保结构及低压级间运算放大器以降低系统功耗。本文提出了一种基于数字检测的算法校准级间增益和电容失配误差,使用较小的面积和功耗有效提高了ADC的整体性能。本数字校准方案将ADC的差分非线性(DNL)和积分非线性(INL)从2.4 LSB和5.9 LSB降低为1.7 LSB和0.8 LSB。对于74.83 MHz的正弦信号,校准技术分别实现了63.14 dB的信号-失真噪声比(SNDR)和75.14 dB的无杂散动态范围(SFDR),功耗为123 mW,满足设计指标,证明了带有数字校正的低压流水线ADC设计的有效性。     

一种低电压、高速CMOS运放的设计与仿真

本文设计了一种基于流水线ADC系统应用的低电压、高速运算放大器,该运放使用折叠式共源共栅结构、稳定的电压偏置电路、新型的共模反馈电路,使运放达到更高的性能.设计基于BSIM3V3 Spice模型,采用SMIC标准0.18 μm CMOS工艺,用Cadence的Spectre工具对整个电路进行仿真.在1.8 V单电源电压、2 pF电容负载的工作条件下,仿真结果显示:直流开环增益为82 dB,其单位增益带宽为260 MHz,相位裕度60°,压摆率100 V/μs,建立时间约10 ns,功耗只有3.6 mW,达到了设计要求.     

采用1.75 Gbps串行发送器的低功耗14位125 MSPS ADC

提供了一种适宜于多通道集成的低功耗、小面积14位125 MSPS流水线模数转换器(ADC)。该ADC基于开关电容流水线ADC结构,采用无前端采样保持放大器、4.5位第一级子级电路、电容逐级缩减和电流模串行输出技术设计并实现。各级流水线子级电路中所用运算放大器使用改进的"米勒"补偿技术,在不增加电流的条件下实现了更大带宽,进一步降低了静态功耗;采用1.75 Gbps串行数据发送器,数据输出接口减少到2个。该ADC电路采用0.18μm 1P5M 1.8 V CMOS工艺实现,测试结果表明,该ADC电路在全速采样条件下对于10.1 MHz的输入信号得到的SNR为72.5 d BFS,SFDR为83.1 d B,功耗为241 m W,面积为1.3 mm×4 mm。     

一种新颖的CMOS电流控制型可变增益放大器

采用0.35μm CMOS技术实现了一种增益按指数规律变化的电流控制型可变增益放大器(VGA)。通过采用Pseudo-exponential函数逼近方法设计指数发生电路,在1.5 V电压下工作所消耗的功率不超过1 mW。仿真结果表明,在输入控制电流误差为0.5 db的范围内,该VGA的增益控制范围可以达到30 db,适用于各种模拟信号处理电路。     

60GHz无线收发机中宽带可变增益放大器的设计

本文采用TSMC65nmRFCMOS工艺设计实现了一种应用于60GHz高速无线通信接收机中的低功耗、高线性度、dB线性控制型的宽带可变增益放大器。该电路采用四级改进的Cherry—Hooper放大器级联结构．通过改变每级放大器单元中反馈电阻的大小获得22dB的可调增益。同时通过采用双负反馈直流失调消除电路,有效的减小了直流失调。仿真结果表明,可变增益放大器在1．2V低电压下,电路功耗仅为3．5row,增益变化范围为10dB～32dB;在最大增益32dB时3dB带宽为2．28GHz,增益压缩1dB时输出差分信号摆幅达到566mVpp。     

625 MS/s、12 bit双通道时间交织ADC的设计研究

基于40 nm CMOS工艺,设计了一款625 MS/s、12 bit双通道时间交织模数转换器(ADC)。单通道ADC采用了前端无采保模块的流水线架构以降低系统功耗。系统采用了宽带高线性度前级驱动电路以及高速高精度栅压自举开关以保证交织系统的有效输入带宽。一种基于辅助通道的后台校正算法被用于校正通道间采样时间失配,该后台校正方法可适用于完全随机输入信号。芯片核心面积为0.69 mm~2。后仿真结果表明,该625 MS/s、12 bit时间交织ADC在全速率下进行奈奎斯特采样,系统无杂散动态范围(SFDR)为67 dB,信号-失真噪声比(SNDR)为58.5 dB,功耗为295 mW,满足设计指标,证明了设计的有效性。     

基于正弦波点击率的非线性误差测试方法

针对ADC在通讯和多媒体技术上的应用需求,研究了基于正弦波点击率的ADC非线性误差测试方法,实现了正弦波点击率技术在ADC非线性误差测试中的应用。向ADC输入正弦波信号,对输出数字码进行标准化处理,补偿正弦波形电压分布的不均匀性,通过点击率算法推算 ADC 的微分非线性误差,并在大规模数模混合测试设备Catalyst-200上验证了算法的可靠性和精确性。实验结果表明,该算法能够精确地估算 ADC非线性误差,完整地表征了ADC线性度和丢码率,为ADC在通讯和多媒体技术上的应用提供了重要的参数依据,具有较强的工程实用性和市场前景性。     

基于时间放大技术的时间数字转换器的设计

本文基于时间放大技术设计了一种两步式的时间数字转换器(TDC),可应用于高精度的飞行测量领域。本设计采用SMIC 55 nm CMOS工艺,采用环形延时TDC作为粗量化电路,采用游标式TDC作为细量化电路。游标式TDC的精度受到延时失配限制,导致在设计时难以突破更高精度的要求。时间放大器通过放大粗量化产生的时间余量,并继续进行第二次细量化,降低了细量化电路的设计难度。针对传统时间放大器输入范围有限以及放大精确度不足的弊端,提出一种新的时间放大器结构,具有精确放大宽范围输入时间间隔的能力。仿真结果表明,采用该种时间放大器的TDC可实现的分辨率为3.7 ps,测量范围为80 ns,微分非线性(DNL)为0.73 LSB,积分非线性(INL)为0.95 LSB,该设计能够在高线性度下更好地兼顾TDC的分辨率与测量范围。     

基于非线性观测器的永磁同步电机位置估计算法研究

为提高表贴式永磁同步电机无位置传感器控制中转子位置和速度的估计精度,提出了一种改进型非线性观测器。通过重构非线性观测器的数学模型,构建了误差方程,利用Lyapunov理论对误差方程进行了稳定性分析。并基于稳定性条件提出了一种误差项步长优化方法,实现了非线性观测器的步长增益自调节。仿真与试验结果表明,改进型非线性观测器具有良好的动态性能,验证了其可行性。     

德州仪器推出业界最高精度数模转换器

日前，德州仪器（TI）宣布推出业界最高精度的数模转换器（DAC），该器件具有18位单调性、±2LSB积分非线性误差（INL）、±1LSB微分非线性误差（DNL）等优势。DAC9881采用小型QFN-24封装，使客户可提高系统性能并简化设计工艺，从而满足自动测试设备、仪表、过程控制、数据采集以及通信系统等高精度工业应用领域的需求。     

流水线模数转换器设计

设计了一款14位、125MS/s流水线模数转换器(ADC)。通过前端采样/保持电路(SHA)消除对输入信号采样的孔径误差,采用4位结构的首级转换电路提高ADC线性性能,设计了带输入缓冲的栅压自举开关以缓解首级转换电路输入采样开关中自举电容对SHA的负载效应,流水线ADC级间通过逐级按比例缩减策略使功耗得到节省。该设计采用0.18μm 1P5MCMOS工艺,ADC版图面积2.3 mm×1.4 mm。Spectre后仿真结果显示,采样频率125 MHz、输入信号在接近Nyquist频率(61MHz)处时信号噪声畸变比(SNDR)和无杂散动态范围(SFDR)可分别达到75.7 dB和85.9 dB。在1.8V电源电压下,ADC核心部分功耗为263 mW。     

智能型无功补偿控制器的研制

以高速低功耗16位单片机为控制核心,配合16位同时采样ADC芯片,实现谐波条件下的对三相电压、电流真有效值、有功功率、无功功率、视在功率、功率因数、频率、温度的实时精确测量,实现对电容器按特定逻辑投切,可满足电网无功补偿的快速性要求。介绍了该装置控制原理和控制电路主要构成,并且通过高精度功率信号源模拟,给出了主要的项目测试数据,基本证明设计正确无误。     

智能型无功补偿控制器的研制

以高速低功耗16位单片机为控制核心,配合16位同时采样ADC芯片,实现谐波条件下的对三相电压、电流真有效值、有功功率、无功功率、视在功率、功率因数、频率、温度的实时精确测量,实现对电容器按特定逻辑投切,可满足电网无功补偿的快速性要求。介绍了该装置控制原理和控制电路主要构成,并且通过高精度功率信号源模拟,给出了主要的项目测试数据,基本证明设计正确无误。     

Design considerations for low power time‐mode SAR ADC

This paper describes circuit design considerations for realization of low power dissipation successive approximation register (SAR) analog‐to‐digital converter (ADC) with a time‐mode comparator. A number of design issues related to time‐mode SAR ADC are discussed. Also, noise and offset models describing the impact of the noise and offset on the timing error of time‐domain comparator are presented. The results are verified by comparison to simulations. The design considerations mentioned in this paper are useful for the initial design and the improvements of time‐mode SAR ADC. Then, a number of practical design aspects are illustrated with discussion of an experimental 12‐bit SAR ADC that incorporates a highly dynamic voltage‐to‐time converter and a symmetrical input time‐to‐digital converter. Prototyped in a 0.18‐µm six‐metal one‐polysilicon Complementary Metal‐Oxide‐Semiconductor (CMOS) process, the ADC, at 12 bit, 500 kS/s, achieves a Nyquist signal‐to‐noise‐and‐distortion ratio of 53.24 dB (8.55 effective number of bits) and a spurious‐free dynamic range of 70.73 dB, while dissipating 27.17 μW from a 1.3‐V supply, giving a figure of merit of 145 fJ/conversion‐step. Copyright © 2013 John Wiley & Sons, Ltd.     

A 0.008‐mm2, 35‐μW, 8.87‐ps‐resolution CMOS time‐to‐digital converter using dual‐slope architecture

This paper presents a high resolution time‐to‐digital converter (TDC) for low‐area applications. To achieve both high resolution and low circuit area, we propose a dual‐slope voltage‐domain TDC, which is composed of a time‐to‐voltage converter (TVC) and an analog‐to‐digital converter (ADC). In the TVC, a current source and a capacitor are used to make the circuit as simple as possible. For the same reason, a single‐slope ADC, which is commonly used for compact area ADC applications, is adapted and optimized. Because the main non‐linearity occurs in the current source of the TVC and the ramp generator of the ADC, a double gain‐boosting current source is applied to overcome the low output impedance of the current source in the sub‐100‐nm CMOS process. The prototype TDC is implemented using a 65‐nm CMOS process, and occupies only 0.008 mm². The measurement result shows a dynamic range with an 8‐bit 8.86‐ps resolution and an integrated non‐linearity of ±1.25 LSB. Copyright © 2016 John Wiley & Sons, Ltd.     

A 7.5‐μW 0.08‐mm2 single‐ended SC delta‐sigma ADC for acoustic sensor applications

This study presents an ultra‐low‐power, small‐size, 1‐bit, single‐ended, and switched‐capacitor (SC) delta‐sigma analog‐to‐digital converter (ADC) for wireless acoustic sensor nodes. This wireless sensor node has a delta‐sigma ADC that converts the sensed signal to a digital signal for convenient data processing and emphasizes the features of small size and low‐power consumption. The chip area of the delta‐sigma ADC is dominated by the capacitor; therefore, a novel common‐mode (CM) controlling technique with only transistors is proposed. This ADC achieves an extremely small size of 0.08 mm² in a 130‐nm CMOS process. The conventional operational transconductance amplifiers (OTAs) are replaced by inverters in the weak inversion region to achieve high power efficiency. At 4‐MHz sampling frequency and 0.7‐V power supply voltage, the delta‐sigma ADC achieves a 55.8‐dB signal‐to‐noise‐plus‐distortion ratio (SNDR) and a 298‐fJ/step figure‐of‐merit (FOM) in a signal bandwidth of 25 kHz, while consuming only 7.5 μW of power. Copyright © 2015 John Wiley & Sons, Ltd.     

FFT‐based calibration method for 1.5 bit/stage pipelined ADCs

A fast Fourier transform (FFT)‐based digital calibration method for 1.5 bit/stage pipeline analog‐to‐digital converter (ADC) is proposed in this paper. Capacitor mismatch and finite gain of the operational amplifier (OPAMP) can be overcome by the proposed calibration method. Given that the capacitor mismatch and the finite OPAMP gain cause the radix of all the stages of 1.5 bit/stage pipeline ADC to become unequal to 2, the FFT processor can be adopted to evaluate the actual radixes of all the stages and then generate new digital output to compensate for error caused by these non‐ideal effects. Moreover, as capacitor mismatch and the finite gain of OPAMP can be compensated, low‐gain OPAMP can be used in high‐performance ADC to reduce power dissipation; a small capacitor can then be adopted to save on space. An example of a 10 bit 1.5 bit/stage pipelined ADC with only an 8 bit circuit performance is implemented in 0.18 µm TSMC CMOS process. Circuit measurement result reveals that the signal‐to‐noise‐and‐distortion ratio of 51.03 dB with 11 dB improvement after calibration can be achieved at the sample rate of 1 MHz. Copyright © 2013 John Wiley & Sons, Ltd.     

A 0.8‐V supply bulk‐driven operational transconductance amplifier and Gm‐C filter in 0.18 µm CMOS process

A low voltage bulk‐driven operational transconductance amplifier (OTA) and its application to implement a tunable Gm‐C filter are presented. The linearity of the proposed OTA is achieved by nonlinear terms cancelation technique, using two paralleled differential topologies with opposite signs in the third‐order harmonic distortion term of the differential output current. The proposed OTA uses 0.8 V supply voltage and consumes 31.2 μW. The proposed OTA shows a total harmonic distortion of better than ?40 dB over the tuning range of the transconductance, by applying 800 mV_ppd sine wave input signal with 1 MHz frequency. The OTA has been used to implement a third‐order low‐pass Gm‐C filter, which can be used for wireless sensor network applications. The filter can operate as the channel select filter and variable gain amplifier, simultaneously. The gain of the filter can be tuned from ?1 to 23 dB, which results in power consumptions of 187.2 to 450.6 μW, respectively. The proposed OTA and filter have been simulated in a 0.18 µm CMOS technology. Simulations of process corners and temperature variations are also included in the paper. Copyright © 2014 John Wiley & Sons, Ltd.     

A 10 b 25 MS/s 4.8 mW 0.13 µm CMOS ADC with switched‐bias power‐reduction techniques

This paper proposes a 10 b 25 MS/s 4.8 mW 0.13 µm CMOS analog‐to‐digital converter (ADC) for high‐performance portable wireless communication systems, such as digital video broadcasting, digital audio broadcasting, and digital multimedia broadcasting (DMB) systems, simultaneously requiring a low‐voltage, low‐power, and small chip area. A two‐stage pipeline architecture optimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate, while switched‐bias power‐reduction techniques reduce the power consumption of the power‐hungry analog amplifiers. Low‐noise reference currents and voltages are implemented on chip with optional off‐chip voltage references for low‐power system‐on‐a‐chip applications. An optional down‐sampling clock signal selects a sampling rate of 25 or 10 MS/s depending on applications in order to further reduce the power dissipation. The prototype ADC fabricated in a 0.13 µm 1P8M CMOS technology demonstrates a measured peak differential non‐linearity and integral non‐linearity within 0.42 LSB and 0.91 LSB and shows a maximum signal‐to‐noise‐and‐distortion ratio and spurious‐free dynamic range of 56 and 65 dB at all sampling frequencies up to 25 MHz, respectively. The ADC with an active die area of 0.8 mm² consumes 4.8 and 2.4 mW at 25 and 10 MS/s, respectively, with a 1.2 V supply. Copyright © 2008 John Wiley & Sons, Ltd.