基于SiGe HBT的38GHz功率放大器设计

功率放大器(Power Amplifier,PA)是射频前端关键的模块,基于0.13μm SiGe HBT工艺,设计了一款38 GHz功率放大器。提出了HBT集电极寄生电容和传输线谐振的方法减小芯片面积,针对毫米波频段下,晶体管可获得最大增益较低,采用堆叠晶体管提高了功率放大器的增益,同时通过优化有源器件参数,提高了功率放大器的输出功率和效率。仿真结果显示,在4 V的供电电压下,工作在38 GHz的功率放大器1 dB压缩点输出功率为17.8 d Bm,功率增益为19.0 dB,功率附加效率为32.3%,功耗为252 mW。     

平衡功率放大器的设计与实现

设计了一个工作频段为902MHz～928MHz、输出功率为32dBm、应用于读卡器系统的末级功率放大器。为了在工作频段内实现平坦的功率增益并获得良好的输入、输出驻波比,本功率放大器采用平衡放大技术设计。仿真优化和实际测试表明,在整个工作频段内放大器的增益平坦度小于±0.5dB,输入、输出驻波比小于1.5,完全满足设计指标要求。     

用于UHF RFID的功率放大器设计

功率放大器是UHF RFID系统的重要模块,也是RFID系统中功耗最大的器件。本文采用TSMC0.18rf CMOS工艺,设计了一款用于RFID的线性功率放大器。在915 MHz频段,最大输出功率为17.8 dBm,饱和效率达到了40%,输出1 dB压缩点(P1dB)为15.4 dBm,其小信号增益达到了28.7 dB。     

数字电视发射机中功率放大器的设计

用最新的LDMOSFET器件,采用平衡放大电路结构熏设计数字电视发射机中的功率放大器。工作频段在470MHz～860MHz,整个频带内增益在12dB左右,工作在线性状态,交调抑制小于-35dB。     

大功率宽带射频脉冲功率放大器设计

利用MOS场效应管(MOSFET),采取AB类推挽式功率放大方式,采用传输线变压器宽带匹配技术,设计出一种宽频带高功率射频脉冲功率放大器模块,其输出脉冲功率达1200W,工作频段0.6M￣10MHz。调试及实用结果表明,该放大器工作稳定,性能可靠。     

一种应用于2.2GHz的射频功率放大器设计

采用Cree公司提供的CGH40010F GaN高电子迁移率晶体管(HEM T)作为有源器件,设计了一款工作在2.2 G Hz的射频功率放大器.利用ADS软件对功率管的偏置电路进行设计的仿真,利用阶跃式匹配方法扩展了带宽,通过对功率管寄生参数的仿真,有效地提高了功率附加效率(PA E).仿真结果表明,在2.1 GHz～2.3 GHz的频率范围内,小信号S21增益为12.03 dB～12.77 dB,大信号输出功率为40.17 dBm,功率附加效率达到61.3％.达到设计指标的要求.     

一种0.8GHz～6GHz CMOS超宽带低噪声放大器设计

给出了一个针对0.8GHz～6GHz 的超宽带低噪声放大器 UWB LNA(ultra-wideband low noiseamplifier)设计。设计采用0.18μm RF CMOS 工艺完成。在0.8GHz～6GHz 的频段内,放大器增益 S21达到了17.6dB～13.6dB。输入、输出均实现良好的阻抗匹配,S11、S22均低于-10dB。噪声系数(NF)为2.7dB～4.6dB。在1.8V 工作电压下放大器的直流功耗约为12mW。     

空天车地立体环境下宽带传输系统设计

针对轨道交通运营安全保障需求,本文阐述了一种以临近空间浮空器为中心的空天车地立体环境下的宽带传输系统设计方案,在分析主要技术指标要求的基础上,给出了主要工作参数设计思路,并重点论述了S频段宽带网络收发器和S频段功率放大器设计方案,并在最后给出了验证方法和实测结果,结果表明本文所述方案满足系统指标要求。     

基于功率合成器的20 GHz CMOS功率放大器设计

设计了一个工作频率高达20 GHz、最高输出功率23.4 dBm的CMOS功率放大器(PA),该PA由两级放大器组成,采用全差分Cascode电路结构。PA的输入、级间、输出匹配网络均采用片上变压器实现,实现单端输入、单端输出,功率合成器用来提高PA的输出信号摆幅。该PA基于TSMC 0.18μm CMOS工艺模型进行设计,采用Agilent ADS软件进行PA性能仿真和片上变压器的设计,版图仿真结果表明:在20 GHz频段内,PA的输入、输出完全匹配(S11=-13.85 dB、S22=-10.94 d B),小信号增益S21达到21.5 dB,芯片面积仅为0.56 mm~2。     

驱动级功率放大器的设计与实现

设计了一个工作频段在902 MHz～928 MHz,输出功率为19 dBm、功率增益高达27 dBm、应用于射频识别(RFID)系统的驱动级功率放大器。为缩短功率放大器的研发周期并提高其开发的成功率,设计运用了仿真优化和实际测试相结合的方法。测试结果与仿真结果的高度一致性验证了这种方法的有效性。     

A CMOS low noise amplifier based on common source technique for ISM band application

In this paper a 2.45 GHz narrowband low noise amplifier (LNA) for wireless communication system is enunciated. The proposed CMOS Low Noise amplifier has been verified through cadence spectre RF simulation in standard UMC 90 nm CMOS process. The proposed LNA is designed by cascoding of two transistors; that is the common source transistor drives a common gate transistor. To achieve better power gain along with low noise figure, cascoding of two transistor and source degeneration technique is used and for low power consumption, the MOS transistors are biased in subthreshold region. At 2.45 GHz frequency, it exhibits power gain 31.53 dB. The S11, S22 and S12 of the circuit is ?9.14, ?9.22 and ?38.03 dB respectively. The 1 dB compression point of the circuit is ?16.89 dBm and IIP3 is ?5.70 dBm. The noise figure is 2.34 dB, input/output match of ?9.14 dB/?9.22 dB and power consumption 8.5 mW at 1.2 V.     

基于新型二维核函数动态X参数的功放建模

为了更准确地描述带有记忆效应的射频（RF）功放特性,基于传统的动态X参数模型,结合功放长期记忆效应以及短期记忆效应机理,提出一种新型动态X参数功放建模方法。新模型保留X参数模型的静态核函数,利用双记忆路径模型提取出表征记忆效应的非线性函数,替换动态核函数。采用输出信号为幅度与频率双变量的新型反馈（FB）结构,引入时变频率变量而简化动态核函数为二维核函数。使用MW6S010N设计功放并建模,由仿真可知,新模型在单音大信号及码分多址（CDMA）信号激励下,均能正确表征功放特性,归一化均方误差（NMSE）较静态X参数模型、传统动态X参数模型以及前馈（FF）结构X参数模型分别减少8.0 dB、6.3 dB、2.5 dB。结果表明该模型能够更加准确拟合带有非线性记忆效应功率放大器的特性。     

Analysis and improvement of PSRR in an envelope‐tracking power amplifier using a common‐drain amplifier topology

A common‐drain power amplifier (PA) for envelope tracking systems is presented. In envelope tracking, the main PA operates mostly in compression and the power supply rejection ratio (PSRR) is not high. Furthermore, the output noise of the supply modulator can be mixed with the RF signal and generates out‐of‐band emissions. In this article, instead of using a common‐source topology, the PSRR of the envelope tracking PA is inherently improved by utilizing a common‐drain topology. A comprehensive analysis shows that the common‐drain topology is less sensitive to the supply noise, as compared to the conventional common‐source topology. The proposed common‐drain PA is implemented using a discrete LDMOS PD20010‐E RF transistor. Measurement results show that the PSRR of the proposed common‐drain PA is improved by up to 7 dB as compared to that of the common‐source PA. For a two‐tone input with 10 MHz bandwidth at the center frequency of 700 MHz, the power added efficiency (PAE) and IM3 of the envelope tracking common‐drain PA are 20% and ? 28 dBc, respectively, at an average output power of 33.4 dBm. The amplifier also shows a 12.4 dB power gain. Moreover, by utilizing the envelope tracking, the PAE is improved by more than 5%.     

Design and analysis of a WLAN CMOS power amplifier using multiple‐gated transistor technique

This article focused on 5.2 GHz highly integrated power amplifier for IEEE 802.11a WLAN application. Multiple‐gated transistor technique was used to improve linearity. A new approach for choosing the bias voltage of auxiliary transistor by analyzing the shift of gate bias is used in the design. The simulated results of the proposed two‐stage differential power amplifier indicate 25.28 dBm P_1‐dB, 32.87% PAE, and 26.18 dBm saturated output power with a 5.2 dB P_1‐dB improvement compared to conventional single transistor amplifier. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2011.     

基于ADS线性射频放大器设计与仿真

为了加速射频放大器的设计及产品化过程,用EDA工具软件对放大器先进行仿真是一种有效的方法.提出了一种利用ADS软件对LNA和小信号功率放大器进行设计的方法,并通过实例对1.5GHz频段射频放大器的稳定性、S 参数、功率增益、输入输出匹配等进行了仿真,给出了仿真结果和最终的设计电路.仿真结果表明,放大器匹配电路设计完全满足性能指标要求.这种方法对放大器的设计有着重要的实用价值,可以进行快速的阻抗匹配和优化,从而加速放大器的设计进程.     

Design scheme for broadband Doherty power amplifier using broadband load combiner

This article proposes a design strategy for broadband Doherty power amplifier (PA) using broadband load combiner. The bandwidth of the Doherty PA based on the proposed combiner using packaged transistor is about 2.5 times the bandwidth of conventional Doherty PA using a quarter‐wave transformer. An easy to implement analytical design methodology has been presented for the proposed load‐combiner while describing the bandwidth enhancement strategy. The design methodology is validated with the design of a broadband Doherty PA based on CREE 10 W packaged GaN high electron mobility transistor devices using the proposed load combiner. Measurement results show more than 45% drain efficiency at 6 dB output power back‐off (OPBO) over 400 MHz frequency range, centred around 1.95 GHz. The peak drain efficiency at saturation is better than 60% over this band of operation. At 6 dB OPBO, the maximum improvement of 18.5% in drain efficiency is achieved as compared to the balanced mode PA. Measurement with single carrier wideband code division multiple access modulated signal shows the average drain efficiency of more than 44% at 36.6 dBm average output power at center frequency of operation. The adjacent channel power ratio is better than ?45 dBc after applying digital predistortion. The circuit is realized with microstrip technology, which can be easily fabricated using conventional printed circuit processes. © 2015 Wiley Periodicals, Inc. Int J RF and Microwave CAE 25:655–674, 2015.     

基于E类功放质谱射频的电源设计与优化

现场质谱仪在野外长时间续航,要求低功耗、高工作效率、宽范围扫描电压的射频电源予以支持。为满足这些要求,设计了基于 E 类功放模型的射频电源。使用 ADS 设计π型阻抗匹配网络,通过 Multisim联合仿真,对已设计的匹配网络进行参数优化,提高工作效率。与其它射频电源相比,采用单管 E 类开关功放,在简化设计、提升效率、提高射频扫描电压方面更具优势,并能够有效提高质谱仪的质量数扫描范围,增强质谱仪器的现场检测能力,具有十分广泛的应用前景和实际意义。     

一种应用于可定位射频标签中的接收强度指示器

本文介绍了一种应用在可定位射频标签中的接收强度指示器。提出了一种低功耗、对温度、工艺变化不敏感的低功耗限幅放大器,分析了其增益误差、噪声和频率响应。分析了级联限幅放大器的级间干扰的原理,并提出了解决方法。经过流片测试,接收强度指示器实现了45dB的电压检测范围,电流消耗为1.1mA。     

基于噪声消除技术的超宽带CMOS低噪声放大器设计

为满足3.5 GHz单载波超宽带无线接收机的射频需求,设计了一种工作在3～4 GHz的超宽带低噪声放大器。电路采用差分输入的CMOS共栅级结构,利用MOS管跨导实现宽带输入匹配,利用电容交叉耦合结构和噪声消除技术降低噪声系数,同时提高电压增益。分析了该电路的设计原理和噪声系数,并在基于SMIC 0.18μm CMOS射频工艺进行了设计仿真。仿真结果表明:在3～4GHz频段内,S11和S22均小于-10 dB,S21大于14dB,带内起伏小于0.5dB,噪声系数小于3dB;1.8V电源电压下,静态功耗7.8mW。满足超宽带无线接收机技术指标。