带光输入光输出窗口的CMOS—SEED集成芯片

通过国际合作的方式成功研制出了我国首片带光输入光输出窗口的CMOS-SEED集成芯片. 带光输入光输出窗口的CMOS-SEED集成芯片是采用倒装焊的制作工艺把CMOS大规模集成电路和SEED光电子器件结合起来.制作时首先分别利用硅CMOS VLSI工艺及GaAs SEED工艺,制作硅CMOS VLSI电路及SEED列阵,再在两种芯片表面特定位置淀积焊柱,然后将两种芯片面对面精密对准、焊合,最后去除SEED背面的GaAs衬底.作为光接收和光调制器的SEED像元是有高速率、高灵敏度和低功耗,光开关速率可达10 ps量级的光电子器件,SEED像元光窗口的大小为10 μm×10 μm,间距为250 μm.SEED光窗口接收到的光信号进入CMOS电路,经多级放大,由路由控制电路选通路由后,交换到SEED光窗口驱动电路的输入端,调制抽运光源,将交换后的信号由SEED光窗口输出.CMOS电路用16个16选1开关来完成16×16 Crossbar交换矩阵的功能.我们设计完成了CMOS逻辑电路和CMOS集成电路版图,在HP公司采用0.35 μm的生产工艺投片,由Lucent公司Bell实验室提供SEED列阵并完成倒装焊工艺. 用带光输入光输出窗口的CMOS-SEED集成芯片设计制作了自由空间16×16 Crossbar光学交换模块,由二维光纤列阵接口器件及光学系统完成光信号的输入输出,实现了光信号的交换.(OD8)     

4×4纵横交换微电机械系统光开关阵列

微电机械系统(MEMS)光开关是微电机系统技术与传统光学技术相结合的新型机械式光开关。采用纵横交换网络和通断型微镜实现4×4微电机械系统光开关阵列,利用球透镜单模光纤准直器作为微电机械系统光开关阵列的输入、输出端口。运用高斯光束耦合理论对光开关阵列插入损耗(IL)进行了理论计算,并对引起插入损耗的主要因素进行了分析。对于失调容限:输入与输出光纤准直器位置失调2μm,定位角度失调0.15°,微镜非垂直反射角度失调0.15°,制作了4×4微电机械系统光开关阵列,对其各个通道的插入损耗进行了实验测试,其中最大值为2.77dB。     

Crossbar光交换网络

Crossbar网络是实现高速并行光学处理的一种最重要而有效的光交换网络结构。作为一种无阻塞网络,Crossbar网络具有简单性,易于实现控制,适合于构成光开关矩阵。总结和分析了近20多年来发展的Crossbar光交换网络,介绍了不同Crossbar光交换网络的原理、结构和性能,分析了Crossbar光交换网络的关键技术。目前光学互连网络的发展方向是实现集成大规模光互连。可以预见光学互连网络会朝着更加实用化的方向发展,并在其应用领域发挥越来越重要的作用。     

光计算中全排列无阻塞双Omega光互连网络的光学实现方法

本文分析了单个Ｏｍｅｇａ光互连网络的局限性，提出了一种全排列无阻塞双Ｏｍｅｇａ光互连网络的光学实现方法。光回路系统由Ａｒ＋３离子激光器、光束分束器、偏振组合棱镜和液晶空间光开关组成，能够实现输入信号列阵光束的并行传输和全排列无阻塞光互连。     

新型光电探测器列阵的实验研究

本文对一种适用于光互连网络的新型光电探测器件列阵进行了实验测试工作。设计了一个测试列阵器件的光互连系统,系统的时钟光点阵由二位相光栅产生,测试所需的信号光点阵由一个２×８的ＳＥＥＤ器件对时钟光进行调制产生。对一个２×８的探测器列阵进行了实验测试工作,该探测器列阵中的探测单元的工作频率可达１００Ｍｂｉｔ／ｓ。     

弧形波导开关阵列的研究

基于非线性克尔效应的自位相调制原理 ,以两模干涉的弧形波导全光开关为单元 ,设计了光强自路由的 1× 4全光交换阵列。经光束传播法数值模拟的结果表明 ,在单路输入的情况下 ,从任一输入端输入的光 ,以其自身的光强为路由信号 ,顺利实现 1× 4的输出切换 ,达到了多路全光自交换的目的     

面向片上光互连的无源H树网络设计

传统的片上电互连已无法满足多核处理系统日益 增长的通信需求,在延迟、能耗和 带宽方面更具优势的片上光互连逐渐引起关注。为了降低片上光网络(optical network-on-chip,ONoC)硬件开销和提升光网络 性能,本文提出一种基于微环谐振器的16端口无源H树光互连网络。利用宽带微环谐振器设 计4组转向光路由器,降低微环谐振器使用并完成端口选择,将信号传输到8端口接收光路由 器以及3级和4级光开关来满足信号的无争用传输。实验结果表明,在16×16阵列规模下与 Crossbar、λ-Router、GWOR、LACE、Light等无源网络结 构相比,无源光H树网络仅需使用 72个微环谐振器。网络平均插入损耗1.49 dB,与λ-Router、GWOR 、TAONoC相比分别降低 了21.5%、10.7%、59.7 %,各路径平均信噪比 为17.48 dB,与λ-Router、GWOR、Light相比分别提高了38.5%、36.0%、17.1%。     

化学镀镍在32×32非致冷红外焦平面互连中的应用

红外焦平面需要用互连技术把光敏元阵列与信号读出电路进行互连,利用化学镀的方法,在32×32非致冷红外焦平面阵列的CMOS读出电路上镀直径为6μm,高度为2μm的互连柱。测试结果表明,该技术稳定可靠,是实现接触孔互连的可行方法。     

半导体激光器列阵器件光束复合研究

文中针对半导体激光器列阵的波长复合和偏振复合技术开展了设计和实验研究。首先利用半导体材料波长易调节的特点,设计了AlGaInAs/GaAs/AlGaAs压应变量子阱结构,得到了760nm、800nm、860nm、930nm、976nm五个波长激射的半导体列阵激光器,同时设计了四个短波通滤波片参数,开展了半导体列阵激光器的多波长光束复合技术的实验研究;其次利用1/2波片和偏振复合棱镜将两束不同偏振状态的光束进行了复合,并设计了光束聚焦系统。最终实现了5个波长,10条半导体激光器列阵的光束复合,得到了196W的激光功率输出,总体效率为76%,其中,波长复合效率可以达到92.4%,输出聚焦光斑尺寸为144μm×1 330μm,聚焦光功率密度达到1.02×105W/cm2,与单条半导体激光器列阵相比,合束光的光功率密度提高了4.3倍。     

虚焦点成像实现平行光输入的PS光互连

用平行光输入２Ｎ×２Ｎ 元素阵列,采用２×２ 全息透镜阵列的虚焦点成像方式,实现了元素阵列的ＰＳ（ＰｅｒｆｅｃｔＳｈｕｆｆｌｅ,即全混洗）光互连;透镜阵列直接实现ＰＳ光互连时,成像放大率为２Ｎ,成像距离ｌＨ 与Ｎ 成线性;当在全息透镜阵列后另引入一成像透镜Ｌ时,推导的成像距离公式和系统放大率公式表明：互连的成像距离主要与成像透镜焦距有关,成像放大率主要与成像透镜焦距和全息透镜焦距之比有关。相应的实验证明了各公式的正确性。     

适于光交换模块光窗分布的16×16非等间距位相计算全息光栅

根据光交换网络中光逻辑ＦＥＴ－ＳＥＥＤ灵巧像元器件光窗分布的要求，设计制作了一种具有非等间距光点列阵的位相计算全息光栅，采用波长为０．８５μｍ的半导体激光器作泵浦光源，光点列阵数为１６×１６，组内光点间距与组间光点间距之比为１４，光强抑制比小于３％。     

自由空间二维榕树网实现方法

鉴于榕树网在自由空间光子交换网络中具有重要的应用价值,分析了榕树网的特点和4×4二维榕树网的空间拓扑结构,通过偏振光分光棱镜、微闪耀光栅阵列、平面反射镜、半反半透镜和液晶空间光调制器的集成,构建二维的榕树交换网实验模块,利用微闪耀光栅的衍射特性,控制每块微闪耀光栅的周期,以实现入射光信号不同方向的闪耀输出,最终完成二维榕树网自由空间水平和竖直方向上的交叉互连,直通则由平面镜反射实现。对二维榕树网实验模块的功能分析表明,该实验模块理论上可以完成4×4二维面阵内光信号(或数据)的排序、交换、组播、广播、矩阵变换等操作,具有交换透明、速度快、空间带宽高等特点,在全光交换和光通信中具有一定的应用。     

Optical I/O Technology for Tera-Scale Computing

This paper describes both a near term and a long term optical interconnect solution, the first based on a packaging architecture and the second based on a monolithic photonic CMOS architecture. The packaging-based optical I/O architecture implemented with 90 nm CMOS transceiver circuits, 1 × 12 VCSEL/detector arrays and polymer waveguides achieves 10 Gb/s/channel at 11 pJ/b. A simple TX pre-emphasis technique enables a potential 18 Gb/s at 9.6 pJ/b link efficiency. Analysis predicts this architecture to reach less than 1 pJ/b at the 16 nm CMOS technology node. A photonic CMOS process enables higher bandwidth and lower energy-per-bit for chip-to-chip optical I/O through integration of electro-optical polymer based modulators, silicon nitride waveguides and polycrystalline germanium (Ge) detectors into a CMOS logic process. Experimental results for the photonic CMOS ring resonator modulators and Ge detectors demonstrate performance above 20 Gb/s and analysis predicts that photonic CMOS will eventually enable energy efficiency better than 0.3 pJ/b with 16 nm CMOS. Optical interconnect technologies such as these using multi-lane communication or wavelength division multiplexing have the potential to achieve TB/s interconnect and enable platforms suitable for the tera-scale computing era.     

液晶光学传感器

利用可变光栅模液晶光学传感器设计了一种光学十字开关互联网络系统,该系统可实时地重新组合光学十字开关互联,液晶光学传感器执行强度－空间频率转换。讨论了这种互联网络系统的特性和最优化问题。     

微光电子集成灵巧象素器件

我们采用 MBE生长出大周期 Ga As/ Al Ga As多量子阱 (MQW)外延材料 ,研制了适用于倒装焊结构的自电光效应器件 (SEED)列阵 ,并与 Si CMOS电路通过倒装焊工艺集成为微光电子集成灵巧象素器件。通过对光电特性测试表明 ,器件具有良好的光探测和光调制性能。     

Optical self-routing switch using integrated laser diode opticalswitch

A 2×2 optical self-routing switch using integrated laser diode optical switches is proposed. The switch is composed of a Benes network, which can perform large-scale switching functions using less hardware than a crossbar switch. The path each data stream takes through the interconnection network is determined by the binary bits of its destination address, and self-routing is accomplished by monitoring terminal voltage changes in gain guides induced by input optical signals which are injected into a p-n junction. Concentrated control is not necessary, and large optical multistage switches can be easily constructed because complicated electrode patterns are not necessary     

640-Gb/s high-speed ATM switching system based on 0.25-μm CMOS,MCM-C, and optical WDM interconnection

A 640-Gb/s high-speed ATM switching system that is based on the technologies of advanced MCM-C, 0.25-μm CMOS, and optical wavelength-division-multiplexing (WDM) interconnection is fabricated for future broadband backbone networks. A 40-layer, 160×114 mm ceramic MCM forms the basic ATM switch module with 80-Gb/s throughput. It consists of 8 advanced 0.25-μm CMOS LSIs and 32 I/O bipolar LSIs. The MCM has a 7-layer high-speed signal line structure having 50-Ω strip lines, high-speed signal lines, and 33 power supply layers formed using 50-μm thick ceramic layers to achieve high capacity. A uniquely structured closed-loop-type liquid cooling system for the MCM is used to cope with its high power dissipation of 230 W. A three-stage ATM switch is made using the optical WDM interconnection between high-performance MCMs. For WDM interconnection, newly developed compact 10-Gb/s, 8-WDM optical transmitter and receiver modules are used. These modules are each only 80×120×20 mm and dissipate 9.65 W and 22.5 W, respectively. They have a special chassis for cooling, which contains high-performance heat-conductive plates and micro-fans. An optical WDM router based on an arrayed waveguide router is used for mesh interconnection of boards. The optical WDM interconnect has 640-Gb/s throughput and simple interconnection     

A simple 8×8 optoelectronic crossbar switch

The authors demonstrate the operation of an 8×8 optoelectronic crossbar switch consisting of integrated arrays of eight 1×8 GaAs metal-semiconductor-metal (MSM photodiodes connected in a current summing network to the input of Si bipolar transimpedance amplifiers. The MSM devices are also connected to TTL transistor-transistor logic) driven CMOS analog multiplexers which, in the `off' state, switch the detectors into an open-circuit mode. This particular combination of detectors and switching network gives a very high interchannel isolation, reduced circuit complexity, and low input noise. Data rates of 200 Mbit's and switch reconfiguration times of -100 ns are achieved. System noise is calculated and measured, and the advantages of using fully integrated GaAs crossbar switch arrays are quantitatively discussed     

Power complexity of multiplexer-based optoelectronic crossbar switches

The integration of thousands of optical input/output (I/O) devices and large electronic crossbar switching elements onto a single optoelectronic integrated circuit (IC) can place stringent power demands on the CMOS substrates. Currently, there is no sufficiently general analytic methodology for power analysis and power reduction of large-scale crossbar switching systems. An analysis of the power complexity of single-chip optoelectronic switches is presented, assuming the classic broadcast-and-select crossbar architecture. The analysis yields the distribution of power dissipation and allows for design optimization. Both unpipelined and pipelined designs are analyzed, and a technique to reduce power dissipation significantly is proposed. The design of a 5.12 Tbit single-chip optoelectronic switch using 0.18-/spl mu/m CMOS technology is illustrated. The pipelined switch design occupies < 70 mm/sup 2/ of CMOS area, and consumes <80 W of power, which compares favorably to the power required in electrical crossbar switches of equivalent capacity.