基于记忆的人工鱼认知模型

为丰富虚拟海洋环境中人工鱼的认知能力，以自然鱼的生物原理和记忆机制为理论依据，提出了一种基于记忆的人工鱼认知模型。信息在瞬时记忆、短时记忆和长时记忆3个阶段传输和存储，人工鱼通过聚焦器提取所关注的感知信息，通过决策器和短时记忆进行行为选择，将经验知识存储在长时记忆中，被短时记忆调用以优化当前决策。动画结果表明，采用此模型后人工鱼能产生记忆指导下的行为，表现出更真实更智能的生命特征。     

Long-term mapping and localization using feature stability histograms

This work proposes a system for long-term mapping and localization based on the Feature Stability Histogram (FSH) model which is an innovative feature management approach able to cope with changing environments. FSH is built using a voting schema, where re-observed features are promoted; otherwise the feature progressively decreases its corresponding FSH value. FSH is inspired by the human memory model. This model introduces concepts of Short-Term Memory (STM), which retains information long enough to use it, and Long-Term Memory (LTM), which retains information for longer periods of time. If the entries in STM are continuously rehearsed, they become part of LTM. However, this work proposes a change in the pipeline of this model, allowing any feature to be part of STM or LTM depending on the feature strength. FSH stores the stability values of local features, stable features are only used for localization and mapping. Experimental validation of the FSH model was conducted using the FastSLAM framework and a long-term dataset collected during a period of one year at different environmental conditions. The experiments carried out include qualitative and quantitative results such as: filtering out dynamic objects, increasing map accuracy, scalability, and reducing the data association effort in long-term runs.     

Some experiments with the interpretation strategy of a modular computer vision system

This paper is concerned with the general problem of computer vision. That is, given a colored input picture, design a system which segments the objects in the scene and interprets them appropriately. During the past few years, we have been engaged in the development of a modular, data-driven computer vision system to achieve this goal. The details have appeared elsewhere, so here we have primarily emphasized the mechanism for updating the hypothesized region interpretations. This is achieved by means of a relaxation labeling process which has continuous access to a scene model describing the picture under consideration.     

Synchronous dataflow architecture for network processors

Network processors are programmable, highly integrated communications circuits optimized to provide processing at high data and packet rates. The packet instruction set computer (PISC) architecture is a synchronous dataflow architecture developed for network processors. It uses a deep pipeline that contains two types of processing elements: PISC processors, which perform programmable data manipulation, and I/O processors, which provide access to shared resources such as look-up table memory, hardware accelerators, or coprocessors.     

用非线性存储方案设计SIMD计算机的一般方法

非线性存储方案能在处理单元数等于存储体数的情况下,使ＳＩＭＤ机实现多种访存模式无冲突,提高其整体性能,文中提出一种用线性存储方案设计ＳＩＭＤ 一般方法,在存储方案给定的前提下,针对有限的模板集设计出同时满足存储器访问无冲突和互联网的并行结构,首先,用布尔向量空间表示模板,并指出模板与ＬＣ置换的对应关系,在此基础上,提出设计局部地址生成逻辑和增强的间接二进制Ｎ方体网络的方法,由于板集中任意的访存方式     

Short-term and long-term memory analysis of learning using 2D and 3D educational contents

ABSTRACT

The effect of 2D and 3D educational content learning on memory has been studied using electroencephalography (EEG) brain signal. A hypothesis is set that the 3D materials are better than the 2D materials for learning and memory recall. To test the hypothesis, we proposed a classification system that will predict true or false recall for short-term memory (STM) and long-term memory (LTM) after learning by either 2D or 3D educational contents. For this purpose, EEG brain signals are recorded during learning and testing; the signals are then analysed in the time domain using different types of features in various frequency bands. The features are then fed into a support vector machine (SVM)-based classifier. The experimental results indicate that the learning and memory recall using 2D and 3D contents do not have significant differences for both the STM and the LTM.     

Dual-port RAMs simplify processor communications

Conventional memory blocks have a single address input and a single, usually bidirectional, data output. Dual-port memories have two address inputs and two data ports. These memories have been designed to facilitate the exchange of data between CPUs within a multiprocessor system. Each microprocessor can access the multiport memory and therefore read the data of another processor or leave data for another processor. There are two problems in the design of multiport memory systems. The first, and more trivial, concerns the way in which each processor supplies an address to the memory and how it accesses the memory data bus. This is not a particularly complex problem and the designer biggest worry is how to design the interface with the least number of multiplexers and buffers. Whenever a processor wishes to access the multiport memory, it takes control of the address and data bus and then accesses the memory. A more fundamental design problem is posed when two or more processors try to access the memory nearly simultaneously. Memory contention is solved by the use of an arbitration circuit that arbitrates between the contending processors, grants access to only one processor and forces the others to wait. Fortunately, it is no longer necessary for all designers to construct their own dual-port memories from discrete components, since several manufacturers now put the memory, address and data multiplexers plus arbitration circuits on chip. IDT's application note shows how its dual-port memory operates and how it is used in multiprocessor systems.     

Data cache prefetching using a global history buffer

Over the past couple of decades, trends in both microarchitecture and underlying semiconductor technology have significantly reduced microprocessor clock periods. These trends have significantly increased relative main-memory latencies as measured in processor clock cycles. To avoid large performance losses caused by long memory access delays, microprocessors rely heavily on a hierarchy of cache memories. But cache memories are not always effective, either because they are not large enough to hold a program's working set, or because memory access patterns don't exhibit behavior that matches a cache memory's demand-driven, line-structured organization. To partially overcome cache memories' limitations, we organize data cache prefetch information in a new way, a GHB (global history buffer) supports existing prefetch algorithms more effectively than conventional prefetch tables. It reduces stale table data, improving accuracy and reducing memory traffic. It contains a more complete picture of cache miss history and is smaller than conventional tables.     

A high-speed integrated services ATM/STM switch

A new, high-speed switch architecture which uses Asynchronous Transfer Mode (ATM) and Synchronous Transfer Moder (STM) to support integrated voice-data-video, multicasting, and virtual networking services is described. The switch employs autonomous processing units with local memory to store switching information and is built around a modified Banyan network with bit-parallel lines linking its node processors. The system is synchronous and time is slotted with slots organized into frames. Fixed-rate video and other real-time periodic traffic are handled via STM switching, while voice, data, datagrams, and other bursty traffic are ATM switched. Multicasting is realized by allocating dedicated STM bandwidth to real-time periodic sources and virtual ATM bandwidth to bursty sources. Virtual networking is achieved by putting an STM subnetwork into place over which authorized users communicate via ATM and/or STM. Analytic models to determine the switch's performance characteristics are developed and illustrated via examples. The results show that the switch has excellent delay vs. throughput performance for ATM traffic in the presence of STM traffic, and very low blocking-and-loss probability for STM circuit set-up requests in the presence of other traffic.     

一种高效的大数据实时性解决方案

大数据计算是物联网和云计算的研究热点之一.针对大数据中的结构化和非结构化数据,Hadoop技术在实时性要求不高的场景中应用效果较好,但在实时性要求高的场景中不能满足需求.针对这一问题,论文利用对象化并行计算提出了一种高效的实时性解决方案.对象化并行计算融合了对象化、Hadoop、内存计算等技术.在方案中,业务数据格式化成对象并分布式存储到集群计算机内存中,任务拆分成子任务通过并行计算来完成.对象化并行计算系统应用在国家电网公司电网资产质量监督管理系统中,应用效果表明该方案可大幅度提升系统性能,满足实时性需求.     

NETRA: a hierarchical and partitionable architecture for computervision systems

Computer vision is regarded as one of the most complex and computationally intensive problems. In general, a Computer Vision System (CVS) attempts to relate scene(s) in terms of model(s). A typical CVS employs algorithms from a very broad spectrum such as numerical, image processing, graph algorithms, symbolic processing, and artificial intelligence. The authors present a multiprocessor architecture, called “NETRA,” for computer vision systems. NETRA is a highly flexible architecture. The topology of NETRA is recursively defined, and hence, is easily scalable from small to large systems. It is a hierarchical architecture with a tree-type control hierarchy. Its leaf nodes consists of a cluster of processors connected with a programmable crossbar with selective broadcast capability to provide the desired flexibility. The processors in clusters can operate in SIMD-, MIMD- or Systolic-like modes. Other features of the architecture include integration of limited data-driven computation within a primarily control flow mechanism, block-level control and data flow, decentralization of memory management functions, and hierarchical load balancing and scheduling capabilities. The paper also presents a qualitative evaluation and preliminary performance results of a cluster of NETRA     

Scene analysis by integrating primitive segmentation andassociative memory

Scene analysis is a major aspect of perception and continues to challenge machine perception. This paper addresses the scene-analysis problem by integrating a primitive segmentation stage with a model of associative memory. The model is a multistage system that consists of an initial primitive segmentation stage, a multimodule associative memory, and a short-term memory (STM) layer. Primitive segmentation is performed by a locally excitatory globally inhibitory oscillator network (LEGION), which segments the input scene into multiple parts that correspond to groups of synchronous oscillations. Each segment triggers memory recall and multiple recalled patterns then interact with one another in the STM layer. The STM layer projects to the LEGION network, giving rise to memory-based grouping and segmentation. The system achieves scene analysis entirely in phase space, which provides a unifying mechanism for both bottom-up analysis and top-down analysis. The model is evaluated with a systematic set of three-dimensional (3-D) line drawing objects, which are arranged in an arbitrary fashion to compose input scenes that allow object occlusion. Memory-based organization is responsible for a significant improvement in performance. A number of issues are discussed, including input-anchored alignment, top-down organization, and the role of STM in producing context sensitivity of memory recall.     

Orthogonal multiprocessor sharing memory with an enhanced mesh for integrated image understanding

This paper proposes a new parallel architecture, which has the potential to support low-level image processing as well as intermediate and high-level vision analysis tasks efficiently. The integrated architecture consists of an SIMD mesh of processors enhanced with multiple broadcast buses, and MIMD multiprocessor with orthogonal access buses, and a two-dimensional shared memory array. Low-level image processing is performed on the mesh processor, while intermediate and high-level vision analysis is performed on the orthogonal multiprocessor. The interaction between the two levels is supported by a common shared memory. Concurrent computations and I/O are made possible by partitioning the memory into disjoint spaces so that each processor system can access a different memory space. To illustrate the power of such a two-level system, we present efficient parallel algorithms for a variety of problems from low-level image processing to high-level vision. Representative problems include matrix based computations, histogramming and key counting operations, image component labeling, pyramid computations, Hough transform, pattern clustering, and scene labeling. Through computational complexity analysis, we show that the integrated architecture meets the processing requirements of most image understanding tasks.     

面向STM的松弛存储一致性算法

软件事务性内存(STM)提供同步手段,让多线程程序高效并发执行。如果两个事务访问了同一个共享数据且至少一个事务进行了修改操作,则称发生了冲突。检测冲突后,一般选择一个事务终止。当前的STM实现都基于严格的线性一致性(Linearizability)语义模型,实现简单。但是,基于该语义会导致很多本来可以完成提交的事务失败,降低了系统效率。把因果一致性模型应用于STM,可以在保证程序准确性条件下取得较好的实际性能。实验数据表明,该算法简单高效,明显减少了冲突数目。     

A net-structure learning system for pattern description

This paper discusses a computer program that recognizes and describes two-dimensional patterns composed of subpatterns. The program also recognizes all patterns in a scene consisting of several patterns.

Patterns are stored in a learned hierarchical, net-structure memory. Weighted links between memory nodes represent subpattern/pattern relationships. Both short term and permanent memories are used.

Pattern recognition is accomplished with a serial heuristic search algorithm, which attempts to search memory and compute input properties efficiently. Without special processing, the program can be asked to look for all occurrences of a specified pattern in a scene.     

A flexibility coupled hypercube multiprocessor for high level vision

In general, message passing multiprocessors suffer from communication overhead between processors and shared memory multiprocessors suffer from memory contention. Also, in computer vision tasks, data I/O overhead limits performance. In particular, high level vision tasks, which are complex and require nondeterministic communication, are strongly affected by these disadvantages. This paper proposes a flexibly (tightly/loosely) coupled hypercube multiprocessor (FCHM) for high level vision to alleviate these problems. A variable address space memory scheme in which a set of adjacent memory modules can be merged into a shared memory module by a dynamically partitionable hypercube topology is proposed. The architecture is quantitatively analyzed using computational models and simulated on the Intel’s Personal SuperComputer (iPSC/I), a hypercube multiprocessor. A parallel algorithm for exhaustive search is simulated on FCHM using the iPSC/I showing significant performance improvements over that of the iPSC/I. This research was supported in part by IBM corporation.     

The design and implementation of a distributed image understanding system

Computer vision is concerned with extracting information about a scene by analyzing images of that scene. Performing any computer vision task requires an enormous amount of computation. Exploiting parallelism appears to be a promising way to improve the performance of computer vision systems. Past work in this area has focused on applying parallel processing techniques to image-operator level parallelism. In this article, we discuss the parallelism of computer vision in the control level and present a distributed image understanding system (DIUS).In DIUS, control-level parallelism is exploited by a dynamic scheduler. Furthermore, two levels of rules are used in the control mechanism. Meta-rules are concerned mainly with which strategy should be driven and the execution sequence of the system; control rules determine which task needs to be done next. A prototype system has been implemented within a parallel programming environment, Strand, which provides various virtual architectures mapping to either a shared-memory machine, Sequent, or to the Sun network.     

RTS: A system to simulate the real time cost behaviour of parallel computations

In this paper, we present a software tool, RTS (real time simulator), that analyses the time cost behaviour of parallel computations through simulation. It is assumed in RTS that the computer system which supports the executions of parallel computations has a limited number of processors all processors have the same speed and they communicate with each other through a shared memory. In RTS, the time cost of a parallel computation is defined as a function of the input, the algorithm, the data structure, the processor speed, the number of processors, the processor power allocation, the communication and the execution environment. How RTS models the time cost is first discussed in the paper. In the model, a locking technique is used to manipulate the access to the shared memory, processing power is equally allocated among all the operations that are currently being performed in parallel in the computer system, and the number of operations in the execution environment of a parallel computation changes from time to time. How RTS works and how the simulation is used to do time cost analysis are also discussed.     

Parallelism versus Memory Allocation in Pipelined Router Forwarding Engines

A crucial problem that needs to be solved is the allocation of memory to processors in a pipeline. Ideally, the processor memories should be totally separate (i.e., one-port memories) in order to minimize contention; however, this minimizes memory sharing. Idealized sharing occurs by using a single shared memory for all processors but this maximizes contention. Instead, in this paper we show that perfect memory sharing of shared memory can be achieved with a collection of two-port memories, as long as the number of processors is less than the number of memories. We show that the problem of allocation is NP-complete in general, but has a fast approximation algorithm that comes within a factor of asymptotically. The proof utilizes a new bin packing model, which is interesting in its own right. Further, for important special cases that arise in practice a more sophisticated modification of this approximation algorithm is in fact optimal. We also discuss the online memory allocation problem and present fast online algorithms that provide good memory utilization while allowing fast updates.