A simple efficient model of parasitic capacitances of deep-submicron LDD MOSFETs

Estimation of parasitic capacitances in a MOSFET device is very important, notably in mixed circuit simulation. For deep-submicron LDD MOSFETs, the extrinsic capacitance (overlap plus fringing capacitances) is a growing fraction of the total gate capacitance. A correct estimation of the extrinsic capacitance requires an accurate modeling of each of its constituents. However the major existing models do not correctly predict the overlap capacitance and the inner fringing capacitance (which is often ignored). In this paper a new approach to model the overlap C_ov and fringing C_if+C_of capacitances in the zero-current regime is presented. The bias dependence of the extrinsic capacitance is investigated and a detailed study of the influence of the LDD doping dose is also undertaken. Then, an efficient, simple and continuous model describing the evolution of overlap and fringing capacitances in all operating regimes of a n-channel LDD MOSFET is developed. Finally this model is incorporated in an existing compact-model for circuit simulation. It is shown that this new model leads to excellent results in comparison with full 2D numerical device simulation.     

Modeling of cylindrical surrounding gate MOSFETs including the fringing field effects

A physically based analytical model for surface potential and threshold voltage including the fringing gate capacitances in cylindrical surround gate(CSG) MOSFETs has been developed.Based on this a subthreshold drain current model has also been derived.This model first computes the charge induced in the drain/source region due to the fringing capacitances and considers an effective charge distribution in the cylindrically extended source/drain region for the development of a simple and compact model.The fringing gate capacitances taken into account are outer fringe capacitance,inner fringe capacitance,overlap capacitance,and sidewall capacitance.The model has been verified with the data extracted from 3D TCAD simulations of CSG MOSFETs and was found to be working satisfactorily.     

Cut-off frequency and transit time analysis in short geometry polysilicon thin-film transistors

An accurate model for the drain characteristics, transconductance, cut-off frequency and transit time of a short geometry polysilicon thin film transistor (poly-Si TFT) is presented. An accurate threshold voltage and field dependent mobility are the key parameters in determining the above-threshold characteristics. The current-voltage characteristics of the device show an excellent agreement with experimental results. The transconductance for both linear and saturation regions is calculated and its variation with channel length, drain and gate voltages is studied. The total gate capacitance including the geometric capacitance and the fringing capacitance is also evaluated and simple closed form expressions for the cut-off frequency and transit time are obtained. A high cut-off frequency is achieved, which is important in realizing the device for millimetre and microwave frequency applications.     

A capacitance method to determine channel lengths for conventional and LDD MOSFET's

A simple method for determining the channel length and in situ gate-oxide thickness of MOSFETs is described. The method is based on the linear relationship between the intrinsic gate capacitance and effective channel length. Measurements from two gate biases on devices of different channel lengths are sufficient to obtain a full characterization. In contrast to the channel-resistance method, the accuracy of the capacitance method is independent of the source-drain and contact series resistance. It can, therefore, be used for conventional as well as lightly-doped drain (LDD) devices. Channel length and gate-oxide thickness determined by this method are given for conventional and LDD MOSFET's. For conventional MOSFET's, the new method agrees with the traditional effective length measurements to better than 0.1 µm.     

Effects of source/drain implants on short-channel MOSFET I-V andC-V characteristics

The effects of source/drain implants on n-channel MOSFET I-V and C-V characteristics are measured and compared for the lightly doped drain (LDD) and the large-angle-tilt implanted drain (LATID) devices. We show that despite substantial improvement in hot-carrier reliability for LATID devices, the LATID design might have a limited range of application for short-channel MOSFETs. This is because as a result of enhanced V_TH roll-off and increased overlap capacitance for the LATID devices compared to LDD devices, the device/circuit performance degrades. The degradation of performance becomes more pronounced as device length is reduced. These results are confirmed by both experimental data and 2-dimensional numerical simulations     

Annealing effects of carbon in n-channel LDD MOSFETs

The degradation pattern of lightly doped drain (LDD) structure MOSFETs with carbon doping under various steps has been studied. For a carbon-doped LDD device with first- and second-level metal and passivation layer but without any final anneal, the results show that a significant reduction in the shifts of the threshold voltage of MOSFETs with time can be achieved. The authors demonstrate that threshold voltage degradation has been reduced for carbon-doped devices and that a final anneal does not improve the hot-electron degradation of these devices. These results imply the existence of neutral electron traps in the gate oxides of MOSFETs     

A new technique to extract channel mobility in submicron MOSFETsusing inversion charge slope obtained from measured S-parameters

We present a novel method to extract the effective channel mobility directly from measured S-parameters in submicron MOSFETs. This method is based on the slope extraction of the total gate charge versus mask gate length from measured S-parameters. Unlike conventional approaches, the use of a very long channel test device or the extraction of the parasitic capacitance and effective channel length are not required to extract the mobility in short-channel LDD devices, thus making the new method more accurate and simpler. The validity of the method is demonstrated by comparing the result with those using a previously reported method     

High-performance 0.10-μm CMOS devices operating at roomtemperature

The authors have fabricated 0.10-μm gate-length CMOS devices that operate with high speed at room temperature. Electron-beam lithography was used to define 0.10-μm polysilicon gate patterns. Surface-channel type p- and n-channel MOSFETs were fabricated using an LDD structure combined with a self-aligned TiSi₂ process. Channel doping was optimized so as to suppress punchthrough as well as to realize high transconductance and low drain junction capacitance. The fabricated 0.10-μm CMOS devices have exhibited high transconductance as well as a well-suppressed band-to-band tunneling current, although the short-channel effect occurred somewhat. The operation of a 0.10-μm gate-length CMOS ring oscillator has been demonstrated. The operation speed was 27.7 ps/gate for 2.5 V at room temperature, which is the fastest CMOS switching ever reported     

Threshold voltage model for deep-submicrometer MOSFETs

The threshold voltage, V_th, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep-submicrometer range has been investigated. Experimental data show that in the very-short-channel-length range, the previously reported exponential dependence on channel length and the linear dependence on drain voltage no longer hold true. A simple quasi-two-dimensional model is used, taking into account the effects of gate oxide thickness, source/drain junction depth, and channel doping, to describe the accelerated V_th on channel length due to their lower drain-substrate junction built-in potentials. LDD devices also show less V_th dependence on drain voltage because the LDD region reduces the effective drain voltage. Based on consideration of the short-channel effects, the minimum acceptable length is determined     

Hot-electron-induced degradation of conventional, minimum overlap,LDD and DDD N-channel MOSFETs

Substrate current characteristics of conventional minimum overlap, DDD (double-diffused drain), and LDD (lightly doped drain) n-channel MOSFETs with various LDD n^- doses have been studied. Threshold voltage shift, transconductance degradation, and change of substrate current for these devices after stressing were also investigated. The minimum gate/drain overlap devices had the highest substrate current and the worst hot-electron-induced degradation. The amount of gate-to-n⁺ drain overlap in LDD devices was an important factor for hot-electron effects, especially for devices with low LDD n^- doses. The injection of hot holes into gate oxide in these devices at small stressed gate voltages was observed and was clearly reflected in the change of substrate current. The device degradation of low-doped LDD n-channel MOSFETs induced by AC stress was rather severe     

A new LDD structure: total overlap with polysilicon spacer (TOPS)

The total overlap with polysilicon spacer (TOPS) structure, a fully overlapped lightly doped drain (LDD) structure, is discussed. The TOPS structure achieves full gate overlap of the lightly doped region with simple processing. TOPS devices have demonstrated superior performance and reliability compared to oxide-spacer LDD devices, with an order of magnitude advantage in current degradation under stress for the same initial current drive or 30% more drive for the same amount of degradation. TOPS devices also show a much smaller sensitivity to n^- dose variation than LDD devices. Gate-induced drain leakage is reported for the first time in fully overlapped LDD devices     

Simple gate-to-drain overlapped MOSFETs using poly spacers for highimmunity to channel hot-electron degradation

Short n-channel MOSFETs with permanent poly spacers over the lightly doped drain (LDD) region are demonstrated to be effective in increasing the resistance to channel hot-electron-induced degradation. The hot-electron lifetime of the poly-spacer devices is two to three orders of magnitude longer than that of a conventional oxide-spacer device. This improvement is entirely due to the reduced electron trapping in the gate oxide under the sidewall spacer. The disadvantages of the poly-spacer devices, higher gate-to-drain overlap capacitance and weaker gate oxide integrity, can both be minimized to within 20% of those of the oxide-spacer device by a short oxidation before the formation of the poly spacer     

A quasi-3D analytical threshold voltage model of small geometry MOSFETs

Numerical 2D and 3D models of MOSFETs, which have been developed so far, are accurate but take enormous computer time and memory for their implementation. It restricts their use only to the design and development of submicron devices. A computationally faster, analytical quasi-3D model for the threshold voltage of small geometry MOSFETs, which should be useful for VLSI circuit simulation, has been presented in this paper. The model is based on a rigorous 2D analytical model. An equivalence between the analytical 2D model and the Yau's charge sharing model has been established, and the same has been utilized to incorporate the narrow width effect. The important features of the present work are: (1) realistic channel implantation profiles for nMOSFETs have been used in developing the 2D model; (ii) the effect of birds' beaks on the lateral confinement of charges in the channels of oxide isolated MOSFETs has been considered in a simple manner; and (iii) the fringing of electric field near the edges of channels (widths) has also been considered empirically. The simulated values of the threshold voltages exhibiting 2D and 3D effects compare well with those obtained using a numerical 3D simulator (MICROMOS) and with available experimental data. The model is also capable of predicting the inverse narrow width effect observed in MOSFETs with fully recessed field oxide.     

An analytic saturation model for drain and substrate currents ofconventional and LDD MOSFETs

An analytic saturation model for conventional and lightly doped drain (LDD) MOSFETs is developed by using the pseudo-two-dimensional approximation in the channel and drain regions to obtain both the channel length modulation factor and the maximum electric field. Using the established I-V model in the linear region, the drain currents of conventional and LDD MOSFETs can be explicitly calculated. The substrate currents of conventional/LDD MOSFETs are calculated by using an existing simplified substrate current formula and the maximum electric field model. It is shown that the accuracy of the maximum electric field is acceptable for calculating the substrate currents of conventional/LDD MOSFETs. The parameters used in the model can be determined by the existing extraction methods and the optimization technique. The saturation model is shown to be valid for a wide range of channel lengths and bias conditions     

Simple extraction method for mobility parameters in Si-MOSFETs at 77 K

A simple technique for the extraction of low field mobility mu /sub 0/ and linear and quadratic coefficients alpha and beta in Si-MOSFETs at 77 K is presented. From measurement of the drain currents and transconductances of the devices one can determine the parameters. The method is applied to long channel and short channel LDD MOSFETs.<>     

High-power-density 4H-SiC RF MOSFETs

The authors have made the first 4H-SiC RF power MOSFETs with cutoff frequency up to 12 GHz, delivering RF power of 1.9 W/mm at 3 GHz. The transistors withstand 200 V drain voltage, are normally off, and show no gate lag, which is often encountered in SiC MESFETs. The measured devices have a single drain finger and a double gate finger, and a total gate width of 0.8 mm. To their knowledge, this is the first time that power densities above 1 W/mm at 3 GHz are reported for SiC MOSFETs.     

Frequency dependence of the unilateral gain in bipolar transistors

The frequency dependence of the current gain and the unilateral gain in advanced bipolar transistors is analyzed. A GaAlAs/GaAs heterostructure bipolar transistor (HBT) is used as an example to show that the extrinsic parasitics still dominate the gain rolloff. Transit-time effects, even though they are a significant component of the time constants that determine the f_T and f _max of transistors, do not cause a change in the rolloff of unilateral gain with a frequency from 6 to 12 dB/octave in these advanced devices. Devices with very large transit times, and hence low f_T and f_max may, however, exhibit the rolloff change if designed to have a very low fringing capacitance and other parasitics     

CAD公式分析切角贴片-双模滤波器和圆极化天线

切角贴片在微带电路中得到了大量的应用。文中给出了分析切角贴片的CAD公式。该CAD公式根据切角贴片的工作机理 ,将边缘场看成延长效应 ,将切角处理为电容加载 ,保证了腔模模型的完整性 ,从而得到分析切角贴片的CAD公式。CAD公式避免了在贴片表面和边缘做矩量法 ,以及矩阵求逆 ,因而计算时间可以忽略不计。与全波分析方法 (IE3D)相比 ,该CAD公式可以得到较为准确的结果 (h/λ0 <0 .0 8,谐振频率误差 <3% )。该公式可用于分析微带双模滤波器和圆极化天线     

Estimation of fringing capacitance of electrodes on s.i. GaAs substrate

Capacitances of the electrodes with various patterns on a semi-insulating GaAs substrate were measured and analysed to estimate parasitic capacitances of GaAs devices. The fringing capacitance was a larger fraction of the total capacitance for electrodes with area less than 200 ?m square. A simple and practical expression for the capacitance was derived from the experimental results.     

Performance and reliability evaluation of high dielectric LDDspacer on deep sub-micrometer LDD MOSFET

High dielectric LDD spacer has been proposed to achieve both reliability and performance improvement on the scaled LDD MOSFET's. However, the sidewall polyoxide and spacer bottom oxide required for process reliability issue will adversely limit the DC performance improvement gained by using high dielectric LDD spacer. AC performance is evaluated by the transconductance cutoff frequency determined by the transconductance, G_M and total gate capacitance, C_GG . For deep-submicron MOSFET's, the dominance of gate to source/drain overlap capacitance in C_GG has significant impact on the AC performance. The increase of C_GG due to the enhanced fringe field from high dielectric LDD spacer significantly dominates over the increase of transconductance, and then deteriorates the AC performance. As the reliability issue is concerned, the key doping profile, N^- source/drain lateral diffusion profile was obtained from the two dimensional process simulator SUPREM-IV corresponding to wide range of LDD N^- doses. The optimized N ^- dose designed for hot carrier reliability issue (under V _GS-V_T=0.5 V_DS operation) is located around 2×10¹³ cm^-2 for both conventional LDD (denoted as OLDD in this paper) and high dielectric LDD (HLDD) devices. However, the improvement achieved by using HLDD instead of OLDD devices is then turned out to be insignificant under this optimized N^- dose condition