基于优化FDTI算法的多芯片去耦电容快速选择

针对电源分配网络中多芯片的去耦电容器的快速选取这一问题，提出一种新的去耦电容器快速选取方案，使得PDN的阻抗既能低于目标阻抗，又不至于过度设计。文中采用优化的频域目标阻抗法，针对多芯片的电源分配网络模型，给出去耦电容器的种类和数目的选取方案。通过GUI界面的仿真，发现该算法能够有效地适用于多芯片的情况，具有较大的工程应用价值。     

基于可分解的多目标进化算法的PDN阻抗的优化

频率的电源分配网络设计是一个多目标优化问题。应用多目标进化算法优化电源分配网络的阻抗,其中去耦电容的个数和种类成为了PDN中两个需要优化的目标函数,这使得PDN中的输入阻抗,在截止频率内小于目标阻抗以达到设计要求。为解决这个问题,应用可分解的多目标进化算法,同时优化这两个目标,以获得期望的Pareto Front(PF)。实验证明,该设计方法易于实现,且效果良好、稳定性强。优化的PDN的输入阻抗满足设计要求并且优化的去耦电容的个数和种类逼近PF。     

基于自适应遗传算法的去耦电容器自动选择

针对在电源分配网络设计过程中,人工选择去耦电容器个数会导致反复设计的问题,提出了基于自适应遗传算法的去耦电容器自动选择的方法。该方法模拟达尔文生物进化论的自然选择过程,在满足目标阻抗的同时,选择出使用去耦电容器总个数最少的方案,以实现自动选择的目的。仿真结果与PCB全波仿真软件结果对比表明,该方法能够满足工程应用的要求,并已被某大型IT企业所采用。     

高速PCB同步开关噪声仿真抑制分析

从电源完整性(PI)的角度分析了抑制同步开关噪声(SSN)的有效途径——降低芯片供电电源的输入阻抗。使用目标阻抗法,并对给定最大去耦电容容值种类的条件下,使用频域对数法进行电源地分配网络(PDN)的优化。以XX电子控制器的PCB板为例,使用Ansoft SIwave及Ansoft Designer仿真软件,对复杂高速PCB板PDN进行优化设计,并通过时域观察优化前后SSN的抑制情况。仿真结果表明:通过优化PDN能够有效降低SSN。     

本征模在电源完整性分析中的应用

针对日益复杂的多层基板电源完整性问题,提出了一种基于本征模分析所需频段内PDN(Power Delivery Network)阻抗大于目标阻抗的仿真设计方法。基于13层的AlN基板,利用AnsysSiwave电磁仿真软件提取电源分配网络的Z阻抗曲线,观察响应上是否有谐振点。针对谐振点,利用本征模观察谐振频点的谐振分布,确认最大谐振位置。通过在最大谐振位置上加载去耦电容的方式将谐振频点移至高频,以此使电源Z阻抗满足目标阻抗需求。     

多负载电源分配网络的去耦分析

传统的利用单端口自阻抗指导电源分配网络设计方法(FDTI),主要适用于一个电源/地平面只有一个负载芯片的情况,对现阶段多负载芯片的复杂电源分配网络已不再适用。文中通过全波仿真软件SI-wave提取每个负载芯片的多输入叠加阻抗,用以指导多负载芯片复杂电源分配网络的设计。利用矢量拟合算法拟合多输入叠加阻抗曲线的有理函数,将该有理函数导入相关电容器选择算法中得到每个芯片的去耦方案。实验结果表明,将选出的去耦电容添加到电源/地平面后,芯片电源端口处的噪声在容许的5%范围内。     

一种多芯片多输入PDN分布式建模及去耦方法

现阶段比较成熟的电源配送网络(PDN)分析方法多是针对单芯片单电源端口进行，无法满足高速系统多电源轨道的需求。文中通过对N端口网络的理论推导，分析了多电源端口PDN阻抗增加的原理，引入多输入阻抗的概念，用以精确捕捉PDN电流分布特性，进而提出了一种适用于多芯片多输入PDN的分布式建模方法，并给出复杂PDN整板去耦方案。实验例证表明，给出的去耦方案能有效地将所有芯片的多输入阻抗降低到目标阻抗之下，满足系统5%噪声容限范围要求。     

基于多输入阻抗的电源分配网络研究

通过多输入阻抗准确描述当代高速平面电源分配网络(PDN).该阻抗能够同时探查多个激励源输入及准确估量其他端口对PDN的影响.多输入阻抗是一种新颖的输入阻抗,它有两种表现形式:多输入自阻抗和多输入叠加阻抗.前者用于描述同一IC内各个电源端口之间的影响,后者用于描述不同IC之间的影响.经时频域仿真,该多输入阻抗能同时精确地...     

基于自谐振频率电容器种类的选择算法

为使PDN阻抗曲线能在一个较宽的频率范围内不超过目标阻抗曲线,对去耦电容器种类的选择至关重要。因此,提出了基于自谐振频率电容器种类的选择算法,该算法已经用于工程实际中,效果理想。     

2020 IEEE EMC & SIPI虚拟会议——提名文章(七)

Genetic Algorithm PDN Optimization Based on Minimum Number of Decoupling Capacitors Applied to Arbitrary Target Impedance摘要:当前功率分配网络(PDN)的设计特点是精确放置去耦电容,并使其数量最小化,以节约成本。本文提出了一种优化算法,逐个放置去耦电容,并迭代评估每个PDN方案的成本函数,只要输入阻抗满足目标阻抗要求就可以确定最小的去耦电容数量。该算法基于遗传算法,并针对PDN设计的具体应用进行了相应的调整。     

Modeling and Measurement of Interlevel Electromagnetic Coupling and Fringing Effect in a Hierarchical Power Distribution Network Using Segmentation Method With Resonant Cavity Model

A hierarchical power distribution network (PDN) consists of chip, package, and printed circuit board (PCB) level PDNs, as well as various structures such as via, ball, and wire bond interconnections, which connect the different level PDNs. When estimating the simultaneous switching noise (SSN) generation and evaluating PDN designs, PDN impedance calculation is an efficient criterion. In this paper, we introduce two new kinds of modeling approaches that are exceptionally suited to improving the accuracy of the PDN impedance estimation, especially for hierarchical PDN. First, we propose a modeling procedure to add an interlevel electromagnetic coupling effect between PDNs of different levels, based on the resonant cavity model and segmentation method. In order to effectively consider the interlevel electromagnetic coupling effect, we introduce a new concept of interlevel PDN, which is, for example, composed of a metal plate in the package-level PDN and a metal plate in the PCB-level PDN. Next, we present a modeling procedure to include the fringing field effect at the edge of small-size PDN structure, which causes a considerable shift of cavity resonance frequencies in the PDN impedance profile. In order to verify the proposed modeling approaches, we have fabricated a series of test vehicles by combining two package-level PDN designs with a PCB-level PDN design. Finally, we have successfully validated the proposed modeling approaches with a series of frequency-domain measurements in a frequency range up to 5 GHz.      

Power/Ground Network Optimization Considering Decap Leakage Currents

In this brief, the authors take a first look at the leakage effects of decaps in power/ground (P/G) grid optimization. Through the use of an approximate leakage current model, it is revealed that simple usage of the leakage model in traditional optimization methods cannot help in reducing noises on P/G grids, and it even hurts power consumption due to overadded decaps. Therefore, it is necessary to develop an efficient method to budget decaps when leakage effect is considered. Here, a new two-stage approach to solve this problem is proposed. Experimental results demonstrate the effectiveness of our new method     

Design and Implementation of Active Decoupling Capacitor Circuits for Power Supply Regulation in Digital ICs

Control of on-chip power supply noise has become a major challenge for continuous scaling of CMOS technology. Conventional passive decoupling capacitors (decaps) exhibit significant area and leakage penalties. To improve the efficiency of power supply regulation, this paper proposes a distributed active decap circuit for use in digital integrated circuits (ICs). The proposed design uses an operational amplifier to boost the performance of conventional decaps. Simulations proved its enhanced decoupling effect in comparison with passive decaps. The proposed active decap also shows advantages in providing additional damping to the on-chip resonant noise. To verify the performance from the proposed circuit, a 0.18-$mu$ m test chip with on-chip noise generators and sensors has been fabricated. Measurements show a 4-11$times$ boost in decap value over conventional passive decaps for frequencies up to 1 GHz with a total area saving of 40%. Local supply noise distribution and decap gating capability were also examined from the test chip.      

Analyze and Design High-Speed Power Delivery Networks Using New Multiinput Impedances in Printed Circuit Boards

In this paper, a new input impedance, the multiinput impedance, which includes all information of the full impedance matrix, is proposed to accurately analyze and design planar power delivery networks (PDNs) in high-speed printed circuit boards and packages. The multiinput impedance includes all of the potential impacts of the other operating active power ports in both low and high frequencies. A systematical power-delivery-network analysis and design method using the multiinput impedance is developed. The global and local characteristics of the decoupled PDN are well demonstrated by the multiinput impedance, which make the analysis and design of the modern decoupled PDNs more accurate and reliable. Numerical and measured results show that the proposed multiinput impedance can characterize both the global and local characteristics of the planar PDNs with high accuracy.      

A high-frequency nonquasi-static analytical model including gate leakage effects for on-chip decoupling capacitors

This paper presents a compact model for on-chip decoupling capacitors (decaps) including gate-oxide leakage. The model makes use of only four parameters, namely, channel resistance, gate-oxide capacitance, and two parameters to quantify gate-oxide leakage, to predict the static and dynamic response of decaps. Quality indices have been defined to enable development of decap design guidelines and evaluation of performance of such capacitors. The model shows how the gate leakage and longer channel lengths severely affect the performance of on-chip decaps for both low and high frequencies. The model also shows that lumped models of decaps at high frequencies fail and have to be substituted by a distributed model. Application of the model uncovers tradeoffs for thin- and thick-oxide capacitors in an available 90-nm CMOS technology. For a general-purpose technology, a reference capacitance value has been realized using decaps with a discrete width and length. Our model predicts that thick-oxide n-channel (p-channel) capacitors require /spl sim/3.37x (/spl sim/3.31x) more silicon area and /spl sim/1.70x (/spl sim/1.17x) degraded time response as compared to their thin-oxide versions. The time response is even more degraded (/spl prop/L/sup 2/) when longer channel decaps are used. This paper contributes by defining performance benchmarks for decaps.     

Modeling, analysis and design of resonant free power distribution network for modern microprocessor systems

This paper presents design-oriented analysis of the power distribution network (PDN) for high performance microprocessor systems to realize the resonant free, close to flat output impedance magnitude over a wide frequency range. Based on the frequency domain analysis, closed form design equations and parametric curves relating the system parameters are derived. A systematic method of estimating the optimum parameters of the decoupling capacitors used in a single or multistage PDN is described to realize the output impedance of specified magnitude for the noise-free, and critically damped voltage at the microprocessor core. The design examples and simulation results are discussed to demonstrate the application of the design equations and parametric curves.