A PWM analog memory programming circuit for floating-gate MOSFETswith 75-μs programming time and 11-bit updating resolution

This paper describes a programming circuit for analog memory using pulsewidth modulation (PWM) signals and the circuit performance obtained from measurements using a floating-gate EEPROM device. This programming circuit attains both high programming speed and high precision. We fabricated the programming circuit using standard 0.6-μm CMOS technology and constructed an analog memory using the programming circuit and a floating-gate MOSFET. The measurement results indicate that the analog memory attains a programming time of 75 μs, an updating resolution of 11 bit, and a memory setting precision of 6.5 bit. This programming circuit can be used for intelligent information processing hardware such as self-learning VLSI neural networks as well as multilevel flash memory     

A PWM signal processing core circuit based on a switched currentintegration technique

A highly functional circuit for pulse width modulation (PWM) signal processing is proposed as a core of the A-D merged circuit architecture for time-domain information processing. The core circuit employs a switched-current integration technique as its computing architecture and functions as a linear arithmetic operator, a memory, and also a delaying device of PWM signals. A 0.8-μm CMOS test chip includes 110 transistors plus two capacitors and performs parallel additions and multiplications at the accuracy of 1.2 ns. A cumulative property of the technique allows the circuit to serve as a low-power accumulator that consumes 23% of the energy of the full digital 7-b accumulator. A PWM multiply-accumulate unit and a nonlinear operation unit are also proposed to extend functionality of the circuit. Since the PWM signal carries multibit data in a binary amplitude pulse, these circuits can be favorably applicable to low-voltage and low-power designs in the deep submicrometer era     

An Efficient Digital VLSI Implementation of Gaussian Mixture Models-Based Classifier

Gaussian mixture models (GMM)-based classifiers have shown increased attention in many pattern recognition applications. Improved performances have been demonstrated in many applications, but using such classifiers can require large storage and complex processing units due to exponential calculations and a large number of coefficients involved. This poses a serious problem for portable real-time pattern recognition applications. In this paper, first the performance of GMM and its hardware complexity are analyzed and compared with a number of benchmark algorithms. Next, an efficient digital hardware implementation is proposed. A number of design strategies are proposed in order to achieve the best possible tradeoffs between circuit complexity and real-time processing. First, a serial-parallel vector-matrix multiplier combined with an efficient pipelining technique is used. A novel exponential calculation circuit based on a linear piecewise approximation is proposed to reduce hardware complexity. The precision requirement of the GMM parameters in our classifier are also studied for various classification problems. The proposed hardware implementation features programmability and flexibility offering the possibility to use the proposed architecture for different applications with different topologies and precision requirements. To validate the proposed approach, a prototype was implemented in 0.25-mum CMOS technology and its operation was successfully tested for gas identification application     

Tiny-scale “stealth” current sensor to probe power semiconductor device failure

“Stealth” electric current probing technique for power electronics circuits, power device modules and chips makes it possible to measure electric current without any change or disassembling the circuit and the chip connection for the measurement. The technique consists of a tiny-scale magnetic-field coil, a high speed analog amplifier and a digitizer with numerical data processing. This technique can be applied to a single bonding wire current measurement inside IGBT modules, chip scale current redistribution measurement and current measurement for surface mount devices. The “stealth” current measurement can be utilized in the failure mechanism understanding of power devices including IGBT short circuit destruction.     

低失配CMOS差分放大器的后端版图设计研究

器件尺寸的缩小提高了晶体管的原始速度,但是集成电路不同模块间有害的相互干扰和版图的非理想性都限制了系统的工作速度和精度。理想的差分放大器电路参数是完全对称的,但实际电路中,由于制造工艺每道工序的不确定性,标称相同的器件都存在有限的不匹配。本文在设计差分电路的版图时通过讨论制造工艺和版图结构对电路性能的影响,设计了失配较小,寄生效应小的单管版图结构,并在全局布局时充分考虑了对称性对电路性能的影响得到了比较理想的差分放大器版图。     

A baseband processor for IS-54 cellular telephony

This paper describes the design of a baseband processor for IS-54 North American cellular telephony standard. The effect of diverse circuit impairments on the error vector in digital mode and on the parasitic amplitude modulation in analog mode are analyzed. An analog offset compensation scheme, which takes advantage of the TDMA operation, is presented. The device incorporates a Manchester data decoder for data transmission in analog mode. The messages can be sent via two interfaces to the DSP or μ-processor. The architecture of the digital signal processing chain is discussed. The device is fabricated in a 0.9 μ CMOS technology with an area of 40 mm²     

STUDIES ON PROGRAMMING FEATURES AND METHODS OF FLOATING GATE MOSFET AS ANALOG MEMORY FOR SYNAPTIC WEIGHTS IN NEURAL NETWORKS

The features of the floating gate devices as analog memory have been investigatedexperimentally.Programming properties of the devices,compatibility and endurance of program-ming,and programming methods are presented in this paper.The results illustrate that thedevice can be used to store the analog weights for the neural networks,and the method that thestored value is adjusted continuously to approach to a given analog values is a rather practicalmethod for storing weights of neural networks.     

Integrating Multiple Resistive Memory Devices on a Single Carbon Nanotube

Nano‐objects would be of great interest for the development of new types of electronic circuits if one could combine their nanometer scale with original functionalities beyond the conventional transistor action. However, the associated circuit architectures will have to handle the increasing variability and defect rate intrinsic to the nanoscale. In this context, there is a very fast growing interest for memory devices, and in particular resistive memory devices, used as building blocks in reconfigurable circuits tolerant to defects and variability. It was recently shown that optically gated carbon nanotube field effect transistors (OG‐CNTFETs) based on large assemblies of nanotubes covered by an organic photoconductive thin film can be operated as programmable resistors and thus used as artificial synapses in circuits with function‐learning capabilities. Here, the potential of such approach is evaluated in terms of scalability by integrating and addressing several individually programmable resistances on a single carbon nanotube. In addition, the charge storage mechanism can be controlled at a length scale smaller than the device length allowing to also program the direction in which the current flows. It thus demonstrates that a single nanotube section can combine all‐in‐one the properties of an analog resistive memory and of a rectifying diode with tunable polarity.     

A Differential Architecture for an Online Analog Viterbi Decoder

A differential architecture of an analog Viterbi decoder is presented. Analog processing enables the analog-digital converter to be excluded from the decoder realization. Moreover, high-speed operation can be achieved via differential processing. We describe the differential operation, together with the resulting decoder structure. The differential architecture enables the trace-back memory to be excluded and makes online decoding after initial transitional stages possible. We analyze the performance of the differential analog decoder by including analog circuit nonidealities in the system-level model. The decoder obeys a nonlinear transfer function, and the monotonical growth of path metrics is avoided by scaling and subtraction of the global minimum. The resulting differential analog decoder performance is compared with the performance of a 3-bit soft-decision digital Viterbi decoder. The simulations are performed for a (2,1,7) convolutional code.     

Projected Mushroom Type Phase-Change Memory

Phase-change memory devices have found applications in in-memory computing where the physical attributes of these devices are exploited to compute in places without the need to shuttle data between memory and processing units. However, nonidealities such as temporal variations in the electrical resistance have a detrimental impact on the achievable computational precision. To address this, a promising approach is projecting the phase configuration of phase change material onto some stable element within the device. Here, the projection mechanism in a prominent phase-change memory device architecture, namely mushroom-type phase-change memory, is investigated. Using nanoscale projected Ge₂Sb₂Te₅ devices, the key attributes of state-dependent resistance, drift coefficients, and phase configurations are studied, and using them how these devices fundamentally work is understood.     

多隧道结单电子动态存储器的Monte Carlo模拟

本文采用Monte Carlo方法模拟了多隧道结单电子动态存储器的存储特性，考察了隧道结的个数、隧道结电容、隧道结电阻、脉冲电压幅度等参数对存储器的存储时间和饱和充电电荷的影响，并与宏观RC电路进行了比较。     

Magnetomechanical Four‐State Memory

With current non‐volatile memory technology approaching intrinsic storage density limits, new data storage technologies are under development. Probe‐based storage systems provide alternatives to conventional mass storage technologies. Ni‐Mn‐Ga, a ferromagnetic shape memory alloy (FSMA), is proposed as a medium for multi‐bit storage using scanning probe microscopy (SPM) techniques. Local modifications of the magnetic stray field were achieved using nanoindentation. Magnetic poles collect within the indentation, which is leveraged to control the magnetic stray field for the patterning of magnetic information. Four magnetic‐based memory states are possible due to magnetic field or stress‐induced twin rearrangement along two crystal orientations, each with two possible magnetic orientations.     

智能天线系统模拟权值乘法器的设计

提出和实现了一种智能天线系统的模拟权值乘法器。这种乘法器将智能天线阵接收到的基带信号与模拟权值进行相乘,实现了智能天线的波束形成。其处理速度快,无量化误差,无需数/模和模/数转换,无需存储空间等外部设备,硬件完全由乘法器芯片和运放芯片组成,模拟电路简单,实现和调试方便。仿真和实验的对比结果表明,提出的模拟权值乘法器具有较强的可行性和可靠性。     

采用单片CPLD实现动目标检测处理

介绍了一种大规模复杂可编程逻辑器件(CPLD)在雷达信号处理系统中动目标检测电路的应用及具体实现方法。系统充分利用CPLD的高集成度,有效地降低了整个电路的复杂程度。由于简化了电路设计,减少了器件数量,大大提高了电路的可靠性。并且采用数字电路后,系统的稳定性和性能指标都比模拟电路更好。     

APR6016及其在桩基检测中的应用

新型语音芯片APR6016采用多级模拟存储技术，实行模拟数字双存储模式；该芯片采用SPI接口，适合用在微处理器组成的系统中。将APR9016应用在桩基检测语音报值系统中，系统功能全、音质好、价格低。     

A refreshable analog VLSI neural network chip with 400 neurons and40 K synapses

An on-chip learning neural network LSI circuit that can refresh the analog storage synaptic weights located on a chip is described. The chip integrates 400 neurons and 40000 synapses with a 0.8-μm double-poly double-metal CMOS technology. This device stores learned information by repeating the refresh process at 200-ms intervals     

Competitive learning in asynchronous-pulse-density integrated circuits

This paper introduces MOS circuits for the integrated implementation of competitive learning. A singlelayer competitive network architecture composed of asynchronous-pulse-coded processing elements is employed. The processing elements perform analog computations and communicate via asynchronous-pulse-density-modulated signals which encode continuous-time signal information using discrete binary values. The specific focus is upon the design and simulation of an adaptive synapse circuit which combines a capacitive analog storage element with subthreshold adaptation circuitry. The simulations presented verify circuit operation in a two-input, three-output competitive network. Accurate clustering of both fixed and random training data is demonstrated.     

Mixed-Mode Programmable and Scalable Architecture for On-Chip Learning

Typical analog VLSI architectures for on-chip learning are limited in functionality, and scale poorly under variable problem size. We present a scalable hybrid analog-digital architecture for backpropagation learning in multilayer feedforward neural networks, which integrates the flexible functionality and programmability of digital control functions with the efficiency of analog parallel neural computation. The architecture is fully scalable, both in the parallel analog functions of forward and backward signal propagation through synaptic and neural functional units (SynMod and NeuMod), and in the global and local digital functions controlling recall, learning, initialization, monitoring and built-in test. The architecture includes local provisions for long-term weight storage using refresh, which is transparent to the functional operation both during recall and learning. Refresh While Learning (RWL) provides a means to compensate for the finite precision of the quantized analog weights during learning. We include simulation results for a network of 32×32 neurons, mapped in parallel onto a MassPar computational engine, which validate the functionality of the architecture on simple character recognition tasks, and demonstrate robust operation of the trained network under 4-bit quantization of the weights owing to the RWL technique.     

智能天线系统模拟权值乘法器的设计

提出和实现了一种智能天线系统的模拟权值乘法器。这种乘法器将智能天线阵接收到的基带信号与模拟权值进行相乘,实现了智能天线的波束形成。其处理速度快,无量化误差,无需数模、模数转换,无需存储空间等外部设备,硬件完全由乘法器芯片和运放芯片组成,模拟电路简单,实现和调试方便。仿真和实验的结果对比表明提出的模拟权值乘法器具有较强的可行性和可靠性。     

A 270-kb/s 35-mW modulator IC for GSM cellular radio hand-heldterminals

The modulator IC is a mixed analog/digital transceiver component in a chip set that is designed for the hand-held terminals of the pan-European 900-MHz Groupe Special Mobile (GSM) digital cellular radio network. The concept of the radio-frequency environment in which the circuit is used is explained, focusing on the differences in existing systems. The architecture and different functions of the modulator circuit and details of the digital and analog processing in the transmission mode are discussed. The receiving mode, which is mostly based on analog processing, is highlighted. The device generates Gaussian minimum-shift-keying (GMSK) modulation and converts the received signal to 8-b words after filtering. The modulator IC uses digital waveform generation and a quadrature signal representation. This device is implemented in a 1.5-μm CMOS technology. The power consumption is less than 35 mW from a 5-V supply