高频C—V法在肖特基势垒接触退化失效分析中的应用

ＧａＡｓ ＭＥＳＦＥＴ的栅极肖特基势垒接触退化的主要失效机理是栅金属下沉和栅金属扩散,因而引起有效沟道宽度减小或沟道掺杂浓度的下降。笔者用高频Ｃ－Ｖ法测定试验前后沟道载流子浓度随深度分布的变化,可获得栅金属下沉和栅金属扩散的信息,为肖特基接触退化的失效分析提供了一种有效的方法。     

GaAs PHEMT器件高温加速寿命试验及物理分析

GaAs微波器件的退化与金属化稳定性密切相关,实现PHEMT器件功能的金属化主要有栅金属化、欧姆接触金属化和信号传输线金属化。本文针对定制的GaAs PHEMT器件的栅金属接触孔链和欧姆接触金属方块条进行了高温加速应力寿命试验,并对器件金属化失效单机理进行寿命预计,同时对试验后的样品进行物理分析。结果显示栅金属接触孔链在180℃下就发生失效,接触孔链表面的金属化层形变,金属化发生了迁移;而AuGeNi欧姆接触在225℃高温下更易发生电迁移失效,金属向体内扩散并在金属条上形成空洞。     

GaAs MESFET栅极漏电流退化机理分析

高温存储试验后某种ＧａＡｓ　ＭＥＳＦＥＴ的栅－漏极正向和反向漏电流增大。为分析失效机理,测定了试验前后栅－漏极低压正向电流随温度的变化,定性估计了试验前后复合－产生中心浓度的变化,确定肖特基势垒接触有源层的复合－产生中心浓度增加是两种漏电流增大的原因,为高温下ＧａＡｓ　ＭＥＳＦＥＴ的肖特基势垒接触存在栅金属下沉和扩散提供了证据。     

GaAs苛MESFET栅极漏电流退化机理分析

高温存储试验后某种ＧａＡｓ ＭＥＳＦＥＴ的栅－漏极正向和反向漏电流增大。为分析失效机理,测定了试验前后栅－漏极低电压正向电流随温度的变化,定性估计了试验前后复合－产生中心浓度的变化,确定肖待基势垒触有源层的复合－产生中心浓度的增加是两种漏电流增大的原因,为高温下ＧａＡｓ ＭＥＳＦＥＴ的肖特基势垒接触存在栅金属下沉和扩散提供了证据．     

基于故障树分析法的GaAs MMIC烧毁失效分析

用故障树分析法对一款高温工作寿命试验过程中烧毁的GaAs功率单片集成电路(MMIC)进行失效分析.故障样品呈现为有源区烧毁,判定由电流过大或过热引起.故障树的顶事件为GaAs功放芯片烧毁,次级因素分为设计缺陷、内部因素及外围因素三个方面.然后列举导致过热或电流过大的情况并建立故障树,通过对故障树中的末级故障逐一排查后,最终定位其烧毁是由栅金属下沉引起.这种故障模式主要出现在长期高温情况下,一般在正常使用过程中不会出现.     

高温正向大电流下TiAl、TiPtAu栅GaAs MESFET的栅退化机理及其对器件特性的影响

针对ＧａＡｓ ＭＥＳＦＥＴ在微波频率的应用中的射频过驱动导致高栅电流密度现象,设计了Ｔｉａｌ栅和ＴｉＰｔＡｕ栅ＧａＡｓ ＭＥＳＦＥＴ的高温正向大电流试验,通过对试验数据和试验样品的扫描电镜静态电压衬度像以及试验中的失效样品进行分析,确定了栅寄生并联电阻的退化是导致器件的跨导ｇｍ、栅反向漏电流Ｉｓ、夹断电压Ｖｐ等特性退化,甚至导致器件烧毁失效的主要原因。     

高温正向大电流下TiAl,TiptAu栅GaAsMESFET的栅退化机理 …

针对ＧａＡｓＭＥＳＦＥＴ在微波频率的应用中的射频过驱动导致高栅电流密度现象,设计了ＴｉＡｌ栅和ＴｉＰｔＡｕ栅ＧａＡｓ ＭＥＳＦＥＴ的高温正向大电流试验,通过对试验数据和试验样品的扫描电镜静态电压衬度像以及试验中的失效样品进行分析,确定了栅寄生并联电阻的经是导致器件的跨导ｇｍ、栅反向漏电流Ｉｓ、夹断电压Ｖｐ等特性退化,甚至导致器件烧毁失效的主要原因。     

砷化镓微波单片集成电路的失效分析

通过封装内部气氛、芯片显微、能谱等分析手段对国内某研究所研制砷化镓微波单片集成电路高温加速寿命试验后的样品进行了失效分析,对其失效机理进行探讨,得出:封装气密性不好、工艺造成的缺陷是引起失效的主要原因,也是造成国内产品质量与可靠性不如国外同类产品的重要原因。     

大容量液体钽电容器高温负荷时失效机理研究

对CA35型160 V/47μF液体钽电解电容器进行2 000 h/85℃高温负荷耐久性试验。通过对失效样品的电性能的测试及对样品阳极钽芯表面氧化膜的结构变化的SEM分析,探讨了其失效机理。表明在高温负荷条件下,由于场致晶化和热致晶化的作用,Ta2O5介质膜由无定形态转化为结晶态,介质膜结构发生畸变是引起产品失效的主要原因。     

砷化镓PHEMT功率管高温加速寿命试验研究

通过解决温度提升、温度稳定控制、寄生振荡抑制等关键问题,使砷化镓PHEMT功率器件的高温加速寿命试验得以实施。经过2 832h试验,三个分组的样品均出现了失效。对样品的失效模式与机理进行了分析,并确定了失效原因。对试验数据进行分析得到了该器件的寿命分布与寿命加速特性,并对分析结论进行了验证。     

Subtle gate oxide defect elimination to improve the reliability of a 32M-bit SRAM product

Tiny defects may escape from in-line defect scan and pass WAT (Wafer Acceptance Test), CP (Chip Probing), FT (Final Test) and SLT (System Level Test). Chips with such kind of defects will cause reliability problem and impact revenue significantly. It is important to catch the defects and derive the prevention strategy earlier in the technology development stage. In this paper, we investigate an SRAM with tiny defects which passed in-line defect scan, WAT, CP and FT but failed in HTOL (High Temperature Operation Life) test, one of the product reliability qualification items. FA (Failure Analysis) reveals gate oxide missing defect is the root cause. The goal is to pass reliability qualification and release product into production on schedule. The failure mechanism, optimization of gate oxide process, enhancement of defect scan and testing methodology will be introduced. Experiment results show very good HTOL performance by the combination of process and testing optimization.     

Analysis of high power microwave induced degradation and damage effects in AlGaAs/InGaAs pHEMTs

The high power microwave (HPM) induced effects in AlGaAs/InGaAs pseudomorphic high electron mobility transistors (pHEMTs) are investigated by simulation and experiments. Simulated results suggest that the HPM damage mechanism is device burnout, which is caused by emerging current path and strong electric field intensity beneath the gate metal. Besides, analysis points out that the gate metal diffusion may be thermally activated, resulting in DC and RF performance degradation. Specifically, a positive shift will occur to the pinch-off voltage while accordingly the small-signal gain will decrease. The HPM injection experiments on the dual-stage pHEMT low noise amplifiers (LNAs) are carried out. Experimental results substantiate that deterioration happens both in the noise figure and in the small-signal gain, which is in agreement with the simulated results. Failure analysis indicates that the HPM induced failure of LNA is attributed to the failure of the first stage pHEMT. Finally, samples dissection analysis using the scanning electron microscopy (SEM) verifies the simulation analysis of the damage mechanism and the location susceptible to burnout. Meanwhile, the assumption of gate metal diffusion is validated by the observation of pits after removing the gate metal. The performance parameters deterioration can be utilized as the degradation (or damage) criteria, and the mechanisms analysis facilitates making reinforcing design.     

VMOS reliability

Whenever a new technology such as VMOS emerges, one key element to its success is the reliability of the products manufactured in that technology. The results of a reliability study to examine the fundamental VMOS device stability, high-temperature operating life (HTOL) failure rates, and electrostatic protection are presented for the VMOS technology. Experimental data for more than five (5) million device-hours of HTOL predict a reliability failure rate of less than 0.01 percent/1000 h at 70°C for products fabricated in the VMOS technology. In addition, an electrostatic protection capability greater than 1800 V is possible with specially designed VMOS input protection devices.     

A Packaged 20-GHz 1-W GaAs MESFET with a Novel Via-Hole Plated Heat Sink Structure

A novel Via-Hole plated heat sink (PHS) structure with an improved gate-packing density is developed for K-band GaAs power FET's. The gate-packing density in this structure is increased to four times greater than that in the conventional direct via-hole structure, by making via-holes under the source-grounding pads fabricated outside the FET active area. The increase in the gate-packing density allows the design of a high-power, high-frequency FET with a larger gate periphery. The resultant 2.4-mm gate periphery device with 0.7µm gate length delivered 1.1 W (30.4 dBm) of output power with 5.0-dB gain and 19.2-percent power added efficiency at 20 GHz, and exhibited 0.74 W (28.7 dBm) at 30 GHz. The same type of device assembled in the hermetically sealed package delivered 1.0 W (30 dBm) of output power with 4.8-dB gain and 13-percent power added efficiency at 20 GHz. Thermal and mechanical-environmental tests were made to assess the reliability of the novel Via-Hole PHS FET. Results showed no failure nor significant change in device parameters throughout the tests.     

掺钕双频微片激光器功率均衡实验研究

为了探究掺钕晶体对激光器功率均衡机制的影响 ,实验对不同参数的掺钕晶体双频微片激光器进行了功率均衡实 验研究。在实验中,通过改变抽运功率和调节热沉温度等手段,研究了双频微片激光器功率 在均衡状态时,热沉温度、 抽运功率和双频激光功率积等参数之间的关系。研究结果表明:对于功率均衡的掺钕双频微 片激光器,当抽运功率增加 时,热沉温度随之降低且与之呈负相关,需要降低热沉温度以实现双频激光的功率重新均衡 ;重新均衡后的双频激光波 长与频差不随抽运功率的变化而变化;功率均衡的双频激光功率积随抽运功率的增大而增大 ,且呈正相关。此结果说明 对于不同参数的掺钕晶体双频微片激光器,均可通过改变抽运功率和热沉温度可以实现功率 可调的功率均衡的双频激光 信号输出。这种输出功率可调谐的双频微片激光器在光生毫米波等领域有较大用途。     

SOI专用集成电路的静态电流监测和失效分析

静态电流测试是一种高灵敏度、低成本的集成电路失效分析技术,在集成电路故障检测、可靠性测试及筛选中的应用日益普遍。针对某绝缘体上硅专用集成电路在老炼和热冲击实验后出现的静态电流测试失效现象,结合样品伏安特性、光发射显微镜和扫描电子显微镜等电学和物理失效分析手段,确定了栅氧化层中物理缺陷的存在、位置及类型;结合栅氧化层经时介质击穿原理分析,揭示了样品的主要失效机理,并分析了经时介质击穿失效的根源,为改进工艺、提高电路可靠性提供了依据。     

Sudden failures associated with the gate oxide of CMOS transistors

Sudden failures appearing during static gate bias — temperature aging of CMOS transistors are investigated in this paper. Shorts between the gate and substrate as well as open gate circuits are found to be failure modes appearing during testing. The subsequent failure analysis reveals that the reaction between the aluminium and gate oxide is the failure mechanism, while defects in P⁺-diffusion regions (which are transferred onto the gate oxide) are the cause of the observed failures.     

Gate metallization "Sinking" into the active channel in Ti/W/Au metallized power MESFET's

Commercial power MESFET's with Ti/W/Au gate metallization show a failure mode consisting of a decrease in Idssand Vpand an increase in R0. The failure mechanism was investigated by electrical and structural analyses with SEM, microprobe, and Auger spectrometry, and turns out to be a thermally activated Au-GaAs interdiffusion leading to encroachment of the gate metal on the channel. This may be common to all Au-metallized MESFET's and can lead to burn-out of devices.     

Impact of gate placement on RF power degradation in GaN high electron mobility transistors

We have investigated the RF power degradation of GaN high electron mobility transistors (HEMTs) with different gate placement in the source–drain gap. We found that devices with a centered gate show different degradation behavior from those with the gate placed closer to the source. In particular, centered gate devices degraded through a mechanism that has a similar signature as that responsible for high-voltage DC degradation in the OFF state and is likely driven by electric field. In contrast, offset gate devices under RF power stress showed a large increase in source resistance, which is not regularly observed in DC stress experiments. High-power pulsed stress tests suggest that the combination of high voltage and high current stress maybe the cause of RF power degradation in these offset-gate devices.     

Investigation of charge trapping/de-trapping induced operation lifetime degradation in triple SuperFlash® memory cell

In this paper, through triple SuperFlash^® cell, different results of high temperature operation lifetime (HTOL) after endurance cycling have been identified. Several factors affected this type device lifetime, including of program-erase cycling stress and bake procedure, are investigated. Due to special erase operation mode, a different behavior of charge trapping/de-trapping in triple SuperFlash^® cell has been observed and analyzed. The mechanism which induced various HTOL results could be explained by the combined effects of voltage acceleration and electrons trapping/de-trapping behaviors during bake.