Model based precise analysis of the injection currents in Al/ZrO2/Al2O3/ZrO2/SiO2/Si structures for use in charge trapping non-volatile memory devices

Metal/insulator/Silicon (MIS) capacitors containing multilayered ZrO₂/Al₂O₃/ZrO₂/SiO₂ dielectric were investigated in order to evaluate the possibility of their application in charge trapping non-volatile memory devices. The ZrO₂/Al₂O₃/ZrO₂ stacks were deposited by reactive rf magnetron sputtering on 2.4 nm thick SiO₂ thermally grown on p-type Si substrate. C–V characteristics at room temperature and I–V characteristics recorded at temperatures ranging from 297 K to 393 K were analyzed by a comprehensive model previously developed. It has been found that Poole-Frenkel conduction in ZrO₂ layers occurs via traps energetically located at 0.86 eV and 1.39 eV below the bottom of the conduction band. These levels are identified as the first two oxygen vacancies related levels in ZrO₂, closest to its conduction band edge, whose theoretical values reported in literature are: 0.80 eV, for fourfold, and 1.23 eV, for threefold coordinated oxygen vacancies.     

Reliable impurity trap memory with high charge trap efficiency using ultrathin SiO2 impurity host layer for nonvolatile memory application

We demonstrated reliable impurity trap memory (ITM) with high charge trap efficiency by incorporating only 1 nm-SiO₂ impurity host layer (IHL) between Al₂O₃ diffusion barrier layer and blocking oxide. While the ITM without IHL showed significant retention degradation as the amount of Ti impurity increased from 0.7 to 3 Å for enlarging memory window, the ITM with IHL showed stable retention characteristic which is charge loss less than 1 V after 10⁴ s at 85 °C. We postulated that the chemical reaction between Ti and SiO₂ induced three dimensionally-distributed impurity traps in IHL, which could result in the well-discrete stored charges in program mode.     

Resistive switching properties of a thin SiO2 layer with CeOx buffer layer on n+ and p+ Si bottom electrodes

Resistive switching properties of a 2-nm-thick SiO₂ with a CeO_x buffer layer on p⁺ and n⁺ Si bottom electrodes were characterized. The distribution of set voltage (V_set) with the p⁺ Si bottom electrode devices reveals a Gaussian distribution centered in 4.5 V, which reflects a stochastic nature of the breakdown of the thin SiO₂. Capacitance–voltage (C–V) measurements indicate the trapping of electrons by positively shifting the C–V curve by 0.2 V during the first switching cycle. On the other hand, devices with the n⁺ Si bottom electrodes showed a broad distribution in V_set with a mean value higher than that of p⁺ Si bottom electrode devices by 0.9 V. Although no charge trapping was observed with n⁺ Si bottom electrode devices, a degradation in interface states was confirmed, causing a tail in the lower side of the V_set distribution. Based on the above measurements, the difference in the V_set can be understood by the work function difference and the contribution of electron trapping.     

ZrO2 insulator modified by a thin Al2O3 film to enhance the performance of InGaZnO thin-film transistor

A high-performance InGaZnO (IGZO) thin-film transistor (TFT) with ZrO₂–Al₂O₃ bilayer gate insulator is fabricated. Compared to IGZO-TFT with ZrO₂ single gate insulator, its electrical characteristics are significantly improved, specifically, enhancement of I_on/I_off ratios by one order of magnitude, increase of the field-effect mobility (from 9.8 to 14 cm²/Vs), reduction of the subthreshold swing from 0.46 to 0.33 V/dec, the maximum density of surface states at the channel-insulator interface decreased from 4.3 × 10¹² to 2.5 × 10¹² cm⁻². The performance enhancements are attributed to the suppression of leakage current, smoother surface morphology, and suppression of charge trapping by using Al₂O₃ films to modify the high-k ZrO₂ dielectric.     

Influence of atomic layer deposition chemistry on high-k dielectrics for charge trapping memories

In this work we report the performance of the SiO₂/Si₃N₄/HfO₂ and SiO₂/Si₃N₄/ZrO₂ stacks with emphasis on the influence of atomic layer deposition chemistry used for forming the HfO₂ and ZrO₂ blocking layers. Two Hf precursors were employed – tetrakis(ethylmethylamino)hafnium (TEMAH) and bis(methylcyclopentadienyl)methoxymethyl hafnium (HfD-04). For ZrO₂, tetrakis(ethylmethylamino)zirconium (TEMAZ) and bis(methylcyclopentadienyl)methoxymethyl zirconium (ZrD-04) were used as metal precursors. Ozone was used as the oxygen source. The structural characteristics of the stacks were examined by transmission electron microscopy and grazing incidence X-ray diffraction. The electrical properties of the stacks were studied using platinum-gated capacitor structures. The memory performance of the stacks was evaluated by write/erase (W/E) measurements, endurance and retention testing. Endurance measurements revealed the most important difference between the stacks. The films grown from TEMAH and TEMAZ could withstand a significantly higher number of W/E pulses (>3 × 10⁵ in the 10 V/?11 V, 10 ms regime), in comparison to the stacks made from HfD-04 and ZrD-04 precursors (<5 × 10³ W/E cycles). This difference in endurance characteristics is attributed mainly to the different deposition temperatures suited for these two precursors and the nature of the layer formed at the Si₃N₄/HfO₂ and the Si₃N₄/ZrO₂ interfaces.     

Optical and electrical characteristics of 17 keV X-rays exposed TiO2 films and Ag/TiO2/p-Si MOS device

This work presents the effect of varied doses of X-rays radiation on the Ag/TiO₂/p-Si MOS device. The device functionality was observed to depend strongly on the formation of an interfacial layer composed of SiO_x and TiO_y, which was confirmed by the spectroscopic ellipsometry. The XRD patterns showed that the as prepared TiO₂ films had an anatase phase and its exposure to varied doses of 17 keV X-rays resulted in the formation of minute rutile phase. In the X-rays exposed films, reduced Ti³⁺ state was not observed; however a fraction of Ti–O bonds disassociated and little oxygen vacancies were created. It was observed that the device performance was mainly influenced by the nature and composition of the interfacial layer formed at the TiO₂/Si interface. The spectroscopic ellipsometry was used to determine the refractive indices of the interfacial layer, which was 2.80 at λ=633 nm lying in between that of Si (3.87) and TiO₂ (2.11). The dc and frequency dependent electrical measurements showed that the interface defects (traps) were for both types of charge carriers. The presence of SiO_x was responsible for the creation of positive charge traps. The interface trap density and relaxation time (τ) were determined and analyzed by dc and frequency dependent (100 Hz–1 MHz) ac-electrical measurements. The appearance of peak in G/ω vs log (f) confirmed the presence of interface traps. The interface traps initially increased up to exposure of 10 kGy and then decreased at high dose due to compensation by the positive charge traps in SiO_x part of the interface layer. It was observed that large number of interface defects was active at low frequencies and reduced to a limiting value at high frequency. The values of relaxation time, τ ranged from 4.3±0.02×10⁻⁴ s at 0 V and 7.6±0.2×10⁻⁵ s at −1.0 V.     

Potentiality of trap charge effects and SiON induced interface defects in a-Si3N4/SiON based MIS structure for resistive NVM device

Potential application of amorphous silicon nitride (a-Si₃N₄)/silicon oxy-nitride (SiON) film has been demonstrated as resistive non-volatile memory (NVM) device by studying the Al/Si₃N₄/SiON/p-Si metal–insulator–semiconductor (MIS) structure. The existence of several deep trap states was revealed by the photoluminescence characterizations. The bipolar resistive switching operation of this device was investigated by current–voltage measurements whereas the trap charge effect was studied in detail by hysteresis behavior of frequency dependent capacitance–voltage characteristics. A memory window of 4.6 V was found with the interface trap density being 6.4 × 10¹¹ cm⁻² eV⁻¹. Excellent charge retention characteristics have been observed for the said MIS structure enabling it to be used as a reliable non-volatile resistive memory device.     

Self-aligned inversion n-channel In0.2Ga0.8As/GaAs metal–oxide–semiconductor field-effect-transistors with TiN gate and Ga2O3(Gd2O3) dielectric

A self-aligned process for fabricating inversion n-channel metal–oxide–semiconductor field-effect-transistors (MOSFET’s) of strained In_0.2Ga_0.8As on GaAs using TiN as gate metal and Ga₂O₃(Gd₂O₃) as high κ gate dielectric has been developed. A MOSFET with a 4 μm gate length and a 100 μm gate width exhibits a drain current of 1.5 mA/mm at V_g = 4 V and V_d = 2 V, a low gate leakage of <10^?7 A/cm² at 1 MV/cm, an extrinsic transconductance of 1.7 mS/mm at V_g = 3 V, V_d = 2 V, and an on/off ratio of ～10⁵ in drain current. For comparison, a TiN/Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As MOS diode after rapid thermal annealing (RTA) to high temperatures of 750 °C exhibits excellent electrical and structural performances: a low leakage current density of 10^?8–10^?9 A/cm², well-behaved capacitance–voltage (C–V) characteristics giving a high dielectric constant of ～16 and a low interfacial density of state of ～(2～6) × 10¹¹ cm^?2 eV^?1, and an atomically sharp smooth Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As interface.     

Characterization of CoxNiyO hybrid metal oxide nanoparticles as charge trapping nodes in nonvolatile memory devices

The Co_xNi_yO hybrid metal oxide nanoparticles (HMONs) embedded in the HfO_xN_y high-k dielectric as charge trapping nodes of the nonvolatile memory devices have been formed via the chemical vapor deposition using the Co/Ni acetate calcined and reduced in the Ar/NH₃ ambient. A charge trap density of 8.96 × 10¹¹ cm^?2 and a flatband voltage shift of 500 mV were estimated by the appearance of the hysteresis in the capacitance–voltage (C–V) measurements during the ±5 V sweep. Scanning electron microscopy image displays that the Co_xNi_yO HMONs with a diameter of ～10–20 nm and a surface density of ～1 × 10¹⁰ cm^?2 were obtained. The mechanism related to the writing characteristics are mainly resulted from the holes trapping. Compared with those devices with the Co_xNi_yO HMONs formed by the dip-coated technique, memory devices with the Co_xNi_yO HMONs fabricated by the drop-coated technique show improved surface properties between the Co_xNi_yO HMONs and the HfON as well as electrical characteristics.     

A low voltage SANOS nonvolatile semiconductor memory (NVSM) device

In this paper, we present a new Polysilicon–Aluminum Oxide–Nitride–Oxide–Silicon (SANOS) device structure suitable for future nonvolatile semiconductor memories. Replacing SiO₂ with a high-K material, Al₂O₃ (K_f = 9) as the top blocking layer of the conventional SONOS device increases the electric field across the tunnel oxide, while reducing the electric field across the blocking layer with its dielectric constant during write and erase operations. Therefore, this new device can achieve lower programming voltages and faster programming speed than the conventional SONOS device. We have fabricated SANOS capacitors with 2 nm tunnel oxide, 5 nm silicon nitride and 8 nm aluminum oxide and studied the programming speed and charge retention characteristics of the new devices. These new SANOS devices achieve a 2 V reduction in the programming voltages with 2.1 V initial memory window.     

Organic alternating current electroluminescence device based on 4,4′-bis(N-phenyl-1-naphthylamino) biphenyl/1,4,5,8,9,11-hexaazatriphenylene charge generation unit

An organic alternating current electroluminescence (OACEL) device based on 4,4′-bis(N-phenyl-1-naphthylamino) biphenyl (NPB)/1,4,5,8,9,11-hexaazatriphenylene (HAT-CN)/tris(8-hydroxy-quin-olinato) aluminum (Alq₃) doped with cesium carbonate (Cs₂CO₃) internal charge generation unit is demonstrated. Maximum luminance of 299 cd/m² is observed for Alq₃ doped with 10-(2-Benzothiazolyl)-2,3,6,7-tetrahydro-1,1,7,7-tetramethyl-1H,5H, 11H-(1) benzopyropyrano (6,7-8-I,j)quinolizin-11-one (C545T) fluorescent emission layer when driven with a peak–peak voltage of 80 V at 120 kHz. The key charge-generation role of NPB/HAT-CN interface is studied experimentally. Furthermore, influence of evaporation sequence of this internal charge generation unit on OACEL performance is investigated. This work demonstrated that the undoped charge generation unit – NPB/HATCN, can also be a good candidate for charge generation unit of OACEL device.     

Characterization of TiOxNy nanoparticles embedded in HfOxNy as charge trapping nodes for nonvolatile memory device applications

Silicon-oxide–nitride-oxide–silicon devices with nanoparticles (NPs) as charge trapping nodes (CTNs) are important to provide enhanced performance for nonvolatile memory devices. To study these topics, the TiO_xN_y metal oxide NPs embedded in the HfO_xN_y high-k dielectric as CTNs of the nonvolatile memory devices were investigated via the thermal synthesis using Ti thin-film oxidized in the mixed O₂/N₂ ambient. Well-isolated TiO_xN_y NPs with a diameter of 5–20 nm, a surface density of ～3 × 10¹¹ cm^?2, and a charge trap density of around 2.33 × 10¹² cm^?2 were demonstrated. The writing characteristic measurements illustrate that the memory effect is mainly due to the hole trapping.     

High-performance barrier using a dual-layer inorganic/organic hybrid thin-film encapsulation for organic light-emitting diodes

We report an inorganic/organic hybrid barrier that combines the alternating deposition of a layer of ZrO₂ using low temperature atomic layer deposition and a 16-μm-thick layer of UV-curable NOA63 epoxy using spin-coating. The effective water vapor transmission rates of single ZrO₂ film was improved by adding solution epoxy from 3.03 × 10⁻³ g/m² day to 1.27 × 10⁻⁴ g/m² day in the hybrid NOA63/ZrO₂/NOA63/ZrO₂ films at 20 °C and a relative humidity of 60%. In consequence, the organic light-emitting diodes encapsulated with inorganic/organic hybrid barriers were undamaged by environmental oxygen and moisture and their luminance decay time improved by a considerable extent.     

Ultra-low-energy ion-beam-synthesis of Ge nanocrystals in thin ALD Al2O3 layers for memory applications

Structural and electrical properties of ALD-grown 5 and 7 nm-thick Al₂O₃ layers before and after implantation of Ge ions (1 keV, 0.5–1 × 10¹⁶ cm^?2) and thermal annealing at temperatures in the 700–1050 °C range are reported. Transmission Electron Microscopy reveals the development of a 1 nm-thick SiO₂-rich layer at the Al₂O₃/Si substrate interface as well as the formation of Ge nanocrystals with a mean diameter of ～5 nm inside the implanted Al₂O₃ layers after annealing at 800 °C for 20 min. Electrical measurements performed on metal–insulator–semiconductor capacitors using Ge-implanted and annealed Al₂O₃ layers reveal charge storage at low-electric fields mainly due to location of the Ge nanocrystals at a tunnelling distance from the substrate and their spatial dispersion inside the Al₂O₃ layers.     

Electrical characterization of metal-ferroelectric (Mn-substituted BiFeO3)-insulator (HfO2)-semiconductor capacitors for nonvolatile memory applications

Metal-ferroelectric (Mn-substituted BiFeO₃)-insulator (HfO₂)-semiconductor has been fabricated by co-sputtering technique. X-ray diffraction (XRD) patterns have proven the existence of a substitution phase. The shift in binding energy of Fe ions and the change in atom ratio of Mn to Fe were analyzed by X-ray photoelectron spectra (XPS). The memory windows as functions of insulator film thickness and annealing temperature were compared. The maximum memory window is 3 V at the sweep voltage of 8 V with thicker (60 nm) HfO₂. The leakage current and the charge injection effect can be reduced with increasing the amount of substituting Mn for Fe-site.     

Enhanced pure red electroluminescence intensity of Eu(o-BBA)3(phen) by red dye co-doping and inorganic semiconductor as charge carrier function layer

There is an emission peak at 494 nm in the electroluminescence (EL) of PVK [poly(n-vinylcarbazole)]: Eu(o-BBA)₃(phen) besides PVK exciton emission and Eu³⁺ characteristic emissions. Both the peaking at 494 nm emission and PVK emission influenced the color purity of red emission from Eu(o-BBA)₃(phen). In order to restrain these emissions and obtain high intensity red emission, 4-(dicyanomethylene)-2-t-butyl-6-(1,1,7,7,-tetramethyljulolidy-9-enyl)-4Hpyran (DCJTB) and Eu(o-BBA)₃(phen) were co-doped in PVK solution and used as the active emission layer. The EL intensity of co-doped devices reached to 420 cd/m² at 20 V driving voltage. The chromaticity coordinates of EL was invariable (x = 0.55, y = 0.36) with the increase of driving voltage. For further improvement of EL intensity, organic–inorganic hybrid devices (ITO/active emission layer/ZnS/Al) were fabricated. The EL intensity was increased by a factor of 2.5 [(420 cd/m²)/(168 cd/m²)] when the Eu complex was doped with an efficient dye DCJTB, and by a factor of ≈4 [(650 cd/m²)/(168 cd/m²)] when in addition ZnS layer was deposited on such an emitting layer prior to evaporation of the Al cathode.     

Enhancing charge transport in copper phthalocyanine thin film by elevating pressure of deposition chamber

Copper phthalocyanine (CuPc)-based thin film transistors were fabricated using CuPc films grown under different deposition pressure (P_dep) (ranging from 1.8 × 10⁻⁴ Pa to 1.0 × 10⁻¹ Pa). The transistor performance highly depended on P_dep. A field-effect mobility of 2.1 × 10⁻² cm²/(V s) was achieved under 1.0 × 10⁻¹ Pa. Detailed investigations revealed that P_dep modulates the molecular packing and orientation of the organic films grown on a SiO₂/Si substrate and influences the charge transport. Furthermore, from a device physics point of view, contact resistance of the fabricated transistors decreased when P_dep increased, which was beneficial in reducing energy consumption.     

The effect of annealing temperature on the electrical properties of metal-ferroelectric (PbZr0.53Ti0.47O3)-insulator (ZrO2)-semiconductor (MFIS) thin-film capacitors

Metal-ferroelectric-insulator-semiconductor (MFIS) thin-film structures using PbZr_0.53Ti_0.47O₃ (PZT) as the ferroelectric layer and zirconium oxide (ZrO₂) as the insulator layer were fabricated in this work. The leakage current and the C-V memory window were measured for MFIS capacitors with the PZT layer annealed at temperatures of 400 °C, 500 °C, 600 °C, 700 °C. The dominant conduction mechanism of Al/PZT(290 nm)/ZrO₂(15 nm)/Si structure is Poole-Frenkel emission in the temperature range of 300-425 K. Under a sweep voltage of 6 V, the largest memory window of 1.31 V was obtained for 500 °C-annealed samples. The memory window as a function of insulator thickness was also discussed. More serious charge injection is observed when the voltage was swept from negative to positive.     

Charge-trapping characteristics of BaTiO3 with and without nitridation for nonvolatile memory applications

The charge-trapping characteristics of BaTiO₃ with and without nitrogen incorporation were investigated based on Al/Al₂O₃/BaTiO₃/SiO₂/Si (MONOS) capacitors. The physical properties of the high-k films were analyzed by transmission electron microscopy and X-ray photoelectron spectroscopy. Compared with the MONOS capacitor with BaTiO₃ as charge-trapping layer, the one with nitrided BaTiO₃ showed higher program speed even at lower operating voltage (4.3 V at +8 V for 100 μs), better endurance property and smaller charge loss (charge loss of 10.6% after 10⁴ s at 85 °C), due to the nitrided BaTiO₃ film exhibiting higher charge-trapping efficiency caused by nitrogen incorporation and suppressed leakage induced by nitrogen passivation.     

Memory characteristics of Al2O3/La2O3/Al2O3 multi-layer films with various blocking and tunnel oxide thicknesses

In order to investigate charge trap characteristics with various thicknesses of blocking and tunnel oxide for application to non-volatile memory devices, we fabricated 5 and 15 nm Al₂O₃/5 nm La₂O₃/5 nm Al₂O₃ and 15 nm Al₂O₃/5 nm La₂O₃/5, 7.5, and 10 nm Al₂O₃ multi-stack films, respectively. The optimized structure was 15 nm Al₂O₃ blocking oxide/5 nm La₂O₃ trap layer/5 nm Al₂O₃ tunnel oxide film. The maximum memory window of this film of about 1.12 V was observed at 11 V for 10 ms in program mode and at ?13 V for 100 ms in erase mode. At these program/erase conditions, the threshold voltage of the 15 nm Al₂O₃/5 nm La₂O₃/5 nm Al₂O₃ film did not change for up to about 10⁴ cycles. Although the value of the memory window in this structure was not large, it is thought that a memory window of 1.12 V is acceptable in the flash memory devices due to a recently improved sense amplifier.