Formation kinetics and structure of Pd2Si films on Si

Backscattering and X-ray techniques have been used to study properties of palladium silicide (Pd₂Si) formed by evaporating thin Pd layers on Si followed by heat treatment. The rate of formation of Pd₂Si in the temperature range of 200–275°C has been measured by 2-MeV ⁴He⁺ ion backscattering. The Pd₂Si layer is found to grow at a rate proportional to the square root of time for thicknesses ranging from approximately 200–4000 Å. The rate of growth is found to be independent of Si substrate orientation or doping type and the rate constant is found to fit a single activation energy of E_a = 1·5±0·1 eV over the temperature range measured. X-ray diffraction indicates the structure to be Pd₂Si with the basal plane roughly parallel to the substrate surface for films formed on 111, 110, 100 and evaporated (amorphous) silicon substrates. The degree of preferred orientation is markedly stronger on [111] Si. Ion channeling measurements confirm that in this case the c-direction of the Pd₂Si is parallel with the [111] direction in the underlying Si.     

Silicide/strained Si1-xGex Schottky-barrierinfrared detectors

By employing a thin silicon sacrificial cap layer for silicide formation, the authors successfully demonstrated Pd₂Si/strained Si_1-xGe_x Schottky-barrier infrared detectors with extended cutoff wavelengths. The sacrificial silicon eliminates the segregation effects and Fermi level pinning which occur if the metal reacts directly with Si_1-x Ge_x alloy. The Schottky barrier height of the silicide/strained Si_1-xGe_x detector decreases with increasing Ge fraction, allowing for tuning of the detector's cutoff wavelength. The cutoff wavelength was extended beyond 8 μm in PtSi/Si _0.85Ge_0.15 detectors. It is shown that high quantum efficiency and near-ideal dark current can be obtained from these detectors     

Structure and electrical characteristics of epitaxial palladium silicide contacts on single crystal silicon and diffused P-N diodes

Pd₂Si contacts to single crystal silicon have been made by depositing Pd at room temperature and annealing at a succession of elevated temperatures. The silicide initially formed is a single crystal, even at room temperature. Its crystal structure is uniquely related to that of the underlying silicon with the basal plane of Pd₂Si making an excellent match, with respect to silicon atom positions, with the (111) plane of silicon. Understanding this epitaxy leads to an appreciation of the excellent electrical characteristics of these contacts which are shown to be superior to alloyed aluminum. For comparison, barrier height measurements reproduce earlier results of Kircher on Pd₂Si formed during a high temperature (200°C) deposition of Pd.     

Schottky–ohmic transition in nickel silicide/SiC-4H system: is it really a solved problem?

The transition from Schottky to ohmic contact in the nickel silicide/SiC system during annealing from 600 to 950 °C was investigated by measuring the electrical properties of the contact and by analyzing the microstructure of the silicide/SiC interface. The graphite clusters formed by carbon atoms during silicidation are uniformly distributed into the silicide layer after annealing at 600 °C and they agglomerate into a thin layer far from the silicide/SiC interface after annealing at 950 °C. At this temperature an increase of the Schottky barrier height was measured, while deep level transient spectroscopy evidences the absence of the 0.5 eV peak related to the carbon vacancies.     

SiC MOSFETs with thermally oxidized Ta2Si stacked on SiO2 as high-k gate insulator

In this paper, we compare the electrical characteristics of MOS capacitors and lateral MOSFETs with oxidized Ta₂Si (O-Ta₂Si) as a high-k dielectric on silicon carbide or stacked on thermally grown SiO₂ on SiC. MOS capacitors are used to determine the dielectric and interfacial properties of these insulators. We demonstrate that stacked SiO₂/O-Ta₂Si is an attractive solution for passivation of innovative SiC devices. Ta₂Si deposition and oxidation is totally compatible with standard SiC MOSFET fabrication materials and processing. We demonstrate correct transistor operation for stacked O-Ta₂Si on thin thermally grown SiO₂ oxides. However the channel mobility of such high-k MOSFETs must be improved investigating the interface properties further.     

Time resolved study on Co/Ni/a-Si phase transition during isothermal annealing at 400 °C

An approach based on in situ sheet resistance analyses during isothermal annealing processes is proposed to find out the critical stages of Co/Ni phase transition on amorphous silicon. Unlike the case of conventional Co/Si systems, it was found that Co/Ni/Si reaction produces a double-peak in the resistance versus time curve. This behaviour was studied by energy filtered transmission electron microscopy (EFTEM), energy dispersive X-ray spectroscopy (EDS) and selected area electron diffraction (SAED) analyses. It was found that cobalt atoms prefer to diffuse through the grain boundaries of the underlying Ni₂Si layer that forms at very low temperature in contact with silicon. The diffusion process stops when cobalt atoms reach the deeper NiSi layer which is located at the interface with the substrate. Finally, CoSi and NiSi phases form separately, and Co(Ni)Si₂ grains nucleate in contact with silicon differently from what is known for thick layer systems.     

GaAs surface plasma treatments for Schottky contacts

The properties of different rectifying metallizations (Al, Ti/Pt, WN_x) on GaAs have been investigated for various surface preparation procedures. In particular, in situ hydrogen plasma treatments were used to remove residual surface contamination (mainly O and C) and a nitrogen plasma to grow a thin mixed nitride layer. Al and Ti/Pt Schottky diodes with an ideality factor very close to 1, but with reduced barrier height, were found after the H₂ plasma as a consequence of H diffusion into GaAs. The Schottky barrier height was further reduced if a H₂ + N₂ plasma was performed. The N content in the sputtering environment during the WN_x deposition affects the diode properties of plasma-treated WN_x contacts. By increasing the N₂ partial pressure, the diode barrier height is reduced, probably due to nitridization of the GaAs surface. Such differences disappear after annealing the diodes in arsine overpressure at 800°C. WN_x contacts deposited under different conditions on H₂ plasma treated substrates also show a similar Schottky barrier height after such annealing.     

Dual metal SiC Schottky rectifiers with low power dissipation

Nickel and titanium are the most commonly used metals for Schottky barrier diodes on silicon carbide (SiC). Ti has a low Schottky barrier height (i.e. 0.8 eV on 6H-SiC), whilst Ni has a higher barrier (i.e. 1.25 eV). Therefore, the first metal allows to achieve a low forward voltage drop V_F but leads to a high leakage current. On the other hand, the second one presents the advantage of a lower reverse leakage current but has also a high value of V_F. In this work, dual-metal-planar (DMP) Schottky diodes on silicon carbide are reported. The rectifying barrier was formed by using an array of micrometric Ti and Ni₂Si (nickel silicide) stripes. This low/high Schottky barrier allowed to combine the advantages of the two metals, i.e. to fabricate diodes with a forward voltage drop close to that of a Ti diode and with a level of reverse current comparable to that of a Ni₂Si diode. Under the application point of view, using this kind of barrier can lead to a reduction of the device power dissipation and an increase of the maximum operating temperature.     

SiC晶圆背面激光退火工艺研究

降低芯片背面金属-半导体欧姆接触电阻是有效提高器件性能的方式之一。采用650 V SiC肖特基势垒二极管(SBD)工艺,使用波长355 nm不同能量的脉冲激光进行退火实验,利用X射线衍射(XRD)和探针台对晶圆背面镍硅合金进行测量分析,得出最佳能量为3.6 J/cm²。退火后采用扫描电子显微镜(SEM)观察晶圆背面碳团簇,针对背面的碳团簇问题,在Ar;气氛下对晶圆进行了表面处理,使用SEM和探针台分别对两组样品的表面形貌和电压-电流特性进行了对比分析。实验结果表明,通过表面处理可以有效降低表面的碳含量,并且使器件正向压降均值降低了6%,利用圆形传输线模型(CTLM)测得芯片的比导通电阻为9.7×10^-6Ω·cm²。器件性能和均匀性都得到提高。     

High-speed Si-based metal-semiconductor-metal photodetectors with an additional composition-graded i-a-Si1−xGex:H layer

The response-speed of Si-based metal-semiconductor-metal (MSM) photodetectors was improved by depositing a composition-graded intrinsic hydrogenated amorphous silicon–germanium (i-a-Si_1−xGe_x:H) layer on crystalline silicon (c-Si). In contrast to the non-composition-graded one (using intrinsic hydrogenated amorphous silicon (i-a-Si:H) layer), the full width at half maximum (FWHM) and fall time of the photodetector transient response were improved from 145.2, 404.6 to 107.6, 223.4 ps respectively. The experimental results showed that the device responsivity and quantum efficiency were increased from 0.329 (A/W) and 0.492 to 0.414 and 0.619 respectively by the employed composition-graded technique. We propose that this enhancement is due to a smoother barrier that is formed at the c-Si and i-a-Si_1−xGe_x:H interface. A lower deposition temperature of i-a-Si_1−xGe_x:H layer could be used to further reduce the fall time of the device transient response from 315.6 (250 °C) to 97.6 (180 °C) ps. To improve the contact properties between Cr electrode and i-a-Si_1−xGe_x:H layer, an annealing technique in hydrogen ambient was employed. The device knee voltage, which is the applied voltage at which the device current start to enter the saturation region in its current (log-scale) versus applied voltage characteristics, could be reduced to around 3.5 V after annealing.     

Characteristics of LPCVD WSi2/n-Si Schottky contacts

Detailed current-voltage and capacitance-voltage characteristics of low-pressure chemical vapor deposited (LPCVD) WSi₂/n-Si Schottky contacts are reported in the temperature range of 21 to 170°C. The diode ideality factor n was found to decrease from a value of 1.46 to 1.15 as temperature was increased. Schottky barrier height φ_B, on the other hand, was found to increase from 0.72 to 0.86 V with temperature. These results suggest that diode characteristics are affected by surface and bulk effects, especially at lower temperatures. High-resolution transmission electron microscopy (TEM) and X-ray photoelectron spectroscopy analyses revealed isolated regions of oxynitride at the silicide/silicon interface that are predominantly located where silicide grain boundaries intersect the silicon surface     

Silicon Schottky barriers and p-n junctions with highly stablealuminum contact metallization

Reactively sputtered amorphous Ta₃₆Si₁₄N₅₀ thin films are investigated as diffusion barriers to improve the thermal stability of contacts to electronic devices, specifically between Al overlayers and Si substrates. Electrical measurements on Schottky diodes and on shallow n ⁺-p junction diodes are used to evaluate the thermal stability of the (Si)/W₄₈Si₂₀N₃₂/Ta₃₆Si ₁₄N₅₀/Al metallization. The W₄₈Si₂₀N₃₂ contacting layer is added to raise the Schottky barrier height on n-type Si. It is shown that a 100-nm-thick Ta₃₆Si₁₄N₅₀ layer effectively prevents the intermixing between Al and Si. With this barrier layer, both shallow junctions and Schottky diodes are electrically stable up to 700°C for 20 min (above the Al melting point of 660°C ), which makes this material the best thin-film diffusion barrier on record     

Characteristics of a In0.52(AlxGa1-x)0.48As/In0.53Ga0.47As(0⩽x⩽1) heterojunction and its application onHEMT's

The quaternary In_0.52(Al_xGa_1-x) _0.48As compound on InP substrates is an important material for use in optoelectronic and microwave devices. We systematically investigated the electrical properties of quaternary In_0.52(Al_xGa_1-x)_0.48As layers, and found a 10% addition of Ga atoms into the InAlAs layer improves the Schottky diode performance. The energy bandgap (E_g ) for the In_0.52(Al_xGa_1-x)_0.48As layer was (0.806+0.711x) eV, and the associated conduction-band discontinuity (ΔE_c), in the InAlGaAs/In_0.53Ga_0.47 As heterojunction, was around (0.68±0.01)ΔE_g . Using this high quality In_0.52(Al_0.9Ga_0.1)_0.48As layer in the Schottky and buffer layers, we obtained quaternary In_0.52(Al_0.9Ga_0.1)_0.48As/In _0.53Ga_0.47As HEMTs. This quaternary HEMT revealed excellent dc and microwave characteristics. In comparison with the conventional InAlAs/InGaAs HEMT's, quaternary HEMT's demonstrated improved sidegating and device reliability     

Material modification of the patterned wafer during dry etching and strip determined by XPS

XPS analysis on single damascene (SD) patterned wafers was performed to study the modification of materials, especially the sidewall, during etching and strip. LKD-5109, MSQ-type materials (k≈2.2) were used as ILD, SiC/SiO₂ as top hard mask (HM), and SiC as bottom liner. The etching in Ar/CF₄/CH₂F₂/O₂ creates a CF_x polymer passivation layer on all patterned surfaces. The etched sidewall surface consists of two regions; a thin skin layer of CF_x polymer and CF-rich SiOC layer behind. An N₂/O₂ strip removes CF_x polymer and CF-rich layer efficiently (less than 1 at.% fluorine content). Instead of fluorine, CN-rich layers containing 11–20 at.% nitrogen were observed for all surfaces. After N₂/O₂ strip, the sidewall consists of two regions; a few nanometers of CN rich SiOC layer at the surface and several tens of nanometers of a C-depleted oxide type layer. N₂/H₂ strip provides a thinner C-depleting oxide type layer than either N₂/O₂ and CF₄/O₂ strips. However, the N₂/H₂ strip cannot eliminate fluorine contamination more than the N₂/O₂ strip.     

镍基高温合金激光熔覆涂层组织及性能研究

为了研究高温合金激光熔覆涂层组织演变及力学性能,采用激光熔覆技术在2Cr25Ni20耐热奥氏体不锈钢表面制备镍基NiCrFeMo高温合金涂层。使用扫描电子显微镜、X射线衍射仪、能量色散光谱仪、显微硬度计等微观分析测试手段对该镍基高温合金涂层的微观组织形貌、物相种类、界面元素分布与偏析、各区域的硬度进行分析。结果表明, 基材与熔覆层结合位置至熔覆层顶部,依次由多种晶粒形态生成;Nb与Mo元素在熔池金属液体对流作用下向基材发生扩散,其它元素基本无扩散;熔覆层存在物相有γ-Ni和Cr₂Fe₁₄C,熔覆层结合位置包含物相Fe₂Ni₃, γ-(Fe, Ni)和Ni_0.9Nb_0.1;基材显微硬度平均值为252HV_0.3左右,熔覆层显微硬度平均值为285HV_0.3左右;经常温拉伸试验,与2Cr25Ni20钢力学性能比较,2Cr25Ni20钢修复件抗拉强度升高,强度增大,断后伸长率明显下降,塑性降低。此研究为后续钢炉转轴修复提供了可行性方案。     

Effect of arsenic implantation on electrical characteristics ofLPCVD WSi2/n-Si Schottky contacts

Electrical characteristics of As-implanted low-pressure chemical vapor deposition (LPCVD) WSi₂/n-Si Schottky barriers are reported. It is shown that As implantation results in a significant Schottky-barrier lowering and an increase in the diode ideality factor n. Silicide annealing prior to As implantation is more effective in reducing Schottky-barrier height. Nearly ohmic characteristics were obtained for As-implanted LPCVD WSi₂ Schottky barriers. Arsenic implanted into high-temperature annealed silicide films was more effective in reducing the effective Schottky-barrier height. Detailed SIMS analysis indicated higher As concentration at the silicide/silicon interface when implanted into high-temperature-annealed silicide films     

Characterization of the Ultrathin HfO2 and Hf-Silicate Films Grown by Atomic Layer Deposition

The physical properties of HfO₂ and Hf-silicate layers grown by the atomic layer chemical vapor deposition are characterized as a function of the Hf concentration and the annealing temperature. The peaks of Fourier transform infrared spectra at 960, 900, and 820 cm_-1 originate from Hf-O-Si chemical bonds, revealing that a Hf-silicate interfacial layer began to form at the HfO₂/SiO ₂ interface after post deposition annealing process at 600 degC for 1 min. Moreover, the intensity of the peak at 750 cm^-1 can indicate the degree of crystallization of HfO₂. The formed Hf-silicate layer between HfO² and SiO² is also confirmed by X-ray photoelectron spectroscopy     

Impact of Crystalline Phase of Ni-FUSI Gate Electrode on Bias Temperature Instability and Gate Dielectric Breakdown of HfSiON MOSFETs

We investigated the influences of gate metals (n⁺/p⁺ poly-Si, Ni silicide (NiSi), Ni₃Si) on the time dependent dielectric breakdown (TDDB) reliability and negative/positive bias temperature instability (NBTI/PBTI) of phase-controlled Ni-full-silicide (Ni-FUSI)/HfSiON/SiO ₂ FETs. The TDDB reliability of NiSi-electrode n-FETs was comparable to that of n⁺-poly-Si-electrode n-FETs. However, further Ni enriching of the electrode to Ni₃Si degraded the reliability. A degradation of the base SiO₂ layer seems to have been responsible for this. A higher compressive strain was observed for the Ni₃Si sample, which may have caused the degradation of the bottom SiO₂. In contrast, the TDDB reliability of p-FETs improved much by using Ni₃Si. We attribute this improvement to the lower cathode energy and/or the absence of boron in the gate electrode. The PBTI of the n-FETs was negligible and was not degraded by Ni enrichment of the gate electrode and additional annealing, suggesting that HfSiON was stable against the Ni-FUSI process. The threshold voltage (V_T) shift in NBTI of p-FETs did not depend much on the gate materials. The major component of the V _T shift in NBTI, however, was changed by Ni enriching from the generation of interface traps to the trapping of holes by the HfSiON bulk     

Investigation of Ti/Al and TiN/Al thin films as the stable ohmic contact for p-type 4H-SiC

Interfacial reactions, surface morphology, and current-voltage (I-V) characteristics of Ti/Al/4H-SiC and TiN/Al/4H-SiC were studied before and after high-temperature annealing. It was observed that surface smoothness of the samples was not significantly affected by the heat treatment at up to 900°C, in contrast to the case of Al/SiC. Transmission electron microscopy (TEM) observation of the Ti(TiN)/Al/SiC interface showed that Al layer reacted with the SiC substrate at 900°C and formed an Al-Si-(Ti)-C compound at the metal/SiC interface, which is similar to the case of the Al/SiC interface. The I-V measurement showed reasonable ohmic properties for the Ti/Al films, indicating that the films can be used to stabilize the Al/SiC contact by protecting the Al layer from the potential oxidation and evaporation problem, while maintaining proper contact properties.     

SiC表面氢化研究

该文提出6H-SiC ( 0001)/SiO2间过渡层的概念和过渡层结构,通过分析过渡层与HF溶液的反应机理,建立湿化学处理中的SiC表面氢化模型。模型以氢钝化SiC表面悬挂键,降低SiC表面的界面态密度,消除了费米能级钉扎,获得理想的SiC表面。将此模型用于SiC/金属接触的SiC表面处理,在100℃以下制备了理想因子n=1.2~1.25的肖特基结和比接触电阻＝510-3 cm2~710-3 cm2的SiC欧姆接触,其优点在于不仅避免了欧姆接触800~1200℃的高温合金,而且改善了肖特基接触的电学特性。SiC表面模型与实验结果吻合较好。