硅片背面减薄技术研究

硅片背面磨削减薄工艺中,机械磨削使硅片背面产生损伤,导致表面粗糙,且发生翘曲变形.分别采用粗磨、精磨、精磨后抛光和精磨后湿法腐蚀等四种不同背面减薄方法对15.24cm(6英寸)硅片进行了背面减薄,采用扫描电子显微镜对减薄后的硅片表面和截面形貌进行了表征,用原子力显微镜测试了硅片表面的粗糙度,用翘曲度测试仪测试了硅片的翘曲度.结果表明,经过粗磨与精磨后的硅片存在机械损伤,表面粗糙且翘曲度大,粗糙度分别为0.15和0.016 μm,翘曲度分别为147和109 μm;经过抛光和湿法腐蚀后的样品无表面损伤,粗糙度均小于0.01 μm,硅片翘曲度低于60 μm.     

硅片抛光

本文侧重介绍了硅片抛光工艺与抛光机理以及硅片抛光剂和硅片抛光表面损伤特性与检测等.     

硅片CMP抛光工艺技术研究

介绍了硅片机械-化学抛光技术,重点分析了10.16 cm硅片抛光加工过程中抛光液的pH值、抛光压力和抛光垫等因素对硅片抛光去除速率及表面质量的影响.通过试验确定了硅片抛光过程中合适的工艺参数,同时对抛光过程中出现的各种缺陷进行了分析总结,并提出了相应的解决方案.     

名词释义——化学机械抛光（CMP）

CMP是利用抛光机、抛光液、抛光垫、抛光布在一定的工艺条件下实现材料表面高平坦化的一种技术。CMP技术来源于硅片抛光工艺 所用的设备和材料都与硅片抛光用的设备、材料等相似。利用这种技术可以使多层SiO2介质平面化和实现多层金属高密度互连，使多层电路结构能在一个近乎平坦的平面上进行制备，加速了低电阻率Cu取代Al作为互连线的步伐，降低了芯片的使用功耗。     

大尺寸硅片背面磨削技术的应用与发展

集成电路芯片不断向高密度、高性能和轻薄短小方向发展，为满足IC封装要求，图形硅片的背面减薄成为半导体后半制程中的重要工序。随着大直径硅片的应用，硅片的厚度相应增大，而先进的封装技术则要求更薄的芯片，超精密磨削作为硅片背面减薄主要工艺得到广泛应用。本文分析了几种常用的硅片背面减薄技术，论述了的基于自旋转磨削法的硅片背面磨削的加工原理、工艺特点和关键技术，介绍了硅片背面磨削技术面临的挑战和取得的新进展。     

硅片表面粗糙度对界面态的影响

针对硅片研磨和抛光产生的亚表面损伤层会影响载流子寿命及界面态的特点,采用机械减薄、机械抛光、化学机械抛光(CMP)制备出不同粗糙度的样品。通过傅里叶红外透射谱分析和C-V 测试分析表明,粗糙度大的硅片表面因表面损伤大,具有更低的红外透射率和更高的界面态密度。     

硅片抛光工艺技术研究

硅片抛光是ＩＣ生产中的重要工序，为提高硅片和ＩＣ产品的质量。本文系统地介绍了ＨＥ系列新型高效抛光剂的制备方法、性能结构、抛光表面质量以及速率等，并探讨了抛光硅片的工艺技术，该技术经国内外几家大型专业厂生产线的实际应用，其效果良好。     

大直径硅晶片化学机械抛光及其终点检测技术的研究与应用

化学机械抛光是硅片全局平坦化的核心技术,然而在实用阶段上,这项技术还受限于一些制造系统整合上的问题,其中有效的终点检测系统是影响抛光成效的重要关键.若未能有效地监测抛光运作,便无法避免硅片产生抛光过度或不足的缺陷.本文在介绍CMP机制与应用的基础上,系统分析了CMP终点检测技术的研究现状及存在的问题.     

背照式CMOS图像传感器的硅减薄湿法刻蚀工艺

针对背照式CMOS图像传感器制作工艺,提出了一种采用氢氧化四甲基铵液进行湿法刻蚀的背部硅片减薄工艺。分析了硅减薄工艺的整体流程,针对化学机械研磨后的湿法刻蚀工艺进行了实验。通过调整反应时间、硅片转速、喷嘴速度和摆幅,得到最优刻蚀参数,使厚度均值达到目标值,平整度控制在一定范围内。该湿法刻蚀工艺中,首先对硅片表面形貌进行修正,接着对硅片进行整体刻蚀,达到目标厚度,最后通过减薄得到BSI背部硅片。采用该硅片制作的图像传感器的成像质量得到提高。     

超薄硅双面抛光片加工效率的提升

用于5G通信芯片支撑层的超薄硅双面抛光片的生产是一个需要攻克的难题。该产品的技术难点在于,硅片厚度低至100μm,薄如纸张,采用传统粘蜡抛光工艺,加工效率极低且碎片率极高,同时硅片几何参数无法保证,成品率较低。由于磨削工艺可有效减少硅片表面的损伤层、改善几何参数,所以针对超薄硅片的加工,采用贴膜抛光工艺可以保证抛光的效率和成品率。在硅片腐蚀后采用磨削+贴膜抛光的工艺,解决了超薄硅双抛片加工效率低、碎片率高、几何参数难以保证、成品率低的问题。     

300mm硅片化学机械抛光技术分析

化学机械抛光是单晶硅衬底和集成电路制造中的关键技术之一,然而,传统的化学机械抛光技术还存在一定的缺点或局限性,为了得到更好的硅片平整度和表面洁净度,在300mm硅片的生产中采用了双面化学机械抛光技术.对双面化学机械抛光的优点以及系统变量对抛光速度和抛光质量的影响进行了详细地分析.     

硅/玻璃紫外固化中间层键合

利用玻璃的透光特性和紫外固化的成熟技术,研究了一种使用紫外固化胶作为中间层的玻璃/硅室温键合工艺.通过选择一定波段的紫外固化胶,旋涂紫外胶后使用365nm光刻机作为紫外光源控制紫外固化,从而实现了硅/玻璃的中间层键合.分析测试结果表明,紫外固化辅助的中间层键合可以成功应用于硅/玻璃键合,中间层厚5～6μm,键合强度达到26MPa.该工艺只需室温条件,简单高效,成本低廉,无需额外的压力或电场,对于硅/玻璃低温键合封装具有潜在的应用价值.     

基于阳极键合的硅微圆盘多环谐振陀螺的设计与制作

提出了一种新型的基于阳极键合的硅微圆盘多环谐振陀螺的结构设计及其制作方法.该种陀螺采用MEMS工艺制作而成,基底材料为肖特BF33玻璃,电极和谐振器均由单晶硅片加工而成,肖特BF33玻璃与单晶硅片通过阳极键合工艺键合在一起.介绍了该种陀螺的基本结构、工作原理,并进行了仿真分析,得出该种陀螺具有较小的频率分裂,表现出陀螺效应.最后,通过MEMS工艺进行了实际加工,得到了该种陀螺的实验样品.     

One-mask process for silicon accelerometers on Pyrex glass utilising notching effect in inductively coupled plasma DRIE

A one-mask process technology is proposed to fabricate silicon capacitive accelerometers using comb drive structures. A doped silicon wafer is anodically bonded on Pyrex glass substrate. High aspect ratio silicon accelerometer structures are micromachined using deep reactive ion etching (DRIE) and released from the glass substrate by further DRIE due to its notching effect.     

A Two-Wafer Approach for Integration of Optical MEMS and Photonics on Silicon Substrate

This letter reports a novel two-wafer approach which demonstrates an integration of optical microelectromechanical system (MEMS) devices and photonics on a silicon substrate. The great advantage of this novel wafer bonding scheme is the ability to maintain the optical axis of the optical MEMS device at the same axis as the optical components. The bonded two wafers which are partially processed, which allows for further processing on the wafer after bonding. Thus, the critical alignment issue is resolved for devices requiring precise alignment in x-/y-/z-axis. Individual functionalities of optical MEMS device and optical coupling between silicon waveguide, fibers and ball lens are demonstrated. This technology shows the potential for integrating silicon photonics integrated circuit and MEMS components with reconfiguration functions on a single silicon substrate.      

High-performance inductors on plastic substrate

Wafer-transfer technology (WTT) has been applied to transfer RF inductors from a silicon wafer to an opaque plastic substrate (FR-4). By completely eliminating silicon substrate, the high performance of integrated inductors (Q-factor > 30 for inductance /spl sim/3 nH with resonant frequency /spl sim/23 GHz) has been achieved. Based on the analysis of a modified /spl pi/-network model, our results suggest that the performance limitation is switched from being a synthetic mechanism of substrate and metal-ohmic losses on low resistivity Si-substrate to merely a metal-ohmic loss on FR-4. Thus, the inductor patterns, which are optimized currently for RFICs on silicon wafer, can be further optimized to take full advantage of the WTT on new substrate from the newly obtained design freedom.     

Substrate transfer for RF technologies

The constant pressure on performance improvement in RF processes is aimed at higher frequencies, less power consumption, and a higher integration level of high quality passives with digital active devices. Although excellent for the fabrication of active devices, it is the silicon substrate as a carrier that is blocking breakthroughs. Since all devices on a silicon wafer have a capacitive coupling to the resistive substrate, this results in a dissipation of RF energy, poor quality passives, cross-talk, and injection of thermal noise. We have developed a low-cost wafer-scale post-processing technology for transferring circuits, fabricated with standard IC processing, to an alternative substrate, e.g., glass. This technique comprises the gluing of a fully processed wafer, top down, to an alternative carrier followed by either partial or complete removal of the original silicon substrate. This effectively removes the drawbacks of silicon as a circuit carrier and enables the integration of high-quality passive components and eliminates cross-talk between circuit parts. A considerable development effort has brought this technology to a production-ready level of maturity. Batch-to-batch production equipment is now available and the technology and know-how are being licensed. In this paper, we present four examples to demonstrate the versatility of substrate transfer for RF applications.     

焊球阵列转变与绝缘基板技术

在半导体整体的焊球阵列封装(BGA)领域,一份针对数个关键封装形式所进行的分析报告中,显示了造成不同焊球阵列封装形式成长或下跌的原因,并更清楚地点出了目前使用的数种基板技术的缺点。这篇分析报告列出了主要的焊球阵列封装的形式和基板发展潮流,还清楚地指出焊球阵列封装整体的发展延缓了硅芯片技术的演进,这在某些BGA领域中尤其明显,主要是因为缺乏先进的基板技术。因此文后得出结论,封装产业供货供应链基板市场中可能出现新的厂商,其也许来自主机板市场。     

Fabrication and Characterization of 150-mm Silicon-on-Polycrystalline Silicon Carbide Substrates

Silicon-on-insulator (SOI) substrates can reduce radiofrequency (RF) substrate losses due to their buried oxide (BOX). On the other hand, the BOX causes problems since it acts as a thermal barrier. Oxide has low thermal conductivity and traps heat generated by devices on the SOI. This paper presents a hybrid substrate which uses a thin layer of polycrystalline silicon and polycrystalline silicon carbide (Si-on-poly-SiC) to replace the thermally unfavorable BOX and the silicon substrate. Substrates of 150 mm were fabricated by wafer bonding and shown to be stress and strain free. Various electronic devices and test structures were processed on the hybrid substrate as well as on a low-resistivity SOI reference wafer. The substrates were characterized electrically and thermally and compared with each other. Results showed that the Si-on-poly-SiC wafer had 2.5 times lower thermal resistance and exhibited equal or better electrical performance compared with the SOI reference wafer.     

HF/O3在300mm硅片清洗中的应用

随着半导体技术的不断发展,集成电路的线宽在不断减小,对硅抛光片表面质量的要求也越来越高,传统的RAC清洗方法已不能满足其需求,因此,必须发展新的清洗方法.本文对传统的RCA清洗方法进行了简单的介绍,分析了其中的不足之处,在此基础上,对新发展的HF/O3槽式清洗法和HF/O3单片清洗法进行了详细的说明,从而对300mm硅片清洗方法的未来发展方向进行了简单论述.