压力传感器的LED排光柱显示装置

外加电压通过热灵敏度漂移补偿自平衡电桥对压力传感器进行激励,其输出信号经热零点多补偿自平衡电桥电路后。用仪用放大器放大到满量程达５Ｖ电路,然后输送到比较电路。依据发光的ＬＥＤ个数可判断被测压力的大小。     

单片集成压力传感器及弱信号处理电路的设计

通过分析硅压敏电阻与晶向的关系,找到力敏电阻在硅膜片上的最佳位置。经测量,在10～400kPa范围内,压阻电桥的灵敏度约为0.36mV/kPa。提出一种由惠斯登电桥双端输出和双级放大器组成的电路结构,以对称的输入结构和全摆幅输出,解决了传感器输出小、易产生零点漂移的问题。用Cadence软件对电路进行模拟,在5V电源电压下,该放大电路的输出范围为0.036～4.953V,开环增益为110dB,CMRR为105.8dB,相位裕度为63.68°,可满足压力传感器的要求。     

压电式压力传感器温度补偿算法的研究

介绍了压电式压力传感器由于受工作环境温度的影响,其零点和灵敏度常会发生漂移,因此,需对其进行补偿;讨论了一种基于最小二乘法的补偿算法,运用该算法对温度变化后的数据进行处理,使传感器的输出基本不随温度的变化而改变,从而使传感器的零点漂移和灵敏度漂移问题得到了很好地解决。结果表明,该算法能起到很好的补偿效果并广泛应用于工程实践中。     

一种新型的Pt-NiO混合敏感膜全固态 溶解CO2传感器及其特性测量

为了方便的测量溶解二氧化碳(CO₂),利用室温下NiO对CO₂的敏感特性,基于碳糊成膜方法,研制了一种新型全固态溶解CO₂传感器.文章中,分析了传感器的结构和NiO敏感膜对CO₂的敏感机理,测量了不同工作点和不同温度下传感器输出电压ΔV_rs随着溶解CO₂浓度变化的响应特性.实验结果显示,基于MISFET结构的Pt-NiO混合敏感膜溶解CO₂传感器可以在室温下方便的检测溶解CO₂浓度.     

通过信号分离抑制离散变化变量传感器漂移噪声

在传感器的输出信号中,漂移噪声是一阶或一阶以上连续的,而在有的传感器中,传感量的变化在时间轴上是离散的,正是基于这两个显然不同的信号特征,本文提出在这类传感器中,利用输出采样的差分值,从传感器输出中将传感信号和漂移信号分离,不采用任何其它的漂移变量补偿元件和电路,可以消除零点漂移,补偿灵敏度漂移。     

一种硅压阻式压力传感器温度补偿算法及软件实现

硅压阻式压力传感器的零点温度漂移和灵敏度温度漂移是影响传感器性能的主要因素之一,如何能使该类误差得到有效补偿对于提高其性能很有意义。通过对硅压阻式压力传感器建立高阶温度补偿模型进行温度误差补偿是一种有效的方法,并在该模型基础上给出了拟合系数计算方法,并用Matlab GUI软件来实现温度补偿系数计算,进而实现传感器输出的动态温补,达到了很好的输出线性性。实验结果表明,补偿后传感器输出的非线性误差小于0.5% F.S。     

用于高温压力传感器的AlN绝缘膜的研究

采用直流磁控反应溅射法制备了高温压力传感器用的AlN薄膜.用X射线衍射对薄膜的晶向结构进行了分析,研究了薄膜的绝缘特性和化学稳定性,分析了AlN与Si的热膨胀系数、热导系数的关系.选用AlN在力敏电阻条和硅弹性膜之间进行绝缘隔离,由于无p-n结,力敏电阻无反向漏电,得到了极好的压力传感器特性,即零点电漂移及热漂移小及非线性小.     

光纤光栅传感器在石油测井中的应用

介绍一种新型光纤布拉格(Bragg)光栅油井温度/压力传感器.在详细分析光纤光栅温度、应力传感原理的基础上,设计了适合于井下温度、压力参数测量的传感器.通过温度和压力实验推导了传感器波长与温度、压力之间的关系,得到了压力响应灵敏度的解析表达式.该传感器可实现温度和压力同时测量.现场实验证明:温度测量范围为10～100℃,温度灵敏度为0.0213=nm/℃;在0～20MPa的压力变化范围内,压力灵敏度达0.1631nm/Mpa,能够很好地满足油井井下测量的要求.     

一种单片集成压力传感器信号调理电路的设计

针对单片集成压力传感器输出幅度较小、温度漂移会引起压力精度变化等难题,提出了一种新型的信号调理电路。该电路通过两个差分放大电路和四个D/A转换器来解决单片集成压力传感器的小输出和温度漂移问题。仿真结果表明,在5 V电源电压下,在0 ℃～85 ℃温度范围内,信号调理电路的最大误差可以减少到满量程输出的1.8 %。     

一种单片集成压力传感器信号调理电路的设计

针对单片集成压力传感器输出幅度较小、温度漂移会引起压力精度变化等难题,提出了一种新型的信号调理电路。该电路通过两个差分放大电路和四个D/A转换器来解决单片集成压力传感器的小输出和温度漂移问题。仿真结果表明,在5V电源电压下,在0℃~85℃温度范围内,信号调理电路的最大误差可以减少到满量程输出的1.8%。     

10Gb/s光调制器InGaP/GaAs HBT驱动电路的研制

采用自行研发的4英寸InGaP/GaAs HBT技术,设计和制造了10Gb/s光调制器驱动电路.该驱动电路的输出电压摆幅达到3V_pp,上升时间为34.2ps(20~80%),下降时间为37.8ps(20~80%),输入端的阻抗匹配良好(S11=-12.3dB@10GHz),达到10Gb/s光通信系统(SONET OC-192,SDH STM-64)的要求.整个驱动电路采用-5.2V的单电源供电,总功耗为1.3W,芯片面积为2.01×1.38mm².     

压力传感器灵敏度电压非线性分析

实验发现压阻型压力传感器的压力输出信号与外加电压并不是线性关系,存在着灵敏度电压非线性。本文指出组成压阻型压力传感器电桥的电阻受温度、输入电压、压力的共同影响,在此基础上提出非线性扩散电阻的多维模型。依据此理论模型,对灵敏度电压非线性现象的成因进行了理论分析,并利用其中受电压控制的电压源及其扩展功能来模拟非线性扩散电阻在电路的等价作用,进而显示出压力传感器灵敏度电压非线性的成因。     

一种新型MOSFET静电场传感器

本文提出了一种非常有发展前途的低温漂固态电场传感器。此传感器是一种恒压惠斯顿电桥,它的电阻是由四个直接栅极SOI MOSFET器件。理论上证明这种传感器的输出信号电压与测量电场成正比,温度漂移等于零。实验结果表明,在300K温度下,传感器的分辨率为3.27 mV/KV/m,大气环境下的温度漂移相当于47V/m的电场,其远小于大气温度下相当于10,000V/m的电流漂移。     

A novel SOI MOSFET electrostatic field sensor

A novel low temperature solid state electric field sensor is demonstrated as a promising sensor. The sensor is a type of constant voltage Wheatstone bridge whose resistors are four direct gate SOI MOSFET devices. It is demonstrated in theory that the output voltage signal is proportional to the electric field E, the temperature drift is about zero when the temperature is in the range from 200 to 400 K, and the doping concentration is in the range from 1×1014 to 1 × 1016 cm-3. The experiment results indicate that the resolution of the sensor is about 3.27 mV for a 1000 V/m electric field at 300 K, and the voltage drift by an amount is about 47 V/m field signal when the degree temperature is in the range from 300 to 370 K, which is much smaller than the current drift of a single MOSFET which is about 10000 V/m field signal.     

A new low power multiplexer based ternary multiplier using CNTFETs

In the following paper, a single bit ternary multiplier utilizing carbon nanotube field-effect transistor (CNTFET) has been presented. Almost in the ternary circuit design, only one supply voltage V_DD is used and a voltage division circuit is activated to produce V_DD/2 for logic ‘1’, So the direct current from V_DD to ground increases the static power considerably. In This paper, using two supply voltages, V_DD and V_DD/2, the circuit is designed so as V_DD/2 could be transmitted to output directly for logic ‘1’ to eliminate direct current from source to ground. This is provided by proper division of truth table and using two level output gates. Also for extending to multi bit multiplier in this way, three type of half adders and one full adder are designed using two supply voltages and removing direct current. The implementation for two bits is reported. The results of simulation, using Hspice software and Stanford 32 nm CNTFET library with the voltage of 0.9 (v), as expected, indicate much lower power dissipation and power delay product (PDP) in comparison with the previous works.     

叠加电桥检测的加速度传感器的设计

This paper describes the design,simulation,processing and test result of a high sensitivity accelerometer based on the piezoresistive effect which uses an overlay bridge detection method.The structure of this accelerometer is supersymmetric "mass-beams".This accelerometer has 8 beams,where two varistors are put in the two ends.Four varistors compose a Wheatstone bridge and the output voltages of the 4 Wheatstone bridges have been superimposed as the final output voltage.The sensitivity of the accelerometer can be improved effectively by these clever methods. A simplified mathematical model has been created to analyze the mechanical properties of the sensor,then the finite element modeling and simulation have been used to verify the feasibility of the accelerometer.The results show that the sensitivity of the accelerometer is 1.1381 m V/g,which is about four times larger than that of the single bridge accelerometers and series bridge sensor.The bandwidth is 0-1000 Hz which is equal to that of the single bridge accelerometers and the series bridge sensor.The comparison reveals that the new overlay detection bridge method can improve the sensitivity of the sensor in the same bandwidth.Meanwhile,this method provides an effective method to improve the sensitivity of piezoresistive sensors.     

A New SOI LDMOSFET Structure with a Trench in the Drift Region for a PDP Scan Driver IC

To improve the characteristics of breakdown voltage and specific on‐resistance, we propose a new structure for a LDMOSFET for a PDP scan driver IC based on silicon‐on‐insulator with a trench under the gate in the drift region. The trench reduces the electric field at the silicon surface under the gate edge in the drift region when the concentration of the drift region is high, and thereby increases the breakdown voltage and reduces the specific on‐resistance. The breakdown voltage and the specific on‐resistance of the fabricated device is 352 V and 18.8 m·cm² with a threshold voltage of 1.0 V. The breakdown voltage of the device in the on‐state is over 200 V and the saturation current at V_gs=5 V and V_ds=20 V is 16 mA with a gate width of 150 µm.     

A programmable voltage reference optimized for power management applications

A 3-bits programmable, low drift, high PSRR and high precision voltage reference, optimized for Power Management (PM) applications, is presented. The topology is based on a high-performance bandgap voltage reference that presents a PSRR of up to 80 dB, which is required in PM applications, because they employ mixed-signal circuits, where high frequency switching noise is present. The proposed approach was successfully verified in a standard 0.35 μm CMOS process. The experimental results confirmed that, for power supply between 3.0 and 3.3 V, and temperatures in ?20°C to 80°C range, the programmable output voltage V _REF exhibits a worst case precision of ±3%.     

A simple division circuit

The design of a simple circuit, which can divide one voltage V₂ by another V V₁, is described. The circuit employs two operational amplifiers, a comparator and a programmable unijunction transistor (PUT). The output V V₀ is in the form V₀ = K( V V₂/ V V₁). where K is a constant which can be programmed through the PUT.     

Collector models for bipolar transistors

Using Ryder's formula for drift velocity vs. electric field, the d.c. field and carrier densities in the collector of a bipolar transistor are calculated analytically for all possible bias conditions. This is accomplished by modeling the majority carrier distribution. The results are compared with computer calculations and fairly close agreement is found. The analytic calculations are used to make a detailed division of the (J_c, V_cb) plane into injection, depletion and scattering-limited drift velocity (SLDV) areas. It turns out that the doping level N_d and the collector width W determine the nature of this division of the (J_c, V_cb) plane.