Fundamental characteristics of DRAM capacitor application of PLZT ultrathin films prepared by MOCVD

Lanthanum-modified lead zirconate titanate (PLZT) thin films (50 nm to 200 nm) were deposited on Pt/SiO₂/Si substrate by metal-organic chemical vapor deposition (MOCVD). The electrical properties of the films were investigated as a function of the La content or the substrate temperature. Ferroelectric PZT(0/50/50) films were obtained at substrate temperatures as low as 500 °C; their electrical characteristics improved with increasing substrate temperature. La exhibited adequate solid solution in the PZT above 650 °C. PLZT(15/45/55) films with a thickness of 100 nm were found to have good properties for application to the capacitors of dynamic random access memory (DRAM), namely, an effective charge density of 80 fF/μm², a permittivity of 1000, an SiO₂ equivalent thickness of 0.4 nm, and a leakage current density of 5 × 10⁻⁸ A/cm. Addition of La to PZT was effective in reducing the leakage current with an increase in the registration rate. RuO₂ and/or IrO₂ bottom electrodes for ferroelectric PLZT films were also investigated. The RuO₂ films were found effective as diffusion barriers for PLZT and MgO. Significant interdiffusion at RuO₂/Si and RuO₂/SiO₂ interfaces occurred during the deposition of PLZT films. Annealing of the RuO₂ film considerably depressed interface reactions. © 1998 Scripta Technica. Electr Eng Jpn, 122(1): 25–36, 1998     

Liquid source chemical vapor deposition of high-dielectric-constant (Ba,Sr)TiO3 films

High-dielectric-constant (Ba, Sr)TiO₃ [BST] films were deposited by the liquid source chemical vapor deposition (CVD) method. The system consisted of a single-wafer, low-pressure thermal CVD reactor, a vaporizer for liquid source materials, and a shower-type gas nozzle head, giving stable BST film deposition on a 6-in. diam. substrate with uniform thickness and uniform chemical composition ratio. The source materials employed were Ba(DPM)₂, Sr(DPM)₂, and TiO(DPM)₂ dissolved in tetrahydrofuran (THF), resulting in conformal step coverage of BST films at lowered substrate temperatures, where DPM denotes dipivaloylmethanate. Moreover, the two-step deposition technique was developed to restart protrusions formed on BST film surfaces at low temperatures, where the BST films consisted of a buffer layer and a main layer; the buffer layer was a layer about 60 Å thick of CVD-BST film annealed in N₂. Thus, the two-step CVD deposition of BST films on Pt and Ru electrodes achieved an equivalent SiO₂ thickness of t_eq ∼ 0.5 nm, a leakage current of J_L ∼ 1.0 × 10⁻⁸ A/cm² (at +1.1 V), and a dielectric loss of tan δ ∼ 0.01 at a total film thickness of 250 Å, along with conformal coverage of 80% for a trench with an aspect ratio of 0.65. Then, for BST films deposited on patterned electrodes 0.24 μm wide, 0.60 μm deep, and 0.15 μm high (each spaced by 0.14 μm), the capacitance was demonstrated to be increased without significant deterioration of the leakage current: the capacitance was increased in comparison with that for films on flat electrodes, by a factor corresponding to the increase in surface area due to sidewalls of storage-node-like pattern features. This capacitance increase reflects the most characteristic advantage of CVD, an excellent step coverage on microscopic pattern features. These electrical properties satisfy the specifications for capacitors for Gb-scale dynamic random access memories (DRAMs), giving a storage capacitance of more than 25 fF/cell for a stacked capacitor having a storage node 0.2 to 0.3 μm high. © 1998 Scripta Technica, Electr Eng Jpn, 125(1): 47–54, 1998     

Trends in the development of ULSI DRAM capacitors

Abstract

DRAM manufacturers face a tremendous challenge to keep the DRAM cell capacitance constant from generation to generation. The 256 Mb DRAM will certainly represent the last DRAM generation to use the standard storage dielectric materials consisting of silicon dioxide and silicon nitride. These materials cannot be shrunk further, and the capacitor area cannot be kept constant in a manufacturable cell. The most promising approach to keep cell capacitance constant in future DRAM generations, beyond 256 Mb, is to develop and integrate high dielectric constant materials.     

Characterization of MOCVD Pt electrode for ferroelectric thin films

Abstract

Platinum thin films were deposited by low pressure chemical vapor deposition (LPMOCVD) on SiO₂/Si and (Ba, Sr)TiO₃/Pt/SiO₂/Si substrates using Pt-hexafluoroacetylacetonate at various deposition temperatures. The shiny mirror-like Pt thin films of a high electrical conductivity were obtained, when the deposition temperature is between 325°C and 350°C, whereas above 375°C Pt thin films showed rough surface as well as poor adhesion property to oxide substrate. Pt thin films had a good step coverage of 90%. The results indicate that LPMOCVD Pt thin films can be applied for the top electrode of high dielectric thin film, which is thought to be one of the best candidate materials for a capacitor of ULSI DRAM.     

The effects of forming gas anneal on the electrical characteristics of ir-electroded BST thin film capacitors

Abstract

The effect of various temperature nitrogen anneals prior to top electrode deposition on the ability of Ba_0.7Sr_0.3TiO₃ (BST) thin-film capacitors with both Ir and Pt top electrodes to withstand hydrogen damage was investigated. Experimental results show that samples that underwent a 750 °C N₂ pre-top electrode anneal exhibited the lowest leakage current density at positive bias for both Ir- and Pt-electroded devices after forming gas anneal. It was also found that DRAM polarization values decreased slightly after forming gas anneal. Also, a post-top electrode deposition 550°C O₂ anneal improved both electrical characteristics (lowered leakage and increased DRAM polarization) of these devices. Complete recovery of the leakage level prior to hydrogen damage was obtained after a 550°C N₂ recovery anneal for some devices independent of the pre-top electrode anneal. Ir- and Pt-electroded BST (40nm) capacitors have been shown to meet the 1 giga-bit DRAM leakage current requirement of 10^?8 A/cm² at 1.7 V. These Ir- and Pt-electroded BST devices achieved capacitance density levels of approximately 50 fF/μm².     

Characterization of hetero-epitaxial PZT capacitor

Abstract

A hetero-epitaxial Au/PbZr_0.48Ti_0.52O₃(PZT)/SrRuO₃(SRO) capacitor was fabricated on a single crystal SrTiO₃ (STO) substrate by pulsed laser deposition. An SRO buffer layer (a nucleation layer) was formed at the SRO/STO interface to ensure the highly epitaxial growth of the PZT and SRO films. An X-ray diffraction measurement revealed that the (00l) planes of the PZT and SRO grew parallel to the substrate surface. A transition layer of ～ 5 nm thickness was observed at the SRO/STO interface by high-resolution transmission electron microscopy (HR-TEM). This transition layer corresponds to the nucleation layer intentionally grown at the interface. Remanent polarization of the capacitor was 32.1 μC/cm² due to the good epitaxial growth of the films.     

SrTiO3 thin films by mocvd for 1 gbit DRAM application

Abstract

Three important aspects of the preparation of SrTiO₃ thin films by MOCVD are discussed in detail in view of the application of these films as the capacitor dielectric of Gbit-scale DRAMs: CVD reactions in the Sr(DPM)₂-Ti(i-OC₃H₇)₄-O₂ system, step coverage and relations between microstructure and electrical properties. The effect of the substrate temperature on the Sr and Ti deposition rates was first investigated for thermal and ECR CVD SrTiO₃ films. SrO and TiO₂ deposition by thermal CVD above 550°C were found to be controlled by the surface reaction and gas transport, respectively, whereas both SrO and TiO₂ deposition are controlled by gas transport for ECR CVD at 450 to 600°C. The influence of the Sr and Ti deposition regimes on the step coverage of SrO, TiO₂ and SrTiO₃ were then assessed. SrO films prepared by thermal CVD at 600°C exhibited the best step coverage, indicating that a relation exists between reaction controlled deposition and good step coverage. The effect of the film composition and film thickness on the microstructure of SrTiO₃ thin films were finally investigated and correlations were made to other analyzed physical and electrical properties. Polycrystalline perovskite phase SrTiO₃ films were obtained for a composition 0.7 ≤ Sr/Ti ≤ 1.2. The best crystallinity, maximum permittivity and maximum refractive index were obtained for Sr/Ti = 0.95. Titanium rich films are thought to be composed of a mixture of a titanium rich amorphous phase and crystalline SrTiO₃, and strontium rich films are believed top correspond to a (SrTiO₃)_m (SrO)_n structure. The dielectric constant slowly decreased as the film thickness was reduced. The sharp decrease observed near 400–500 Å could be due to the existence of some perturbed layer at the interface with one or both of the electrodes     

Preparation of BST thin films on Pt electrode on Si wafer with down-flow LSMCVD reactor

Abstract

A novel type of down-flow LSMCVD (Liquid Source Mist CVD) reactor was developed to prepare a high dielectric BST thin film on Pt electrode on Si wafer. Barium acetate [Ba (OOCCH₃)₂], strontium acetate [Sr (OOCCH₃)₂], and titanium isoproxide [Ti (OC₃H₇ ⁱ )₄] were used as metal sources. Metal sources were dissolved in acetic acid, 1-butanol, or 2-methoxyethanol. BST [Ba/(Ba + Sr) = 0.7] film annealed on Pt/Ti/SiO₂/Si above 650°C was polycrystalline. BST film has a (110) preferred orientation with increasing temperature. Surface roughness of BST film and grain size increased with increasing temperature. The metal-oxygen bond was formed at 650°C as shown in the spectra of FTIR. The depth profiles of elements of BST thin films indicated a uniform composition throughout the film. BST films annealed at 750°C showed a dielectric constant and a tanδ of 390 (thickness: 150 nm) and 0.06 at a frequency of 100 kHz, respectively. The behavior of capacitance of the BST film with bias voltage showed paraelectric property. BST film annealed at 750°C had the leakage current density of 3.2 (μA/cm²) at a bias voltage of 2V.     

CHARACTERISTIC OF (100)-TEXTURED (PbxSr1 −x)TiO3 THIN FILMS USED FOR DRAM AND TUNABLE DEVICE APPLICATION

ABSTRACT

The (Pb_xSr_1-x)TiO₃ (PST) thin films were deposited on LaNiO₃ (LNO(1 0 0))/ Pt/Ti/SiO₂/Si substrates electrode by RF-magnetron sputtering using three different Pb target composition ranging from 32.5%～37.5% and different process condition. Structural and dielectric properties of the PST thin films for tunable microwave and DRAM application were investigated. The PST thin films deposited at 400°C show higher dielectric constant than those post-annealed at 600°C because of better crystallization. The former also have lower leakage current around 10^?8 A/cm² up to applied field of 350 kv/cm, which is suitable for DRAM application. On the other hand, the post-annealed PST thin films have satisfactory tunability around 58% and figure of merit around 30, which are more suitable for microwave device application.     

Chemical Vapor Deposition of Ru Bottom Electrode for Ferroelectric Bi4 − x La x Ti3O12 Capacitors

Ruthenium films formed by metalorganic chemical vapor deposition were investigated, taking account of the application to the bottom electrode of ferroelectric capacitors. Ruthenium films were deposited using a liquid-type source of Ru[EtCp]₂ in a cold-wall type reactor with infrared lamps. A smooth and flat Ru film was successfully formed on a SiO₂-covered Si substrate without a seed layer. As the deposition temperature increased to 400°C, the crystallinity of the Ru film improved and the film exhibited high c-axis orientation. After forming a Bi_{4 ? x} La _x Ti₃O₁₂ (BLT) film by a sol-gel technique, a Pt/BLT/Ru capacitor was fabricated on the Ru film. Good hysteresis loops with 2P _r = 20 μC/cm² and 2V _c = 3.4 V were successfully obtained and the ferroelectric property did not depend on the deposition temperature of Ru in the temperature range from 325°C to 400°C. On the contrary, the leakage current density was significantly suppressed down to 1/100 as the deposition temperature of Ru increased from 325°C to 400°C.     

The effect of deposition temperature on the material and electrical properties of PZT thin films for ULSI DRAM applications

Abstract

The effects of deposition temperature on the properties of thin films of sputtered lead-zirconate-titanate (PZT) have been studied for ULSI DRAM storage capacitor dielectric applications. The films were deposited by reactive dc magnetron sputtering from a multi-component target. The grain size for the films deposited at 400°C was found to be less than 1000 Å, while it was ～ 10–30 μm for films deposited at 200°C. Small grain-sized material is desirable since it leads to better cell-to-cell uniformity in terms of charge storage capacity and other electrical and reliability properties. The optimum lead compensation was found to increase as the deposition temperature (T _dep) increased. Leakage current density stays fairly constant as T _dep is varied. As-deposited films, with a deposition temperature of 500°C, were rich in the perovskite phase and showed a high charge storage density of 11.2 μC/cm² and a low leakage current density of 5.1 × 10^?7 A/cm² (both at 1.5 V). This implies the possibility of eliminating the high temperature crystallization-annealing step.     

Microstructural Properties of Ba0.6Sr0.4TiO3/RuO2 Multi-Layers Grown on MgO and YSZ by Pulsed-Laser Deposition

The microstructure of Ba_0.6Sr_0.4TiO₃ (BST)/RuO₂ multi-layers grown on (100) MgO and (100) YSZ substrates, respectively, by pulsed-laser deposition (PLD) has been studied by transmission electron microscopy (TEM) and high-resolution electron microscopy (HREM). The RuO₂ films deposited at 700°C adopt epitaxial relationships with both substrates. The epitaxial films on (100) MgO consist of two variants with an orientation relationship given by (110) RuO₂//(100) MgO and [001] RuO₂//[011] MgO. The epitaxial films on (100) YSZ contain four variants with an orientation relationship given by (200) RuO₂//(100) YSZ and [011] RuO₂//[001] YSZ. The BST films deposited on the RuO₂ electrode are epitaxial on the (200) RuO₂ films deposited on YSZ, and non-epitaxial on the (110) RuO₂ films deposited on MgO. The epitaxial relationship between the BST and (200) RuO₂ films can be described as (111) BST//(200) RuO₂ and [1&1macr;0] BST//[011] RuO₂. The BST films contain at least four variants. The growth and microstructural properties of the multi-layer structures can be understood based on geometrical consideration of the crystal structures.     

Current Conduction and Dielectric Behavior of High k-Y2O3 Films Integrated with Si Using Chemical Vapor Deposition as a Gate Dielectric for Metal-Oxide-Semiconductor Devices

Integration of Y₂O₃ high-k thin film over Si as gate dielectric in high performance CMOS and high-density MOS memory storage capacitor devices is described. Y₂O₃ film growth by low-pressure chemical vapor deposition induces interfacial reactions and complex SiO_{2 – x} layer growth. It has a graded structure, in crystalline-SiO₂ form at Y₂O₃ side and amorphous SiO_{2 – x} form at Si side. MIS devices based on Y₂O₃/SiO₂-SiO_{2 – x} composite dielectric integrated with Si show high frequency C-V behavior indicative of inversion to accumulation changes in capacitance. Observed bi-directional hysterisis in C-V is detrimental to the functioning of storage capacitor in memory function. Detailed investigation of this effect led to understanding of gate bias controlled emission of carriers as responsible mechanism. Observed anomalous increase in inversion capacitance at low frequency is attributed to additional charges transferred from SiO_{2 – x}/Si interface states. Leakage current and injected charge carrier transport across bilayer interface is dominated by Poole-Frankel (PF) process at low fields and by Fowler-Nordhiem (FN) at high fields. This investigation provides a greater understanding of the complex nature of integration of Y₂O₃ films.     

Dielectric properties of nanocrystalline TiO2 prepared using spark plasma sintering

Ultra fine rutile powders (below 50 nm) were prepared via the sol-gel process and bulk type TiO₂ specimens were fabricated using spark plasma sintering (SPS). The TiO₂ specimen sintered at a low temperature (720^∘C) exhibited a highly relative density (97%) and a nano-sized grain structure (200 nm). Dielectric properties of spark plasma sintered TiO₂ specimens including dielectric constants (k) and losses (tan δ) were measured. The TiO₂ specimen, obtained by SPS, showed a high dielectric constant (∼780) and a low tan δ (∼0.005), and a relaxation behavior at 1 MHz. After the subsequent annealing process of the TiO₂ specimen in O₂ flow, the dielectric constants remarkably decreased (k = 100s). These dielectric properties of nanocrystalline TiO₂ specimens prepared by SPS were discussed in terms of space charges produced by the reduction of Ti⁴⁺ ions and crystallographic orientations of grains.     

Electrodes for ferroelectric thin films

Abstract

Platinum and ruthenium oxide (RuO₂) deposited by ion beam sputter-deposition are evaluated for use as electrodes for PZT thin film capacitors. The effect of deposition temperature, film thickness, and the presence of oxygen on hillock formation in platinum is discussed. It is shown that the hillock density in Pt/Ti/SiO₂/Si films can be significantly reduced by properly controlling the processing conditions and film thickness. Stress measurements correlate with the experimental observation that depositing thinner platinum films (<800 Å) is an effective means of reducing hillock formation. The use of an intermediate deposition temperature 200–250°C also helps minimize hillock formation. Diffusion of the Ti adhesion layer into and/or through the platinum was significantly reduced by replacing the Ti with a TiO_x adhesion layer. RuO₂ electrodes are compared to Pt in terms of resistivity, surface morphology, microstructure and film orientation.     

Interface potential barrier height and leakage current behavior of Pt/(Ba,Sr)TiO3/Pt capacitors fabricated by sputtering process

Abstract

Variations of the leakage current behaviors and interface potential barrier height (φ _B ) of rf-sputter deposited (Ba, Sr)TiO₃ (BST) thin films, with thickness ranging from 20nm to 150 nm are investigated as a function of the thickness and bias voltages. The top and bottom electrodes are dc-sputter-deposited Pt films. φ _B critically depends on the BST film deposition temperature, postannealing atmosphere and time after the annealing. The postannealing under N₂ atmosphere results in a high interface potential barrier height and low leakage current. Maintaining the BST capacitor in air for a long time reduces the φ _B from about 2.4 eV to 1.6eV due to the oxidation. φ _B is not so dependent on the film thickness in this experimental range. The leakage conduction mechanism is very dependent on the BST film thickness; the 20nm thick film shows tunneling current, 30 and 40 nm thick films show Schottky emission current and the thicker films show a mixed characteristics and bulk and interface limited currents although the mechanism is not clearly understood at this moment.     

Pt/TiN electrodes for stacked memory with polysilicon plug utilizing PZT films

Abstract

The mechanism of TiN barrier metal oxidation of Pt/TiN electrodes are investigated for planarized stacked memory utilizing lead zirconate titanate (PZT). Thinner (<100 nm) and highly oriented platinum films are required in gigabit scale ferroelectric nonvolatile memories whose capacitor size is comparable to PZT grain size. Oxygen diffusivity to oxidize TiN is found to depend on the Pt film thickness. In cross-sectional TEM images of PZT/Pt/TiN/Si, titanium oxide is observed beneath the Pt grain boundary. The oxygen is diffused through the Pt grain boundary under heat treatment in an oxygen atmosphere for crystallization of PZT films, and oxidizes the underlying TiN barrier metal.     

Ferroelectric properties of (Bi3.15 Nd 0.85 )Ti 3 O 12 with decreasing film thickness

Film texture and ferroelectric behaviors of (Bi_3.15Nd_0.85)Ti₃O₁₂ (BNdT) of layered-perovskite structure deposited on Pt/TiO₂/Si substrate are dependent on the film thickness. When the film thickness is reduced from ∼240 to ∼120 nm, BNdT grains evolve from a rod-like morphology to a spherical morphology, accompanied by a decrease in average grain size. At the same time, P-E hysteresis transforms from a square-shaped hysteresis loop (2Pr ∼24.1 μC/cm² at 240 nm) to a relative slimmer hysteresis loop (with a lower 2Pr = 19.8 μC/cm² at 120 nm). The nonvolatile polarization (Δ P) shows a maximum at the film thickness of 160 nm, where Δ P was measured to be 14.7 μC/cm² and 6.8 μC/cm² at 5 V and 3 V, respectively. A small amount of excess bismuth in the film thickness of 130 nm, introduced by co-sputtering, can lead to a much enhanced remanent polarization (2Pr of 21.3 μC/cm² at 5 V and 15.2 μC/cm²at 3 V), which is promising for low voltage FRAM applications.     

Integration of H2 barriers for ferroelectric memories based on SrBi2Ta2O9 (SBT)

Abstract

In this study, integration of an hydrogen barrier into a FeRAM process flow is investigated. It is reported in the literature that ferroelectric properties can be maintained after hydrogen annealing by using IrO_x as a top electrode [16][17][18]. Advantage of materials like IrO_x is less catalytic activity compared to Pt. However, we found that IrO_x is not a promising candidate for top electrode barrier. (Pt)/IrO_x/SBT/Pt capacitors are prone to shorting or exhibit high leakage. IrO_x films are very easily reduced by reducing ambient which will result in peeling off. Also, IrO_x films tend to oxidize Ti or TiN layers immediately. Therefore, other barrier materials or layer sequences like Ir/IrO_x have to be considered.

For protection of the entire capacitor an Encapsulation Barrier Layer (EBL) is required. In this study, LPCVD SiN is used. LPCVD SiN is a standard material in CMOS technology. Production tools are available and it is well known as hydrogen barrier. By modifying the deposition process and using a novel process sequence, no visual damage of the capacitors after SiN-deposition and FGA is seen. Also, no degradation of electrical properties after capacitor formation as well as after SiN-deposition and FGA is observed. However, after metal 1 and metal 2 processing, 2P_r values at 1.8V are reduced from 12μC/cm²to 2μC/cm². Polarization at 5.0V is not affected.     

Sputtered ferroelectric thin films for dynamic random access memory applications

Abstract

A low thermal budget (with 550°C annealing) process with Ti-compensation for sputtered ferroelectric PZT thin films has been developed. PZT films with a composition near the morphotrophic phase boundary (Zr/Ti = 53/47) annealed at 550°C for 1 hr in a N₂ ambient exhibits high charge storage density and low leakage current density, which are the important requirements of dielectric materials for ULSI DRAM cells. It was also found that Ti compensated films show good fatigue endurance in comparison with non-Ti compensated films.