激光等离子体诱导靶上电势信号的振荡特性

纳秒脉冲激光烧蚀金属元靶产生等离子体,由于极少量速度较快的电子逃逸造成了等离子体区域出现微量剩余正电荷,并在周围空间激发电场.通过在靶上偏置负高压(0～1 000 V)研究了金属靶由于受等离子体作用而出现的电势变化.实验发现:靶上电势信号整体呈单峰分布,并在早期阶段(＜700 ns)出现强烈振荡现象,振荡频率(约40 MHz)不随靶偏置电压与激光能量发生变化.并首次对该振荡信号的产生机制进行了分析,认为靶上电势振荡是靶材偏置负压与等离子体中的净余电荷相互作用的结果.     

基于二维PIC-DSMC的微间隙气体放电等离子体演化过程研究

准确的理解微间隙气体放电中非平衡等离子随时间的演化过程对于设计气体开关、微电子及其它等离子体器件有着非常大的帮助。通过二维PIC-DSMC耦合算法模拟了一个大气压氮气环境下微间隙平板电极发生气体放电时电子及离子的运动演化过程,得到了气体放电过程中平板电极间电子和离子数密度分布随时间变化的趋势,讨论了阳极附近电子云的形成与演变、阴极附近存在的鞘层以及电子和离子的速度及温度分布,最后将模拟计算得到的击穿电压与帕邢曲线及相关实验结果进行了对比,为相关等离子体器件的进一步发展提供了理论基础。     

射频等离子体中的维持机理

本文涉及到在平行板射频等离子体中,气体大于10bar情况下的维持机理。为了考查研究,选择了两个特殊的频率—380kHz和1 3MHz。描述了包括电极电位和等离子体电位随时间变化的等离子体特性。靠近电极表面存在离子鞘层,这个鞘层中的电压降高到足以使电子获得能量产生电离。本文认为由于电极表面的离子轰击而产生的二次电子发射是主要的维持机理。利用产生率等于电荷流量加上复合率的关系,阐述了一个简单的模型。这就预示着外加电压与电流之间的一种线性关系。这种线性关系在低频情况下得到了实验证实。改变电极材料和改变电极间距都得到了与模型相一致的结果。然后介绍了一种在13MHz频率下测量离子电流的新方法。对于实际测到的低密度,要解释其结果,就需要一个附加维持机理,它来源于等离子体的本底产生。     

铜靶上激光等离子体诱发电势信号的实验研究

纳秒脉冲激光等离子体在周围空间激发电场,以金属靶作为探针即可测定靶上感应电随时间的变化,提出了"元靶探针"探测等离子体电学信号的测试方法.测试数据表明,在无偏置电压条件下,靶电势曲线呈双峰结构,电势峰值随激光能量单调增大;在外加负高压偏置条件下,靶感应电势曲线整体上(约ms)呈单峰结构,电势峰值随偏置电压增大而增大并出现饱和趋势,同时在信号的初期阶段(约700 ns)出现高频振荡现象,振荡频率不随激光能量及置电压发生变化.     

用于离子激光器的容性耦合射频放电理论研究

为了对高电流下的容性耦合射频(CCRF)放电有清晰的了解,我们建立了CCRF放电的自洽模型,研究了CCRF放电的放电特性和从低电流向高电流模式的转变规律.利用两电子组模型,结合流体模型自洽地研究了射频放电中放电参量与射频电压之间的变化关系.研究表明,在不考虑电极的γ过程时,射频放电的参量基本上随射频电压线性变化,没有出现转变迹像,而当考虑电极的γ过程后,射频放电明显出现两个不同的运行区域,对应于射频放电的低电流α区和高电流γ区.当射频放电出现转变后,传导电流密度和等离子体密度大幅度升高,鞘层电场增强,鞘层宽度明显减小,等离子体电场也减小.在γ放电下,快电子的电离速率分布主要在放电中心区且比较均匀,说明快电子在电极鞘层间形成了振荡,因此放电类似于空心阴极放电.(PC11)     

4H-SiC p-i-n紫外光电探测器的电容-电压特性研究

分析并比较了4H-SiC p-i-n紫外光电探测器的电容-电压（C-V）特性随温度和偏置电压的变化情况,观测到4H-SiC p-i-n结构中的深能级缺陷。结果表明：由于近零偏压时探测器i型层已处于耗尽状态,其高频（1 MHz）C-V特性几乎不随反向偏压变化,随着温度升高,被热离化的自由载流子数量增多导致高频结电容随之增大;探测器的低频（100 kHz）结电容比高频结电容具有更强的电压和温度依赖性,原因在于被深能级缺陷俘获的载流子随反向偏压增大或随温度升高而被离化,从而对结电容产生影响。     

空间等离子体鞘层的时域特性研究

空间等离子体环境,是计算机及各类电子设备所面临的新型恶劣环境。通过将设备表面简化为平面,给出了一维粒子层模型。根据静电场理论给出了描述鞘层电位的Poisson方程、等离子体理论和Boltzmann方程,给出了粒子数密度守恒方程。通过牛顿运动定律建立了等离子体的动量方程。基于Poisson方程、粒子数密度守恒方程和等离子体动量方程建立了等离子体鞘层动力学模型。该模型可以给出航天器表面附近等离子体鞘层形成过程的时域特性,如电荷通量、充电电位随时间的变化规律,为电子设备抗空间等离子体防护技术的研究提供理论基础。     

激光诱导击穿空气等离子体参数的光谱分析法

空气等离子体的电子温度和密度对激光诱导空气击穿等离子体产生闪光过程的研究有着重要的意义,本文将纳秒Nd∶YAG脉冲激光(1064 nm)聚焦于大气中,诱导其产生等离子体闪光,并通过Avantes-ULS3648型9通道的光谱仪采集闪光光谱,通过光谱分析,研究了不同延迟时间下激光诱导击穿空气等离子体产生过程中的等离子体电子温度和电子密度的变化情况。根据同一元素不同峰值位发出的光谱,由相对强度比较法可以得出等离子体电子温度,由斯塔克展宽法可得到等离子体电子密度的变化,通过分析发现,等离子体电子温度和密度均随延迟时间的增大而下降。这些结果对研究强激光作用下空气击穿的气体动力理论机制有一定的科学意义。     

He-Ne管正柱区鞘层及电子温度的计算

本文计算小孔径He-Ne管等离子体鞘层及电子温度,并对其电势及厚度的公式进行了讨论;计算的正柱区伏-安特性与实验符合.     

感应耦合等离子体刻蚀机二维放电模拟

为研究感应耦合等离子体(ICP)刻蚀机腔室与线圈结构以及工艺参数对等离子体分布均匀性的影响,基于商业软件CFD-ACE 中等离子体与电磁场等模块建立了ICP刻蚀机二维放电模型.仿真研究了典型工艺条件(1.33Pa,200W,200sccm)下氩等离子体电子温度与电子数密度的空间分布,对比了不同气压与功率条件下等离子体参数在硅片表面的一维分布.结果表明,电子数密度随气压与功率的增加而升高;电子温度随气压的增加而降低,随功率增加在较小范围内先降低再升高.通过分析屏蔽板对等离子体参数的影响,发现其有助于提高等离子体密度.进而发现屏蔽板的孔隙率越大,电子温度越高,电子数密度则越低.     

Far infrared emission from hot electrons in Si-Inversion layers

We observed narrow-band voltage tunable far infrared emission from hot electrons in n-channel Si-Inversion layers due to radiative transitions between electric subbands. The radiation was generated by heating up the electron distribution in the inversion layer by applying a pulsed electric field E along the channel. From the E dependence of the subband emission together with the temperature and E dependence of the Shubnikov de Haas oscillations we obtained a measure of the hot electron temperature T_e up to 40 V/cm. (T_e?T_L) shows an E² dependence at small E (up to 3 V/cm) and approaches a linear dependence at large E.     

Extremely Low Operating Voltage Green Phosphorescent Organic Light‐Emitting Devices

Organic light‐emitting devices (OLEDs) are expected to be adopted as the next generation of general lighting because they are more efficient than fluorescent tubes and are mercury‐free. The theoretical limit of operating voltage is generally believed to be equal to the energy gap, which corresponds to the energy difference between the highest occupied molecular orbital (HOMO) and the lowest unoccupied molecular orbital (LUMO) for the emitter molecule divided by the electron charge (e). Here, green OLEDs operating below a theoretical limit of the energy gap (E_g) voltage with high external quantum efficiency over 20% are demonstrated using fac‐tris(2‐phenylpyridine)iridium(III) with a peak emission wavelength of 523 nm, which is equivalent to a photon energy of 2.38 eV. An optimized OLED operates clearly below the theoretical limit of the E_g voltage at 2.38 V showing 100 cd m^?2 at 2.25 V and 5000 cd m^?2 at 2.95 V without any light outcoupling enhancement techniques.     

A novel analytical model of the vertical breakdown voltage on impurity concentration in top silicon layer for SOI high voltage devices

A novel analytical model of the vertical breakdown voltage (V_{B , V} ) on impurity concentration (N_d ) in top silicon layer for silicon on insulator high voltage devices is first presented in this article. Based on an effective ionisation rate considering the multiplication of threshold energy ε_T in the electron, a new formula of silicon critical electric field E_{S , C} on N_d is derived by solving a 2D Poisson equation, which increases with the increase in N_d especially at higher impurity concentration, and reaches up to 68.8?V/µm with N_d  = 1 × 10¹⁷?cm^?3 and 157.2?V/µm with N_d  = 1 × 10¹⁸?cm^?3 from the conventional about 30?V/µm, respectively. A new physical concept of critical energy ε_B is introduced to explain the mechanism of variable high E_{S , C} with heavy impurity concentration. From the E_{S , C} , the expression of V_{B , V} is obtained, which is improved with the increasing N_d due to the enhanced E_{S , C}. V_{B , V} with a dielectric buried layer thickness (t_I ) of 2?µm increases from 428?V of 1 × 10¹⁷?cm^?3 to 951?V of 1 × 10¹⁸?cm^?3. The dependence of N_d and top silicon layer thickness (t_S ) for an optimised device is discussed. 2D simulations and some experimental results are in good agreement with the analytical results.     

A 0.5 V bulk-input OTA with improved common-mode feedback for low-frequency filtering applications

This paper presents the design of a two-stage pseudo-differential operational transconductance amplifier (OTA) and its application in low-frequency continuous time filters. The OTA was designed in a 0.18 μm, 0.45 V V _T CMOS process. An improved bulk-mode common-mode feedback (CMFB) circuit has been designed which does not load the OTA compared to prior art. A self cascode load structure and partial positive feedback provide higher gain. The bulk terminals of all transistors have been biased to lower their threshold voltages (V_T) and maximize signal swing. The OTA operates at a supply voltage of 0.5 V and consumes only 28 μW of power. Rail-to-rail input is made possible by using the transistor’s bulk terminal as the input. For a load of 20 pF the OTA has a measured DC gain of 63 dB and a gain-bandwidth product of 570 kHz. To demonstrate the use of the OTA in practical circuits, three active RC filters were designed: a 10 kHz Butterworth filter, a 10 kHz Bessel filter, and a 2.5 kHz Tschebycheff filter.     

Positive Column Plasma in a Neon Discharge at Medium Pressures†

The present paper concentrates on the experimental investigation of the behaviour of steady-state plasma columns in a neon discharge for a pressure range of 2-32 mm Hg. The electron temperature T _e, the electron concentration across the centre-line tube n _o, the electron radial distribution n(r), the axial electric field E and the ionic current density at the discharge tube walls are determined. The experimental results are compared to the theoretical data obtained in the model proposed by Kagan and Ljagushchenko (1964 a, b). For our experimental conditions a good agreement is obtained between theory and experiment.     

Effect of stress voltages on voltage acceleration and lifetime projections for ultra-thin gate oxides

This paper investigates the effect of NFET (N+ poly gate, N+ diffusion of FET) stress voltage conditions, for ultra-thin gate oxides, on the voltage acceleration, and lifetime projections to use conditions. This work employs the model relating the critical defect density (N^BD) to the charge-to-breakdown and the defect generation probability (P_g). The models for N^BD and P_g were adjusted for effects at voltages between 2 V and 3 V, and oxide thickness less than 2.7 nm. For N^BD, a model is proposed that is supported by published data and provides a gradual transition to a plateau for oxide thickness less than 2.7 nm. For P_g, a stronger dependency of Log(P_g) in the range of 2–3 V is employed to give a better fit to published data. This adjusted P_g is also used below 2 V to show trend of projection. In the direct tunneling range below 3 V, there is an increase of the voltage acceleration factor (AF) with decreasing voltage. Also, below 3 V, AF shows a decrease as the oxide thickness is reduced from 2.0 nm to 1.2 nm, and this trend becomes stronger as the gate voltage is reduced. Above a gate stress voltage of 3 V, in the range of 3–4 V, AF is almost constant, and there is a slight decrease of AF with decreasing oxide thickness in the range of 2.0–1.2 nm. A voltage power-law fit for the range above 3 V shows a decreasing power index with decreasing oxide thickness.     

Fabrication of blocked impurity-band structures on gallium-doped silicon by plasma hydrogenation

The electrical characteristics of blocked impurity-band structures (BIB-structures) based on gallium-doped silicon (N _Ga≈5×10¹⁷ cm⁻³) are investigated. The blocking layers were formed by passivation of the gallium impurity by means of treatments in an rf-discharge hydrogen plasma at substrate temperatures T=20–220 °C. It is found that the activation energy E _a of the hopping conductivity with hopping between nearest gallium neighbors decreases from 8.7 meV (before hydrogenation) to 1.3 meV (after hydrogenation at T=220 °C). The current-voltage characteristics and temperature dependence of the dark current of the structures and their change after isochronal (t=20 min) annealing at temperatures T=220–400 °C are determined. The current-voltage characteristics of the structures at low temperatures are calculated. The results of calculations are found to agree with experimental data. Fiz. Tekh. Poluprovodn. 31, 311–317 (March 1997)     

Effects of quantization on random telegraph signals observed in deep-submicron MOSFETs

Random telegraph signals (RTS) have been investigated in the drain to source voltage of W_eff×L_eff=1.37×0.17 μm² medium-doped drain (MDD) n-type MOSFETs. The emission (τ_e) and capture (τ_c) times of the probed trap were studied as a function of gate voltage as well as substrate voltage. The small size and high doping density of the n-MOSFETs studied create a strong electric field in the MOSFET inversion layer, which makes the surface conduction band split into discrete energy levels. Therefore, modified expressions of τ_e and τ_c including the influence of bulk bias (V_SB), which changes the degree of quantization, are presented. The trap position in the oxide with respect to the Si–SiO₂ interface, and the trap energy, were calculated from the gate voltage dependence of the emission and capture times under different bulk bias conditions. The behavior of the emission and capture times predicted by the two-dimensional (2D) surface quantization effects is in qualitative agreement with the experimental results. The RTS amplitude (ΔV_DS/V_DS) shows a positive dependence on V_SB. The coefficient α for screened oxide charge scattering was calculated at different gate voltages and bulk bias from the RTS amplitude. In addition, the theoretical calculation of the scattering coefficient α, using a 2D surface mobility fluctuation model, was presented, which shows a good agreement with the experimental data.     

Nitridation of silicon in a multiwafer plasma system

Silicon wafers were nitrided in a multiwafer plasma system at low temperatures (< 850°C). An argon plasma (400 kHz rf plasma) was used to which small quantities (approximately 2–8 %) of NH3, N₂ or mixtures of N₂ and H₂ were added. As the rf power was increased, the film thickness as well as the etch rate (in buffered HF) increased. The rate of film growth was found to be slower than that for oxidation in a similar type of plasma system. The effects of variation of power and gas composition on film composition and etch rate are discussed.     

Hole injection enhanced hot-carrier degradation in PMOSFETs used for systems on chip applications with 6.5–2 nm thick gate-oxides

Hot-carrier reliability is studied in core logic PMOSFETs with a thin gate-oxide (T_ox=2 nm) and in Input/Output PMOSFETs with a thick gate-oxide (6.5 nm) used for systems on chip applications. Hot-hole (HH) injections are found to play a more important role in the injection mechanisms and in the degradation efficiency. This depends on the technology node for stressing voltage conditions corresponding to channel hot-hole injections, i.e. closer to the supply voltage than the other voltage condition. Distinct mechanisms of carrier injections and hot-carrier degradation are found in core devices used for high speed (HS) and low leakage (LL) applications where the hole tunneling current dominates at low voltages while the electron valence band tunneling from the gate occurs at gate-voltages above −1.8 V. Devices with T_ox=6.5 nm have shown the existence of a thermionic hot-hole gate-current which is directly measured at larger voltages. This is related to the increase in the surface doping, the thinning of the drain junction depth and the location of the hot-carrier generation rate which is closer to the interface. Results show that hole injections worsen the hot-carrier damage in thin and thick gate-oxides which are both distinguished by the effects of the interface trap generation, the permanent hole trapping and the hole charging–discharging from slow traps using alternated stressing in thin gate-oxides. This consequently leads to a significant lifetime increase in 2 nm HS, LL devices with respect to 6.5 nm Input/Output devices explained by the dominant effect of the fast interface trap generation due to the hole discharge from slow traps and bulk oxide traps in 2 nm devices at the tunneling distance of the interface.