0.18μm自偏置锁相环抗单粒子辐射加固技术研究

设计了一款抗辐射自偏置锁相环(PLL),对PLL电路中关键逻辑进行单粒子效应分析,找出敏感节点,再对这些节点进行加固设计。该PLL电路用SMIC 0.18μm 1P4MCMOS工艺实现了设计。加固后的电路在中国原子能科学研究院核物理研究所,选择入射能量为206MeV、LET为37MeV·cm2/mg的72 Ge离子进行了单粒子辐射试验。PLL未发生失锁现象,能够满足航天应用的需求。     

一种抗单粒子瞬态扰动触发器加固结构

提出了一种新型的电阻-电容抗辐射触发器加固结构(RC-DICE),并与DICE结构加固触发器、RDFDICE结构加固触发器进行了比较。测试电路利用0.18μm体硅CMOS工艺进行流片,单粒子验证试验在中国原子能科学研究院抗辐射应用技术创新中心进行。结果证明:新型抗辐射加固触发器在50 MHz工作频率下,单粒子翻转线性能量转移阈值≥37 MeV·cm~2/mg,能够满足航天应用的需求。     

辐照加固的500MHz锁相环设计

设计了一款与CSMC 0.5μm CMOS工艺兼容的频率为500 MHz的辐照加固整数型锁相环电路,研究了总剂量辐照以及单粒子事件对锁相环电路主要模块及整个系统性能的影响。此外,通过修正BSIM3V3模型的参数以及施加脉冲电流源来模拟总剂量辐照效应和单粒子事件,对锁相环整体电路进行了电路模拟仿真以及版图寄生参数提取后仿真。模拟结果表明,辐照总剂量为1Mrad(Si)时锁相环电路仍能正常工作,产生270.58~451.64 MHz的时钟输出,峰峰值抖动小于100 ps,锁定时间小于4μs;同时在对单粒子事件敏感的数字电路的主要节点处施加脉冲电流源后,锁相环电路均能在短时间内产生稳定的输出。     

一种提高锁相环中电荷泵SET抵抗能力的辐射加固设计技术

A radiation-hardened-by-design （RHBD） technique for phase-locked loops （PLLs） has been developed for single-event transient （SET） mitigation. By presenting a novel SET-resistant complementary current limiter （CCL） and implementing it between the charge pump （CP） and the loop filter （LPF）, the PLL＇s single-event susceptibility is significantly decreased in the presence of SETs in CPs, whereas it has little impact on the loop parameters in the absence of SETs in CPs. Transistor-level simulation results show that the CCL circuit can significantly reduce the voltage perturbation on the input of the voltage-controlled oscillator （VCO） by up to 93.1% and reduce the recovery time of the PLL by up to 79.0%. Moreover, the CCL circuit can also accelerate the PLL recovery procedure from loss of lock due to phase or frequency shift, as well as a single-event strike.     

宇航VDMOS器件单粒子辐射加固技术综述

宇航用功率VDMOS器件是航天器电源系统中实现功率转换的核心元器件之一。针对航天器对宇航用功率VDMOS器件的发展需求,在总结国内外宇航用功率VDMOS器件产品及技术发展现状的基础上,对比分析了宇航用功率VDMOS器件在技术水平、系列化程度、长期可靠性和系统应用等方面存在的主要差距。对我国宇航用功率VDMOS器件的主要任务进行了展望。     

一种基于SOI的抗单粒子效应锁相环设计

基于0.5μm SOI工艺,设计了一种具有抗单粒子效应的锁相环。重点对压控振荡器进行抗辐照加固,采用电流源放大器实现。与普通结构相比,提高了锁相环在辐照环境下的稳定性。该锁相环最高输出频率达到80MHz,动态电流为12.23mA,抗单粒子效应能力大于37 MeV·cm2/mg。     

一种基于SOI的抗单粒子效应锁相环设计

基于0.5 μm SOI工艺,设计了一种具有抗单粒子效应的锁相环。重点对压控振荡器进行抗辐照加固,采用电流源放大器实现。与普通结构相比,提高了锁相环在辐照环境下的稳定性。该锁相环最高输出频率达到80 MHz,动态电流为12.23 mA,抗单粒子效应能力大于37 MeV·cm²/mg。     

一款深亚微米抗辐照芯片的设计与实现

设计了一款适用于航空航天领域的深亚微米抗辐照四路串口收发电路,重点介绍了逻辑设计、后端设计和抗辐照加固设计。电路采用0.18μm CMOS工艺加工,使用工艺加固、单元加固及电路设计加固等多层次加固技术,有效地提高了电路的抗辐照能力。     

一种抗单粒子效应的加固技术研究

针对数字波控电路在星载控制电路应用中存在的单粒子翻转效应问题,提出了一种基于DICE单元的双稳态D触发器设计改进,设计了一种能够抵御众多类型单粒子翻转效应的D触发器,并基于该D触发器,结合电路级单粒子加固技术设计了一款串并转换芯片。测试表明,采用改进D触发器结构的波控芯片能够抵御至少80 MeV的单粒子效应事件。芯片峰值功耗不大于10 mA,写入速率不低于10 MHz,功耗为1 mW/MHz。     

ASIC电路中时钟驱动的抗单粒子加固

CMOS工艺制成的ASIC电路在太空中应用时,在辐射效应的影响下可能导致数据出错,影响整个系统的可靠性.在ASIC电路的抗辐射设计时,最关注的是时钟(CLK)驱动电路受辐射效应的影响.为此,文章分析了深亚微米工艺条件下CLK电路受到单粒子瞬态扰动效应(SET)的影响,为消除SET效应对CLK电路的扰动提出了四种加固方案...     

A novel radiation hardened by design latch

Due to aggressive technology scaling, radiation-induced soft errors have become a serious reliability concern in VLSI chip design. This paper presents a novel radiation hardened by design latch with high single-event-upset (SEU) immunity. The proposed latch can effectively mitigate SEU by internal dual interlocked scheme. The propagation delay, power dissipation and power delay product of the presented latch are evaluated by detailed SPICE simulations. Compared with previous SEU-hardening solutions such as TMR-Latch, the presented latch is more area efficient, delay and power efficient. Fault injection simulations also demonstrate the robustness of the presented latch even under high energy particle strikes.     

一种新型的抗辐射加固锁存器

Due to aggressive technology scaling, radiation-induced soft errors have become a serious reliability concern in VLSI chip design. This paper presents a novel radiation hardened by design latch with high single-eventupset （SEU） immunity. The proposed latch can effectively mitigate SEU by internal dual interlocked scheme. The propagation delay, power dissipation and power delay product of the presented latch are evaluated by detailed SPICE simulations. Compared with previous SEU-hardening solutions such as TMR-Latch, the presented latch is more area efficient, delay and power efficient. Fault injection simulations also demonstrate the robustness of the presented latch even under high energy particle strikes.     

一种抗单粒子全加固D触发器的设计

采用当前成熟的两种抗单粒子翻转锁存器构成了主从D触发器,在D触发器加固设计中引入了时钟加固技术,对输出也采用了加固设计。仿真对比显示本设计的加固效果优于国内同类设计。     

基于三模冗余结构的自刷新寄存器设计

设计了一种带自刷新功能的寄存器,该寄存器采用两级数据锁存结构,在第二级锁存结构中设计了一个选择电路。该选择电路采用三选二机制,用于三模冗余结构中取代常用寄存器,选择数据来自三模冗余结构的三路输出。有两路值相同,输出结果为该值,用于修正寄存器的输出值。在0.13μm工艺条件下用此结构设计的寄存器,面积为32.4μm×8.4μm,动态功耗0.072μW·MHz-1,建立时间0.1 ns,保持时间0.08 ns。该结构用于三模冗余结构中,可有效防止单粒子翻转效应(Single Event Upset,SEU)的发生。测试结果表明采用该结构的寄存器组成的存储单元三模冗余加固结构,在时钟频率1 GHz时,单粒子翻转错误率小于10-5。     

用于超宽带系统的低参考杂散正交锁相环

本文介绍了一个用于中国超宽带标准频率综合器中的低相位噪声、低参考杂散的正交锁相环。通过使用具有毛刺抑制作用的电荷泵,锁相环的参考杂散被有效地抑制。通过使鉴频鉴相器和电荷泵工作在传输特性曲线的线性区,锁相环的线性度得以提高。为了保证正交锁相环输出信号的正交性,提出了一种串联正交压控振荡器。锁相环采用TSMC 0.13 μm CMOS工艺制造,电源电压1.2 V。正交锁相环在1 MHz频偏处的相位噪声为-105 dBc/Hz,参考杂散为-71 dBc。整个锁相消耗了13 mA的电流。     

A low reference spur quadrature phase-locked loop for UWB systems

This paper presents a low phase noise and low reference spur quadrature phase-locked loop(QPLL) circuit that is implemented as a part of a frequency synthesizer for China UWB standard systems.A glitch-suppressed charge pump(CP) is employed for reference spur reduction.By forcing the phase frequency detector and CP to operate in a linear region of its transfer function,the linearity of the QPLL is further improved.With the proposed series-quadrature voltage-controlled oscillator,the phase accuracy of the QPLL is guaranteed.The circuit is fabricated in the TSMC 0.13μm CMOS process and operated at 1.2-V supply voltage.The QPLL measures a phase noise of -95 dBc/Hz at 100-kHz offset and a reference spur of -71 dBc.The fully-integrated QPLL dissipates a current of 13 mA.     

基于保护门的纳米CMOS电路抗单粒子瞬态加固技术研究

随着器件特征尺寸的缩减,单粒子瞬态效应(SET)成为空间辐射环境中先进集成电路可靠性的主要威胁之一。基于保护门,提出了一种抗SET的加固单元。该加固单元不仅可以过滤组合逻辑电路传播的SET脉冲,而且因逻辑门的电气遮掩效应和电气隔离,可对SET脉冲产生衰减作用,进而减弱到达时序电路的SET脉冲。在45 nm工艺节点下,开展了电路的随机SET故障注入仿真分析。结果表明,与其他加固单元相比,所提出的加固单元的功耗时延积(PDP)尽管平均增加了17.42%,但容忍SET的最大脉冲宽度平均提高了113.65%,且时延平均降低了38.24%。     

A radiation-hardened-by-design technique for improving single-event transient tolerance of charge pumps in PLLs

A radiation-hardened-by-design (RHBD) technique for phase-locked loops (PLLs) has been developed for single-event transient (SET) mitigation. By presenting a novel SET-resistant complementary current limiter (CCL) and implementing it between the charge pump (CP) and the loop filter (LPF), the PLL's single-event suscepti-bility is significantly decreased in the presence of SETs in CPs, whereas it has little impact on the loop parameters in the absence of SETs in CPs. Transistor-level simulation results show that the CCL circuit can significantly reduce the voltage perturbation on the input of the voltage-controlled oscillator (VCO) by up to 93.1% and reduce the recovery time of the PLL by up to 79.0%. Moreover, the CCL circuit can also accelerate the PLL recovery procedure from loss of lock due to phase or frequency shift, as well as a single-event strike.     

一种65 nm CMOS低功耗加固SRAM单元

提出了12管低功耗SRAM加固单元。基于堆叠结构,大幅度降低电路的泄漏电流,有效降低了电路功耗。基于两个稳定结构,可以有效容忍单粒子翻转引起的软错误。Hspice仿真结果表明,与相关加固结构相比,该结构的功耗平均下降31.09%,HSNM平均上升19.91%,RSNM平均上升97.34%,WSNM平均上升15.37%,全工作状态下均具有较高的静态噪声容限,表现出优秀的稳定性能。虽然面积开销平均增加了9.56%,但是,读时间平均下降14.27%,写时间平均下降18.40%,能够满足高速电子设备的需求。