量子元胞自动机干支型交叉线及应用

量子元胞自动机(QCA)耦合功能阵列是一种二维的纳米尺度计算范式,可靠性较低的共面交叉线结构是QCA电路交叉互连时的薄弱环节。信号分布网络是实现交叉线功能的一种新方法,但面临元胞随机翻转干扰问题。为解决该问题,首先分析了QCA基本器件逻辑功能实现机理,并提出了一种干支型交叉线。该器件可以在两路信号相遇时选通干路信号屏蔽支路信号,从而达到抑制干扰信号的目的。通过仿真实验得出了其鲁棒功能结构和时钟分配原则。然后利用干支型交叉线改进了异或门设计,仿真结果进一步验证了其逻辑功能。     

量子元胞自动机共面五输入择多门结构的分析与设计

量子元胞自动机（Quantum-dot Cellular Automata,QCA）是一种具有新型计算范式的纳米器件,它是未来有望替代传统CMOS器件的有力竞争者之一.本文首先从QCA器件的功耗角度出发,对影响半径为41nm的QCA共面系统中元胞的耦合度进行建模,根据元胞之间的位置关系构造QCA门结构模型,据此对现有的共面五输入择多门进行分类,通过性能分析总结其结构特点,以此设计出一个新的低功耗五输入择多门,测试结果表明该结构功耗最低且其他性能也相对较优.另外,为验证所提出五输入择多门在电路中的性能,本文选择MR Azghadi全加器设计了一款共面QCA全加器,与同类加法器相比性能也最优.     

基于量子元胞自动机容错全加器的设计

为提高新一代纳米器件量子元胞自动机(QCA)电路的稳定性及可靠性,提出了一种容错1位全加器,然后通过QCADesigner软件来仿真分析1位容错全加器,验证了该设计的可行性及它具有较好的容错性,该设计对复杂QCA电路的容错性的研究起到借鉴作用.     

基于贝叶斯模型的QCA扇出结构转换特性

基于半径为2的贝叶斯模型,量化分析了量子元胞自动机(QCA)扇出结构的转换特性。分析表明,采用半径为1的贝叶斯模型进行QCA转换特性分析将导致传输线正确概率的误差增大到40%,而半径为2的贝叶斯模型平衡了运算量和计算精度,适用于QCA的可靠性分析。仿真表明,扇出结构的正确概率随元胞尺寸和元胞间距的增大而逐渐降低,也随着输入条件和输出端的不同而改变,输入为‘1’时,扇出的拐角输出端的正确概率高于85%,而输入为‘0’时,拐角输出端的正确概率低于20%。这是由于QCA是一种基于量子机理进行工作的器件,不同的输入或不同的元胞尺寸和元胞间距都将造成元胞扭结能的改变,进而影响元胞的翻转概率。研究所得结论可为今后QCA的电路实现与设计和可靠性分析提供参考。     

基于概率模型的QCA触发器可靠性研究

通过将时序逻辑电路中的反馈回路打开,在原有电路结构的基础上增加一路输入,采用概率转移矩阵方法建立了基于QCA的RS触发器、D触发器、JK触发器的可靠性模型,深入研究了各组成元件对其可靠性影响的差异,从而为其可靠性的提高提供了依据,这对于高缺陷率的QCA电路的可靠性设计具有重要的指导意义。     

基于量子元胞自动机的奇偶校验系统分块设计

量子元胞自动机(QCA)是一种纳米范围内不含晶体管的计算范例。基于QCA提出了QCA奇偶校验系统电路的分块设计方法。首先设计了异或门、奇偶判断单元,再运用分块设计思想构建了奇数产生电路和奇偶校验电路的结构,所设计的电路拥有尺寸极小和功耗极低等优点,QCADesigner软件仿真结果验证了设计的有效性。     

量子元胞自动机全加器的性能分析与设计

作为一种新型的纳米器件,量子元胞自动机（Quantum-dot cellular automata,QCA）有望取代传统CMOS器件.本文总结了目前已提出的三种全加器（Full Adder,FA）架构,通过概率转移矩阵（Probabilistic Transfer Matrix,PTM）分析找出其中最稳定的架构,进一步地,利用这三种全加器分别构建串行加法器,并从复杂度、不可逆功耗、成本等方面进行比较,结果发现性能最优的全加器架构为MR Azghadi FA.随后,选择该架构提出了一种针对全加器的新型逻辑门和共面QCA全加器电路,并应用此全加器设计了多位串行加法器,经对比分析表明,本文所提出的全加器电路在面积、元胞数和功耗等方面均有较大改进,且具有很好的扩展性.     

基于QCA的五输入Majority门设计及应用

Majority门作为多数逻辑电路的基本逻辑单元,其性能直接影响整体电路的质量.使用量子元胞自动机（QCA）设计Majority门具有结构简单的优点.本文提出了一种三层电路实现五输入Majority门的设计,并以此设计了全加器,进一步应用于多位加法器和乘法器中,与已发表的电路设计比较表明,其版图使用面积和元胞数有明显的减少,加法器元胞数和面积改进最高可达43%和87.2%,乘法器元胞数和面积改进最高可达48.2%和100%.     

一种针对QCA电路自动布局布线的混合策略研究

量子元胞自动机（Quantum Cellular Automata,QCA）电路的自动布局布线是在相关约束条件下自动放置电路单元、自动形成连线，实现门级或元胞级电路的设计过程，是QCA电路设计大型化、复杂化和系统化的必要工具.布局布线算法设计过程中最大的难题是如何解决“时钟同步”，随着二维时钟方案提出，该问题的解决方案变得更加策略化，但仍存在诸多缺陷，如成功率低，布局面积较大等.本文将二维时钟方案的布局布线问题抽象成组合优化模型，提出了一种基于遗传算法GA(Genetic Algorithm)和改进A*算法的混合策略.两种算法相互配合搭建可能的电路布局，并通过精心设计的适应度函数，搜索满足时钟同步的个体，最终实现从硬件电路到二维时钟方案上的门级布局.实验结果表明，本算法在目前被广泛应用的二维时钟方案USE(Universal,Scalable and Efficient)上的布局成功率接近100%.相较当前世界上最先进的两个QCA布局布线工具fiction和Ropper，本算法可适用电路规模更大（逻辑门数量大于10），在成功率和生成布局面积上都有大幅度的优化.     

多元线性回归分析在QCA数值比较器可靠性研究中的应用

基于概率转移矩阵方法建立了QCA数值比较器的可靠性模型,采用多元线性回归方法定量分析了QCA数值比较器中各组成元件对整体可靠性的不同影响,并比较了元件可靠性改善度对整体可靠性改善度的不同影响.结果表明,当传输线可靠性改善度为3.00％时,整体可靠性改善度为16.51％,远高于其它元件,从而为大规模QCA数值比较器电路的...     

An efficient design of CORDIC in Quantum-dot cellular automata technology

Power dissipation of future-integrated systems, consisting of a numberless of devices, is a challenge that cannot be easily solved by classical technologies. Quantum-dot Cellular Automata (QCA) is a Field-Coupled Nanotechnology (FCN) and a potential alternative to traditional CMOS technologies. It offers various features like extremely low-power dissipation, very high operating frequency and nanoscale feature size. This study presents a novel design of CORDIC circuit based on QCA technology. The proposed circuit is based on several proposed QCA sub-modules as adder and Flip-Flop. To design and verify the proposed architecture, QCADesigner tool is employed and power consumption is estimated using QCAPro software. The proposed QCA CORDIC achieves about 69% reduction in power and area compared to previous existing designs. The outcome of this work can open up a new window of opportunity for the design of the CORDIC module and can be used in low-power signal and image processing systems.     

一位QCA数值比较器的可靠性研究

针对量子元胞自动机电路中存在的元胞移位、元胞未对准、元胞遗漏、元胞旋转等固有缺陷,采用概率转移矩阵方法建立了一位QCA数值比较器的可靠性模型,并对其可靠性进行了深入分析。对于不同的输入,分别比较了各组成元件在同样的故障概率水平下对整体可靠性(正确输出的概率)的不同影响。仿真结果表明,在所有的输入情况下传输线始终是影响其可靠性的主要因素,从而确定了传输线在该数值比较器中的重要性,进而为大规模QCA数值比较器的设计以及可靠性的提高提供了依据。     

Single-bit digital comparator circuit design using quantum-dot cellular automata nanotechnology

The large amount of secondary effects in complementary metal–oxide–semiconductor technology limits its application in the ultra-nanoscale region. Circuit designers explore a new technology for the ultra-nanoscale region, which is the quantum-dot cellular automata (QCA). Low-energy dissipation, high speed, and area efficiency are the key features of the QCA technology. This research proposes a novel, low-complexity, QCA-based one-bit digital comparator circuit for the ultra-nanoscale region. The performance of the proposed comparator circuit is presented in detail in this paper and compared with that of existing designs. The proposed QCA structure for the comparator circuit only consists of 19 QCA cells with two clock phases. QCA Designer-E and QCA Pro tools are applied to estimate the total energy dissipation. The proposed comparator saves 24.00% QCA cells, 25.00% cell area, 37.50% layout cost, and 78.11% energy dissipation compared with the best reported similar design.     

Efficient design of parity preserving logic in quantum-dot cellular automata targeting enhanced scalability in testing

Design of parity preserving logic based on emerging nanotechnology is very limited due to present technological limitation in tackling its high error rate. In this work, Quantum-dot cellular automata (QCA), a potential alternative to CMOS, is investigated for designing easily testable logic circuit. A novel self-testable logic structure referred to as the testable-QCA (t-QCA), using parity preserving logic, is proposed. Design flexibility of t-QCA then evaluated through synthesis of standard functions. The programmability feature of t-QCA is utilized to implement an ALU, realizing six important functions. Although the parity preservation property of t-QCA enables concurrent detection of permanent as well as the transient faults, an augmented test logic circuit (TC) using QCA primitives has been introduced to cover the cell defects in nanotechnology. Experimental results establish the efficiency of the proposed design that outperforms the existing technologies in terms of design cost and test overhead. The achievement of 100% stuck-at fault coverage and the 100% fault coverage for single missing/additional cell defects in QCA layout of the t-QCA gate, address the reliability issues of QCA nano-circuit design.     

基于改进DDS技术的FPGA数字调制器研究与实现

提出了一种基于改进直接数字频率合成(DDS) 技术的现场可编程门阵列(FPGA)数字调制器设计与实现方法.该方法首先对DDS技术进行改进,然后再利用这种改进的DDS技术在Matlab/ DSP Builder环境下建立现场可编程门阵列(FPGA)数字调制器的设计模型.通过对二元频移键控(BFSK) 的仿真实验表明,使用这种改进DDS技术的FPGA数字调制器实现方法建立的模型进行算法级和寄存器传输级(RTL)仿真,不仅能验证模型的正确性和有效性,且还简化系统的硬件电路,节省系统资源,提高系统的可靠性与灵活性,最终达到成本低,修改方便,快速产生多种模式数字调制信号的目的.     

A new quantum-dot cellular automata full-adder

A novel expandable five-input majority gate for quantum-dot cellular automata and a new full-adder cell are presented. Quantum-dot cellular automata (QCA) is an emerging technology and a possible alternative for semiconductor transistor based technologies. A novel QCA majority-logic gate is proposed. This component is suitable for designing QCA circuits. The gate is simple in structure and powerful in terms of implementing digital functions. By applying these kinds of gates, the hardware requirement for a QCA design can be reduced and circuits can be simpler in level, gate counts and clock phases. In order to verify the functionality of the proposed device, some physical proofs are provided. The proper functionality of the FA is checked by means of computer simulations using QCADesigner tool. Both simulation results and physical relations confirm our claims and its usefulness in designing every digital circuit.