Applications of single and dual gate GaAs MESFETs for Gbit/s optical data transfer systems

Intrinsic large signal rise and fall times of less than 30 ps without charge storage demonstrate the potential of single and dual gate GaAs MESFETs for Gbit/s optical communication systems. The applications as signal regenerator, bit synchronizer, laser modulator, multiplexer, and demultiplexer are shown. Using only one dual gate GaAs MESFET clock and pulse shape regeneration as well as 1 Gbit/s laser modulation is performed. Bit synchronization is demonstrated up to 4 Gbit/s. 1 to 2 Gbit/s and 2 to 4 Gbit/s multiplexing as well as 2 to 1 Gbit/s demultiplexing with additional clock and pulse shape regeneration is shown using dual gate FETs. 2 to 4 Gbit/s multiplexing without clock regeneration is also accomplished using single gate GaAs MESFETs.     

A high speed GaAs 8-bit multiplexer using capacitor-coupled logic

Capacitor-coupled logic has been used to design and fabricate a GaAs eight channel multiplexer IC for use at 1.2 Gbit/s, which is fully compatible with ECL, and which offers good stability and very high tolerances to device parameters and circuit voltages. A technique has been developed to enable initial charging of all the coupling capacitors, upon application of a simple pulse sequence to control lines. Preliminary results show correct operation of the multiplexer when operated on wafer probes up to 250 MHz, the present practical limit for such measurements. Higher frequency measurements will be carried out on packaged devices, but these results are not yet available. The divide-by-two elements in the multiplexer can be programmed to self oscillate at /SUP 1///SUB 4/ their maximum usable frequency, allowing simple testing of high frequency performance. A very good agreement between the measured maximum usable frequencies and those predicted from the oscillation frequencies has been achieved, with over 60 percent yield for dividers. On the basis of these preliminary results, indicating operation at speeds up to about 600 MHz, it is anticipated that future wafers with 1 /spl mu/m gate lengths will operate at 1.2 Gbits/s.     

Technology and Design Considerations for a Very-High-Speed Fiber-Optic Data Bus

The techology for very-high-speed fiber-optic data transmission is reviewed, and an assessment is made of the data rate limitations for a ring bus. Maximum data rates for single-channel transmission are estimated to he in the five-ten Gbit/s range, but bus capacity can be increased to 100 Gbits/s or higher with parallel interconnections or carrier-frequency multiplexing. A recirculating fiber loop is proposed as a buffer between the high data rate bus and terminals which operate at relatively low speeds. A bus terminal design based on this concept is suggested.     

Fully differential 8-to-1 current-mode multiplexer for 10 Gbit/s serial links in 0.18 /spl mu/m CMOS

A new fully differential CMOS current-mode multiplexer where a high multiplexing speed is achieved by performing multiplexing at low-impedance node, and inductive shunt peaking with active inductors is presented. The differential configuration of the multiplexer not only minimises the effect of common-mode disturbances, particularly those coupled from the power and ground rails, but more importantly, the flow of the out currents in the opposite directions minimises the effect of electro-magnetic interference from channels, making the multiplexer particularly attractive for high-speed data transmission over long interconnects and printed circuit board (PCB) traces. The proposed multiplexer also ensures that total current drawn from the supply voltage is constant, thereby minimising the amount of noise injected to the substrate. The multiplexer has been implemented in TSMC's 1.8 V 0.18 /spl mu/m CMOS technology and analysed using Spectre from Cadence Design Systems with BSIM3.3 v device models. Simulation results demonstrate that the multiplexer offers sufficiently large eye opening when multiplexing at 10 Gbit/s.     

Diode Circuits for Pulse Regeneration and Multiplexing at Ultrahigh Bit Rates

Clocked step-recovery diode (SRD) circuits are investigated for regenerating and multiplexing PCM-type signals in the range from 0.1 to a few gigabits per second. One regenerator type is particularly suited for operating with signals in the 1-V range, whereas a differential version employing a magic T was developed for handling signals of down to about 5 mV. By making use of line transformers as coupling networks, high-level versions have been cascaded. Experiments performed at 0.3 and 1 Gbit/s yielded voltage amplifications (peak amplitudes) of 2.5-5.5 for single stages, and insertion power gains of 7-11 dB for 2-3 stage cascades. Diode stages have also been used for multiplexing 4 and 2 individual bit streams to give a combined output signal at 1 and 2 Gbit/s, respectively. In a preliminary multiplexer experiment an output at 4.5 Gbit/s was obtained. Finally, possibilities are discussed for improving the performance of the regenerators/multiplexers and for their applications.     

Integrated bipolar master/slave D-flip-flop with multiplexing capability for Gbit/s operation

A versatile integrated bipolar circuit developed for a broadband communication system is described. It consists of a master/slave D-flip-flop with a 2:1 time-division multiplexer at the input and a powerful buffer stage at the output. Despite realisation in a relatively simple bipolar technology, bit rates up to 1.5 Gbit/s (NRZ) were measured.     

Optoelectronic time division multiplexing

The concept of using optoelectronic (photoconductive) switches as the sampling element in time division multiplexing is introduced in the context of VLSI off-chip data transmission. A 4:1 multiplexer was fabricated in Cr : GaAs, activated by a GaAs laser via optical fibre delay lines and operated at 2.5 Gbit/s.     

Silicon bipolar IC for PRBS testing generates adjustable bit ratesup to 25 Gbit/s

For the first time, a completely integrated pseudo-random pattern generator providing adjustable bit rates up to at least 25 Gbit/s without additional external multiplexing is presented. The sequence length is 2ⁿ-1. The application of the monolithic Si bipolar IC serves as a single chip measurement instrument for pseudo-random binary sequence (PRBS) generation required for the characterisation and development of high-speed components used in future optical fibre communication systems. Only three external microwave components are needed for operation: a clock generator, a power divider and a phase shifter. The chip is realised in an advanced implanted base silicon bipolar technology     

Characteristics of Gbit/s optical receiver sensitivity and long-span single-mode fiber transmission at 1.3 µm

Sensitivity of a 1.3 μm Ge APD receiver was measured at data rates ranging from 100 Mbits/s to 2 Gbits/s, using a high-speed GaAs FET RZ driver, low-noise Si bipolar transistor (BIT) receiver amplifier, and a highly sensitive TD comparator. The required received optical level at a 10^-9error rate was -31.9 dBm for 2 Gbits/s with a Ge APD/Si BIT front end having a 50 Ω input impedance. A Ge APD/ GaAs FET front end, with a 500 Ω input impedance, brought about 2 dB improvement at 100 Mbits/s, as compared with a Ge APD/Si BIT (50 Ω) front end. A coupling loss of 4 dB, achieved by a hemispherical microlens tipped on a single-mode fiber, and a low fiber loss of 0.57 dB/km, including splice loss, enabled 44.3 km single-mode fiber transmission at 2 Gbits/s. The 1.3 μm transmission system has a data rate repeater-spacing product of 88.6 (Gbit/s)km. Prospects of Gbit/s receiver sensitivity and the 2 Gbit/s transmission system, with more than 50 km repeater spacing, are also discussed.     

68.3 km transmission with 1.37 Tbit km/s capacity using wavelength division multiplexing of ten single-frequency lasers at 1.5 ?m

We describe the first single-fibre lightwave transmission system with more than 1 Tbit km/s capacity. The ultrahigh-capacity transmission over 68.3 km of low-loss single-mode fibre was achieved by closely spaced wavelength division multiplexing of ten distributed feedback lasers. The lasers operated around 1.5 ?m wavelength and the multiplexer channel spacing was 1.35 nm. Each laser/channel was modulated at 2 Gbit/s giving a total transmission capacity of 1.366 Tbit km/s.     

A time division multiplexer IC for bit rates up to about 2 Gbits/s

A bipolar 4:1 time-division multiplexer IC developed for a planned 1.12 Gbit/s optical communication system is presented. Without resorting to sophisticated technology, the high speed was achieved by modification of well-known circuit concepts and by careful circuit optimization. With a current-switch output, reliable operation was measured to over 2 Gbit/s compared to over 1.5 Gbit/s if emitter-follower outputs are used. The experimental results agree very well with the simulation predictions.     

GigaHertz MUX-DEMUX Chip with HF BIST

Full functional test at speed, in-situ is an ideal choice for use for detection of errors in circuit behaviour for high speed broadband communication circuits and to avoid test set-up disturbances on high frequency signals. This article presents a novel technique to solve the high frequency test of Gbit/s data rate Time-Division Multiplexer/Demultiplexer circuits. This in-situ test technique is based on conventional pseudo-random sequence generation and signature analysis. By linear feedback interconnect and reusable architecture the multiplexer/demultiplexer circuits can operate as generator/analyser with minimal degeneration of bit shift rate. Circuit simulation showed that the system operates correctly with a clock frequency up to 3 GHz in a silicon bipolar technology with a current gain cut-off frequency f _T = 15 GHz.     

A 9.5-Gb/s Si-bipolar ECL array

A 9.5-Gb/s Si-bipolar ECL array that has a gate delay of 35 ps, a risetime of 45 ps, and a falltime of 40 ps is described. The ECL circuit design and the chip layout were optimized. A Si-bipolar process with 0.3-μm emitter width and packaging capable of accepting 10-GHz signal were used. The array was used in three key circuits of an optical communication system: a decision circuit, a 4:1 multiplexer, and a 1:4 demultiplexer. Operation of the decision circuit at 9.5 Gb/s, of the 4:1 multiplexer at 6.7 Gb/s, and of the 1:4 demultiplexer at 6.7 Gb/s were confirmed     

20 Gbit/s optical time multiplexing with TJS GaAlAs lasers

Optical time multiplexing has been demonstrated using ultrashort optical pulses (30 ps) generated by direct modulation of TJS GaAlAs lasers. With the detection method used, an intensity correlator using second-harmonic generation in LiIO3, a bit rate of 20 Gbit/s was observed. However, the ultrashort optical pulses generated by the TJS lasers indicate that optical time multiplexing at 30 Gbit/s can be achieved.     

Over 80 Gbit/s 2:1 multiplexer and low power selector ICs using InP/InGaAs DHBTs

A 2:1 multiplexer (MUX) and low power selector ICs have been successfully designed and manufactured using an InP/InGaAs DHBT technology. The 2:1 MUX has been tested at data rates up to 80 Gbit/s with an output swing of 600 mV, while the selector IC has achieved operation speed up to 90 Gbit/s at a power consumption of only 385 mW.     

40-Gbit/s TDM transmission technologies based on ultra-high-speedICs

This paper presents 40-Gbit/s time division multiplexing (TDM) transmission technologies based on 0.1-μm-gate-length InP high electron mobility transistor IC's and a scheme for upgrading toward a terabit-per-second capacity system. A 40-Gbit/s, 300-km, in-line transmission experiment and a dispersion-tolerant 40-Gbit/s duobinary transmission experiment are described as 40-Gbit/s single carrier system applications on dispersion-shifted fiber. An ultra-high-speed receiver configuration using a high-output-power photodiode is introduced to realize fully electrical receiver operation beyond 40 Gbit/s. The high-sensitivity operation of the optical receiver (-27.6 dBm@BER=10^-9) is demonstrated at a data bit rate of 50 Gbit/s for the first time using a unitraveling carrier photodiode. A dense wavelength division multiplexing (DWDM) system operating up to terabits per second can be easily realized on a zero-dispersion flattened transmission line using ultra-high speed TDM channels of 40 Gbit/s and beyond. An experiment demonstrates 1.04-Tbit/s DWDM transmission based on 40-Gbit/s TDM channels with high optical spectrum density (0.4 bit/s/Hz) without dispersion compensation     

Diode multiplexer in the multi-Gbit/s range

A clocked multiplexer circuit was realised which provided 4.48 Gbit/s, 5 Gbit/s, and 7.84 Gbit/s output-pulse streams for p.c.m.-type input tributaries at 1.12 Gbit/s, 0.25 Gbit/s, and 1.12 Gbit/s, respectively. The circuit employed essentially ultra-broadband 180° hybrids, step-recovery diodes, and GaAs Schottky-barrier diodes. Output voltages up to 2 V were obtained across a load of 50 ?. The pulse width of the output pulses was approximately 100 ps.     

An STS-N byte-interleaving multiplexer/scrambler anddemultiplexer/descrambler architecture and its experimental OC-48implementation

The authors present a byte-interleaving architecture for generating higher-order signals in the synchronous optical network (SONET) digital hierarchy and report on the implementation and system performance results of an experimental 2.488 Gbit/s SONET STS-3c to STS-48 (OC-48) byte multiplexer/scrambler and STS-48 (OC-48) to STS-3c byte demultiplexer/descrambler. The proper operation of the byte multiplexer and demultiplexer has been verified in an OC-48 experiment with a bit error rate (BER) of less than 10^-14. It is shown that the byte-interleaving architecture leads to a simple and modular implementation of higher-rate interfaces (such as OC-192 at 9.95 Gbit/s) using state-of-the-art technologies     

An analysis of gain-switched semiconductor lasers generating pulse-code-modulated light with a high bit rate

A theoretical analysis of gain-switched semiconductor lasers is described. Results of the numerical solution of the coupled rate equations for photon and electron densities are presented, along with analytical expressions which have been derived by using certain approximations to solve these nonlinear differential equations. The two sets of results are seen to be in good agreement. The design requirements to be met in order to use the pulse-code-modulated output in an optical communications system are discussed. It is shown theoretically that bit rates, of the order of 7 Gbits/s without time-division multiplexing, and 35 Gbits/s with multiplexing can be obtained.     

2×10 Gbit/s WDM 1310-nm optical transmission over 63.5-kmstandard single-mode fiber using optical preamplifiers

Twenty Gbit/s transmission over 63.5 km SMF at 1310 nm is reported by using two channel 10 Gbit/s wavelength (de)multiplexing (Δλ=1.5 nm). Two 1310 nm SL-MQW semiconductor optical amplifiers are utilized for loss compensation and sensitivity improvement. For the 1310 nm wavelength domain, a record bitrate x distance product of 1.27 Tbit/s.km has been obtained. Crosstalk penalties are identified, and the feasibility of an extension up to at least four, 10 Gbit/s channels is discussed