Ku波段20W AlGaN/GaN功率管内匹配技术研究

文章的主要目的是研究第三代半导体AlGaN/GaN功率管内匹配问题。以设计Ku波段20WGaN器件为例,研究了内匹配电路的设计、合成以及内匹配电路的测试,实现了GaN功率HEMT在Ku波段20W连续波输出功率的内匹配电路,并使整个电路的输入、输出电路阻抗提升至50Ω。最终所研制的AlGaN/GaNKu波段内匹配功率管在11.8GHz～12.2GHz频带内,输出功率大于20W。在12GHz功率增益大于5dB,功率附加效率29.07%,是目前国内关于GaN功率器件在Ku波段连续波输出的最高报道。     

Wide-band GaInAs MISFET amplifiers

The authors present the first reported results on wideband GaInAs MISFET amplifiers. Using 1-μm-gate-length, 0.56-mm-gate-width GaInAs MISFETs, they obtained: (a) a power output of 230±30 mW (0.41 W/mm) with 33±3% power-added efficiency; (b) a power output of 265±15 mW (0.47 W/mm) with 30±3% power-added efficiency (both over the 7-11-GHz band), and (c) a power output of 220±45 mW (0.39 W/mm) with 32±4% power-added efficiency over the 6-12-GHz band. With a 0.7-μm-gate-length GaInAs MISFET, a small-signal gain of 5±0.5 dB over the 11.4-22.6-GHz band was obtained. These data include all connector, bias network, and circuit losses. The authors present an equivalent circuit model of these MISFETs based on S-parameter measurements. The model is essentially that of a MISFET with capacitors representing gate-to-source and gate-to-drain overlap capacitances added at input and output     

High performance 10-12.5 Gbit/s modulator driver in InP SHBT technology

A high performance modulator driver circuit is presented using 4" InP SHBT technology. The IC was developed for driving EAM modulators in OC-192 (10 Gbit/s) and with forward error correction (FEC: 10.7 Gbit/s or 12.5 Gbit/s) optical fibre systems. The monolithic integrated circuit features output amplitude control, output crossing point control and output DC offset control. Measured results show the circuit operates at 10 to 12.5 Gbit/s with a swing of 3.1 V/sub p-p/ at each output and 20/18 ps rise/fall times. The power dissipation is 1.4 W with a standard power supply of -5.2 V.     

40-Gb/s high-power modulator driver IC for lightwave communicationsystems

A monolithic integrated modulator driver with a data decision function for high-speed optical fiber links is presented. The integrated circuit (IC) was manufactured in a 0.2-μm gate length AlGaAs/InGaAs high electron mobility transistor technology with an f_T of 68 GHz. The modulator driver IC features differential configuration and operates up to 40 Gb/s with a clock phase margin of 210° and an output voltage swing of 2.9 V_p-p at each output. The maximum slew rate of the output signal is 200 mV/ps. The power dissipation of the circuit is 1.6 W using a single supply voltage of -5 V     

A high-efficiency class-E GaN HEMT power amplifier at 1.9 GHz

A single stage class-E power amplifier in GaN high electron mobility transistor (HEMT) technology is reported. The circuit operates at 1.9 GHz. At 30-V drain bias, a power-added-efficiency (PAE) of 57% and a maximum output power of over 37dBm was achieved, corresponding to a power density of 5.25W/mm. At 40-V drain bias, an output power of 38.7dBm is achieved at 50% PAE corresponding to a power density of 7.4W/mm.     

Generation of square and triangular wave with independently controllable frequency and amplitude using OTAs only and its application in PWM

This paper presents a self-generating square/triangular wave generator using only the CMOS Operational Transconductance Amplifiers (OTAs) and a grounded capacitor. The output frequency and amplitude of the proposed circuit can be independently and electronically adjusted. The proposed circuit validates its advantage by consuming less amount of power, which is about 71.3 µW. The theoretical aspects are authentically showcased using the PSPICE simulation results. The performance of the proposed circuit is also verified through pre layout and post layout simulation results using the 90 nm GPDK CMOS parameters. A prototype of this circuit has been made using commercially available IC CA3080 for experimental verification. Experimentation also gives the similar output as per the theoretical proposition. The designed circuit is also made applicable to perform pulse width modulation (PWM).     

A 75 μW rail-to-rail class AB CMOS operational amplifier

A new class AB CMOS operational amplifier featuring rail-to-rail output swing is presented. The proposed circuit operates with an output voltage supply of 1 V only, while the overall power consumption is lower than 75 μW. The output stage shows a quiescent current of 15 μA, while it guarantees a peak current of 220 μA. The slew rate is 1.5 V μs⁻¹ (C₁ = 150 pF) and the THD is −63 dB, when a 0.98 V_pp−10.4 kHz sinewave is applied, as measured on an experimental prototype realised with a standard 0.8 μm CMOS process. The circuit presented is suitable for use in portable hand-set systems or in medical aids.     

An integrated photodetector-amplifier using a-Si p-i-n photodiodesand poly-Si thin-film transistors

The authors propose a photodetector-amplifier circuit consisting of a bridge photodetector circuit and a CMOS differential amplifier, both monolithically integrated on a transparent substrate. A test circuit was fabricated using a-Si p-i-n photodiodes and poly-Si thin-film transistors on a quartz substrate. A clear effect of the differential amplifier was demonstrated in the test circuit. It is shown that the circuit performance can be controlled by changing the bias current of the differential amplifier. With a relatively low bias current on the order of 10^-11 A, the circuit works digitally with output voltages either close to 0 V or V_DD. The power consumption of the circuit is approximately 60 μW, which is low enough for use in two-dimensional arrays     

2.5W低噪声CMOSD类音频功放设计

提出了一种基于0.5μm5VCMOS工艺的低噪声PWM调制D类音频功率放大器。该放大器在5V电源电压下以全桥方式可以驱动4Ω负载输出2.5W功率;转换效率等于87%,信噪比达94dB(负载8Ω,输出功率1W);THD+N仅0.05%(负载4Ω,输出功率1W);PSRR为68dB(频率1kHz)。分析了整体电路结构及其线性化模型,并着重介绍了高性能前置斩波稳定运算放大器(开环增益117dB,等效输入噪声16μV.Hz-1/2),线性三角波振荡电路(斜率偏差仅±0.2%)和功率器件、驱动电路的设计。最后给出了D类放大器的测试结果。     

40 Gbit/s monolithic integrated modulator driver in InP SHBT technology

A high-speed and high-gain modulator driver circuit is presented using 4-inch InP SHBT technology. The IC was developed for driving EAM modulators in 40 Gbit/s optical fibre systems. The monolithic integrated circuit features output amplitude control and output crossing point control. Measured results show the circuit operates at 40 Gbit/s with a swing of 2.5 V/sub p-p/ at each output and 9/8 ps rise/fall times. The power dissipation is 1.5 W with a standard power supply of -5.2 V.     

An X-Band High-Power and High-PAE PHEMT MMIC Power Amplifier for Pulse and CW Operation

An X-band high-power and high power added efficiency (PAE), two-stage AlGaAs/InGaAs/GaAs psuedomorphic high electronic mobility transistor (PHEMT) monolithic microwave integrated circuit (MMIC) power amplifier is presented. The amplifier is designed to fully match a 50 Omega input and output impedance. Based on a 0.35 mum gate-length power PHEMT technology, the MMIC is fabricated on a 3 mil thick wafer. Under an 8 V DC bias condition, the characteristics of 17.5 dB small-signal gain, 10 W continuous wave mode saturation output power of 42% PAE, and 12.6 W pulse saturation output power of 52.6% PAE at 9.4 GHz can be achieved.     

一种反激式LED恒流驱动电路的设计与实现

设计了一种输出功率达120W的反激式变换LED恒流驱动电路,其输出电压范围为33～37V,可为120只功率为1W的LED管采用10串12并混联方式组成的LED阵列提供驱动电流。对其功率因数校正电路、反激式变换电路、恒流控制电路进行了设计和试制,性能测试表明,其输出恒流效果较好,电流稳定度约2.7%,输出电压纹波低,可用于恒流驱动混联方式组成的多只LED阵列。     

ESD protection design on analog pin with very low input capacitancefor high-frequency or current-mode applications

An electrostatic discharge (ESD) protection design is proposed to solve the ESD protection challenge to the analog pins: for high-frequency or current-mode applications, By including an efficient power-rails clamp circuit in the analog input/output (I/O) pin, the device dimension (W/L) of an ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (μm/μm) in a 0.35-μm silicided CMOS process, but it can sustain the human body model (HBM) and machine model (MM) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only ~1.0 pF (including the bond-pad capacitance) for high-frequency applications     

A series-resonant DC/AC inverter for impedance-load drives

A DC/AC inverter without cycloconversion configured by a half-bridge series-resonant inversion (HB-SRI) circuit is presented. The inverter is a series resonator with two auxiliary switches in shunt with the resonant capacitor so as to configure adaptively the output current suitable for impedance load. The output sinusoidal voltage is synthesized by a series of equal-amplitude quasisinusoidal pulses (QSPs) and the corresponding current is formed by unequal QSPs and adaptively phase-shifts to the impedance load. The presented HB-SRI is operated by frequency modulation with a constant-on time control. System modeling and waveform syntheses for the output sinusoidal voltage and its current are clearly derived, A typical design example of a 500 W HB-SRI inverter is examined to assess the system performance. The power efficiency is over 90% when the inverter output is above 200 W. The total harmonic distortions (THDs) for various impedance loads are all within 6%     

Silicon-on-Sapphire Complementary MOS Memory Cells

Complementary MOS circuitry offers the advantages of high-speed, low-quiescent power dissipation, and loose device parameter tolerances. However, only with the recent development of clean technology has it been possible to fabricate stable devices. The advances in silicon-on-sapphire epitaxy have permitted the development of a high-speed low-power complementary MOS circuit module. This paper describes the circuit, its operation, the method used in fabricating it in silicon-on-sapphire, and the switching performance of the circuit. The basic memory cell is a NDRO flip-flop with feedback supplied through a transmission gate. The total circuit delay from write command to output sense signal is 5 to 7 ns at a standby power dissipation of 7 to 20 /spl mu/ W. To show the feasibility of adapting silicon-on-sapphire complementary MOS technology to LSI, a 9-bit word (1-byte) was constructed. The entire module containing 54 N-channel and 36 P-channel devices dissipated less than 100 /spl mu/ W in a standby condition.     

A Compact C‐Band 50 W AlGaN/GaN High‐Power MMIC Amplifier for Radar Applications

A C‐band 50 W high‐power microwave monolithic integrated circuit amplifier for use in a phased‐array radar system was designed and fabricated using commercial 0.25 μm AlGaN/GaN technology. This two‐stage amplifier can achieve a saturated output power of 50 W with higher than 35% power‐added efficiency and 22 dB small‐signal gain over a frequency range of 5.5 GHz to 6.2 GHz. With a compact 14.82 mm² chip area, an output power density of 3.2 W/mm² is demonstrated.     

开关电容功率因数补偿模块的研究

论述了采用开关电容功率因数补偿模块改善整流装置的输入电流波形的方法。在对工作原理进行分析的基础上，采用PSpice仿真的方法，综合以提高输入端功率因数和转换效率、降低输入电流谐波含量和输出电压脉动系数为目标，分别对输出功率为60W，40W和15W的具有开关电容功率因数补偿模块的电子镇流器的参数进行优化，得到了具有实用价值的结果。     

A 1.6-GS/s 12-bit return-to-zero GaAs RF DAC for multiple Nyquist operation

A 12-bit 1.6-GS/s digital-to-analog converter (DAC) implemented with 4-/spl mu/m/sup 2/ GaAs HBT process is presented. Return-to-zero (RZ) current switches are added to current steering DAC for high-frequency wideband applications to achieve 800-MHz bandwidth at first and second Nyquist band without the need for a reverse sinc equalization filter in wideband transmitter application. The RZ circuit also improves spectral purity by screening the switching noise from the analog output during data transition. Measured performance shows two-tone third-order harmonic distortion of -70 dB at 1.5-GHz output frequency, clocked at 1.6 GHz. Reliable interface with CMOS logic IC is guaranteed with the inclusion of a four-clock-deep FIFO circuit. The DAC dissipates 1.2 W at -5 V when sampled with 1.6-GHz clock, with typical output voltage swing of 1.2 V/sub PP/.     

基于AC/DC数字电源控制器iw1810的LED驱动电路设计

IW1810集成了一个64 kHz的PWM控制器和一个800 V的BJT,该芯片采用数控技术,工作在准谐振模式,提供过流和输出过压保护,简化外围元件确保电路的高效性,无载功率小于100 mW。设计一款基于IW1810高度集成、高效恒流的AC/DC LED驱动电路,电路工作在90 V到264 V的宽电压范围内,输出恒流340 mA,输出功率为4 W,效率高达80%以上,电路板面积仅为18 mm×38 mm。     

Single-stage single-switch input-current-shaping technique withfast-output-voltage regulation

A new single-stage single-switch input-current-shaping (S⁴ ICS) technique, which combines the boost-like input-current shaper with a continuous-conduction-mode (CCM) DC/DC output stage, is described. In this technique, the boost inductor can operate in both the discontinuous conduction mode (DCM) and CCM. Due to the ability to keep a relatively low voltage (<450 V_DC) on the energy-storage capacitor, this technique is suitable for the universal line-voltage applications. The voltage on the energy-storage capacitor is kept within the desirable range by the addition of two transformer windings. The principle of operation of the S⁴ICS circuit with a forward DC/DC converter is presented. Experimental results obtained on a 100 W (5 V/20 A) prototype circuit are also given