共查询到20条相似文献,搜索用时 31 毫秒
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低功率LDO稳压器适合于在便携式电子设备和电池供电系统中应用。本介绍了不同种类的新型LDO稳压器IC及其特点。 相似文献
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LT1468是Analogue Linear Technology公司最新设计的单个可折叠式共基共射型运算放大器.利用LT1468可以克服其它类型放大器带宽窄、转换速率低和建立时间长等缺陷.LT1468运算放大器可应用于16位系统,且能有效抑制滤波器和仪器本身精度所带来的失真. 相似文献
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本文提出了一种工作于22 GHz-29 GHz的宽带低剖面高增益低副瓣阵列天线。天线由64个(8×8)子阵列组成,采用泰勒幅度加权进行非均匀馈电从而实现低副瓣。馈电网络采用悬置带状线结构,可有效降低馈电网络剖面高度;辐射网络采用8条CTS(continuous Transverse Stub)结构等间距排列,能有效降低损耗和实现宽带性能。通过HFSS仿真得到的结果表明,其阻抗带宽为27.5%,最终实现在工作频段范围内反射系数均小于-15 dB,且在E面和H面的副瓣电平均小于-20 dB,整体增益高于24.5 dBi。 相似文献
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A low power and low phase noise phase-locked loop(PLL) design for low voltage(0.8 V) applications is presented.The voltage controlled oscillator(VCO) operates from a 0.5 V voltage supply,while the other blocks operate from a 0.8 V supply.A differential NMOS-only topology is adopted for the oscillator,a modified precharge topology is applied in the phase-frequency detector(PFD),and a new feedback structure is utilized in the charge pump(CP) for ultra-low voltage applications.The divider adopts the extende... 相似文献
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In this paper a novel low input impedance current mirror/source is proposed. The principle of its operation compared to that
of the simple current mirror is discussed. Also are given the comparative simulation results with HSPICE in TSMC 0.18 μm CMOS
which verify the theoretical formulation and operation of the proposed structure. Simulation results show an input resistance
for the proposed current mirror about 0.006 Ω. This is 4 × 105 times lower than that of the simple one while both working with 1.5 V supply and 50 μA bias current. It consumes only 161 μW
and exhibits an excellent current error value of Zero at 55 μA which remains below 0.6% up to 100 μA. Favorably its minimum
output voltage is reduced to 0.2 V. 相似文献
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本文提出了一种低电压应用的低功耗、低相位噪声锁相环(PLL)。其中压控振荡器(VCO)的工作电压为0.5V,其他模块的工作电压为0.8V。为了适应极低电压下的应用,文中振荡器采用了纯NMOS差分拓扑结构,鉴频鉴相器(PFD)采用改进的预充电结构,而电荷泵(CP)采用新型负反馈结构。预分频电路采用扩展的单相时钟逻辑电路构成,它可以工作在较高的频率下,节省了芯片面积和功耗。此外还采用了去除尾电流源等设计方法来降低相位噪声。采用SMIC 0.13μm RF CMOS工艺,在0.8V电源电压下,测得在整个锁定范围内,最差相位噪声为-112.4dBc/Hz@1MHz,其输出频率范围为3.166~3.383GHz。改进的PFD和新型CP功耗仅为0.39mW,占据的芯片面积仅100μm×100μm。芯片总面积为0.63mm2,在0.8V电源电压下功耗仅为6.54mW 。 相似文献
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This paper describes a novel divide-by-32/33 dual-modulus prescaler(DMP).Here,a new combination of DFF has been introduced in the DMP.By means of the cooperation and coordination among three types,DFF, SCL,TPSC,and CMOS static flip-flop,the DMP demonstrates high speed,wideband,and low power consumption with low phase noise.The chip has been fabricated in a 0.18-μm CMOS process of SMIC.The measured results show that the DMP’s operating frequency is from 0.9 to 3.4 GHz with a maximum power consumption of 2.51 mW under a 1.8 V power supply and the phase noise is -134.78 dBc/Hz at 1 MHz offset from the 3.4 GHz carrier.The core area of the die without PAD is 57×30μm~2.Due to its excellent performance,the DMP could be applied to a PLL-based frequency synthesizer for many RF systems,especially for multi-standard radio applications. 相似文献
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Single-mode-fibre designs with segmented core for achieving simultaneously low loss and dispersion are described. Results showing dispersion flattening of ± 1.5 ps/km nm over a 280 nm range are presented. Such dispersion flattening is achieved while maintaining spot sizes of 4?5 ?m, which compare favourably with those for earlier designs without dispersion flattening. 相似文献
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本文设计了应用SCL、TPSC和CMOS静态三种类型的触发器配合工作的新型双模预分频器。与传统使用单一种类型触发器的双模预分频器相比,该双模预分频器更容易获得高速、宽带、低功耗和低相位噪声的性能。为了验证此设计的性能,采用了SMIC 0.18um CMOS 工艺流片实现。在电源电压为1.8V的条件下测试,此双模预分频器的工作频率范围从0.9 GHz 到 3.4 GHz ;当输入信号为 3.4 GHz时,其功耗为2.51mW,相位噪声为-134.78 dBc/Hz @ 1 MHz. 其核心面积为 is 57um*30um。鉴于其良好的性能,可以应用于许多射频系统的频率综合器中,特别在多标准无线通信系统中。 相似文献
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基于0.13μm锗硅(SiGe)双极型互补金属氧化物(Bipolar Complementary Metal Oxide Semi-conductor,BiCMOS)工艺,设计制作了一种高增益低功耗K频段低噪声放大器(Low Noise Amplifier,LNA),通过优化晶体管尺寸及利用硅通孔设计高品质因数射极退化电感,降低了LNA噪声.实测结果表明,在1.6 V偏置条件下,该LNA在20 GHz的噪声系数等于1.94 dB,输入1 dB压缩点等于-29.6 dBm;18~21.3 GHz频率范围内,LNA增益大于23.3 dB,S11和S22均小于-10 dB.包含偏置电路功耗在内,芯片功耗仅21 mW,优于其他同等噪声系数的K频段SiGe BiCMOS LNA.该LNA可应用于卫星通信等K频段低功耗接收机系统. 相似文献
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