A 1 V power amplifier for 81–86 GHz E-band

The design and layout of a two stage SiGe E-band power amplifier using a stacked transformer for output power combination is presented. In EM-simulations with ADS Momentum, at E-band frequencies, the power combiner consisting of two individual single turn transformers performs significantly better than a single 2:1 transformer with two turns on the secondary side. Imbalances in the stacked transformer structure are reduced with tuning capacitors for maximum gain and output power. At 84 GHz the simulated loss of the stacked transformer is as low as 1.35 dB, superseding the performance of an also presented alternative power combiner. The power combination allows for a low supply voltage of 1 V, which is beneficial since the supply can then be shared between the power amplifier and the transceiver, thereby eliminating the need of a separate voltage regulator. To improve the gain of the two-stage amplifier it employs a capacitive cross-coupling technique not yet seen in mm-wave SiGe PAs. Capacitive cross-coupling is an effective technique for gain enhancement but is also sensitive to process variations as shown by Monte Carlo simulations. To mitigate this two alternative designs are presented with the cross coupling capacitors implemented either with diode coupled transistors or with varactors. The PA is designed in a SiGe process with f _T  = 200 GHz and achieves a power gain of 12 dB, a saturated output power of 16 dBm and a 14 % peak PAE. Excluding decoupling capacitors it occupies a die area of 0.034 mm².     

A 0.5–2.5 GHz 910 uW complementary LNA employing positive–negative feedback

A 0.5–2.5 GHz ultra low power differential resistive feedback common gate low noise amplifier (RFCGLNA) without the use of inductor is presented. The proposed RFCGLNA adopts the NMOS and PMOS complementary topology to reduce the power consumption by half. Based on common-gate topology, the proposed RFCGLNA employs capacitive cross-coupling (CCC) and resistive feedback techniques. The CCC technique can further reduce the power consumption by half. The resistive feedback technique can constrain the common mode voltages of the proposed RFCGLNA and meanwhile, improve the third-order input intercept point (IIP3). The DC path is supplied by the current source transistor which forms a positive feedback loop to improve the gain at low frequency. Implemented with 65 nm standard complementary metal oxide semiconductor (CMOS) technology, the measured performance achieves 15 dB gain with S₁₁ < ?10 dB in the 0.5–2.5 GHz band. The noise figure (NF) is 3.9–5.0 dB and the IIP3 is 3.1–3.6 dBm. The power consumption is only 910 uW.     

A Miniaturized Monolithic 18–40 GHz Sub-harmonic Mixer

In this paper, a miniaturized 18–40 GHz sub-harmonic mixer is designed and implemented with 0.15 μm GaAs pHEMT process. The proposed mixer employs anti-parallel diode pair with parallel to ground configuration, and a novel coupler structure to feed RF and LO signals, resulting in broadband performance and compact chip size. The measured conversion loss is 10.3–13.5 dB in a wide operation frequency band of 18–40 GHz. The chip size is 0.66 mm².     

A 0.1–4 GHz SDR receiver with reconfigurable 10–100 MHz signal bandwidth in 65 nm CMOS

A 0.1–4 GHz software-defined radio (SDR) receiver with reconfigurable 10–100 MHz signal bandwidth is presented. The complete system design methodology, taking blocker effects into account, is provided. Fully differential Op-Amp with Miller feedback and feed-forward compensations is proposed to support wideband analog circuits with low power consumption. The stability and isolation of inverter-based trans-conductance amplifier are analyzed in details. The design approach of high linearity Tow-Thomas trans-impedance amplifier is presented to reject out-of-band blockers. To compensate for PVT variations, IIP2, frequency tuning, DC offset and IQ calibration are also integrated on-chip. The SDR receiver has been implemented in 65 nm CMOS, with 1.2/2.5 V power supply and a core chip area of 2.4 mm². The receiver achieves S11 input matching below ?10 dB and a NF of 3–8 dB across the 0.1–4 GHz range, and a maximum gain of 82–92 dB with a 70 dB dynamic range. Dissipated power spans from 30 to 90 mW across this entire frequency range. For LTE application with 20 MHz signal bandwidth and a LO frequency of 2.3 GHz, the receiver consumes 21 mA current.     

System simulations of a 1.5 V SiGe 81–86 GHz E-band transmitter

This paper presents simulation results for a sliding-IF SiGe E-band transmitter circuit for the 81–86 GHz E-band. The circuit was designed in a SiGe process with f _T  = 200 GHz and uses a supply of 1.5 V. The low supply voltage eliminates the need for a dedicated transmitter voltage regulator. The carrier generation is based on a 28 GHz quadrature voltage oscillator (QVCO). Upconversion to 84 GHz is performed by first mixing with the QVCO signals, converting the signal from baseband to 28 GHz, and then mixing it with the 56 GHz QVCO second harmonic, present at the emitter nodes of the QVCO core devices. The second mixer is connected to a three-stage power amplifier utilizing capacitive cross-coupling to increase the gain, providing a saturated output power of +14 dBm with a 1 dB output compression point of +11 dBm. E-band radio links using higher order modulation, e.g. 64 QAM, are sensitive to I/Q phase errors. The presented design is based on a 28 GHz QVCO, the lower frequency reducing the phase error due to mismatch in active and passive devices. The I/Q mismatch can be further reduced by adjusting varactors connected to each QVCO output. The analog performance of the transmitter is based on ADS Momentum models of all inductors and transformers, and layout parasitic extracted views of the active parts. For the simulations with a 16 QAM modulated baseband input signal, however, the Momentum models were replaced with lumped equivalent models to ease simulator convergence. Constellation diagrams and error vector magnitude (EVM) were calculated in MATLAB using data from transient simulations. The EVM dependency on QVCO phase noise, I/Q imbalance and PA compression has been analyzed. For an average output power of 7.5 dBm, the design achieves 7.2% EVM for a 16 QAM signal with 1 GHz bandwidth. The current consumption of the transmitter, including the PA, equals 131 mA from a 1.5 V supply.     

A 11.2 mW 48–62 GHz Low Noise Amplifier in 65 nm CMOS Technology

In this paper, a wideband low noise amplifier (LNA) for 60 GHz wireless applications is presented. A single-ended two-stage cascade topology is utilized to realize an ultra-wideband and flat gain response. The first stage adopts a current-reused topology that performs the more than 10 GHz ultra-wideband input impedance matching. The second stage is a cascade common source amplifier that is used to enhance the overall gain and reverse isolation. By proper optimization of the current-reused topology and stagger turning technique, the two-stage cascade common source LNA provides low power consumption and gain flatness over an ultra-wide frequency band with relatively low noise. The LNA is fabricated in Global Foundries 65 nm RFCMOS technology. The measurement results show a maximum \(S_{21}\) gain of 11.4 dB gain with a \(-\)3 dB bandwidth from 48 to 62 GHz. Within this frequency range, the measured \(S_{11}\) and \(S_{12}\) are less than \(-\)10 dB and the measured DC power consumption is only 11.2 mW from a single 1.5 V supply.     

A 4.6 GHz cascade switched biasing LC–QVCO using source-body resistor

This paper presents a 4.6 GHz LC quadrature voltage-controlled oscillator (QVCO) in which the phase noise performance is improved by two methods: cascade switched biasing (CSB) technique and source-body resistor. The CSB topology can reduce the resonator loss caused by MOSFET resistance. Meanwhile, it can maintain the benefits of conventional switched biasing technique. The source-body resistors are utilized to reduce the noise contribution of the substrate related to the cross coupled MOSFETs. The proposed QVCO has been implemented in standard 0.18 μm CMOS technology. With the two methods mentioned above, it consumes 4.9 mW under 1 V voltage supply and achieves a phase noise of ?120.3 dBc/Hz at 1 MHz frequency offset from the carrier of 4.56 GHz. The figure of merit is 186.5 dBc/Hz and the tuning range is from 4.2 G to 5 GHz (17.3 %). When the QVCO operates at 0.8 V voltage supply, the power consumption is 2.88 mW and the phase noise is ?115.7 dBc/Hz at 1 MHz frequency offset from the carrier of 4.58 GHz.     

A 400 MHz–1.5 GHz all digital integer-N PLL with a reference spur reduction technique

In this Letter, 400 MHz–1.5 GHz all digital integer-N PLL with a reference spur reduction is proposed. A reference spur is occurred by updating DCO control code at every reference clock period. To reduce a reference spur component, the phase detector which transfers phase error information only when phase error is detected has been designed. The measured clock jitter is 2.528 ps_rms at 1.5 GHz operation, and 3.991 ps_rms at 400 MHz operation. The ADPLL occupies 0.088 mm², and consumes 1.19 mW at 1.5 GHz. This ADPLL is implemented in 65 nm CMOS technology.     

A 0.5–1 GHz single stage linear-in-decibel VGA with 80 dB gain range in 0.18 μm CMOS

Communication systems require a wide gain range. For example the code-division multiple access system (CDMA) requires more than 80 dB of gain range so that, many variable gain amplifiers (VGAs) must be used, resulting in high power consumption and low linearity because of VGA non-linearity factors. In this paper, a one-stage VGA in 0.18 μm technology is presented. The VGA based on the class AB power amplifier is designed and simulated for a high linearity and an 80 dB tuning range. For the linear-in-decibel tuning range, transistors in sub-threshold region is used. The current control circuit of the VGA changes gain continuously from ?68 to 18 dB at 0.5 GHz and ?60 to 20 dB at 1 GHz with gain error of less than 2 dB. The power consumption enjoys a highest value about 13.5 mW in the maximum gain and P1dB is also about ?3.4 dBm at 0.5 GHz and 2.2 dBm at 1 GHz.     

Design of high-linearity 75–90 GHz CMOS down-conversion mixer for automotive radar

This paper presents a 75–90 GHz down-conversion mixer applied in automotive radar, which is characterized with high linearity, low local oscillator (LO) drive as well as high conversion gain (CG) using TSMC 65-nm CMOS general-purpose technology. The good linearity and isolation of mixer are required for automotive radar to cover short-middle-far range detection. The mixer includes an enhanced double-balanced Gilbert-cell core with series peaking transmission line and source degeneration technique for improving linearity and CG, two on-chip baluns and intermediate frequency (IF) buffer for IF test. Besides, to make the design more accurate and efficient, the modeling and design of millimeter-wave (mm-wave) passive devices are introduced. The mixer consumes 12 mW under 1.5 V. The input 1 dB compression point (P_1dB) is 2.5 dBm as well as IIP3 of 13.2 dBm at 80 GHz. High performances are achieved with the CG of 5 dB at 76 GHz with LO power of 0 dBm for frequencies of 75–90 GHz which covers the application of automotive radar frequency band (76–81 GHz) and LO-RF isolation of 33–37 dB for frequencies of 60–90 GHz. The area of the mixer is 0.14 mm², with PADs included.     

A low power CMOS phase-switching prescaler for 1.8–2.4 GHz wireless communications

A divide-by-31/32 phase switching prescaler with a simple divide-by-4 multi-phase ring counter is presented. By using this divide-by-4 unit, a low power consumption is obtained while a wide range operation is maintained. Fabricated with a standard 0.18 μm CMOS technology, the prescaler can work properly from 1.8 to 3.1 GHz with a maximum current dissipation of 1.3 mA from a 1.8 V supply voltage. It can cover most of wireless communication standards in 1.8/1.9 GHz and 2.4 GHz bands.     

A 0.4–2.3 GHz broadband power amplifier extended continuous class-F design technology

A 0.4–2.3 GHz broadband power amplifier (PA) extended continuous class-F design technology is proposed in this paper. Traditional continuous class-F PA performs in high-efficiency only in one octave bandwidth. With the increasing development of wireless communication, the PA is in demand to cover the mainstream communication standards’ working frequencies from 0.4 GHz to 2.2 GHz. In order to achieve this objective, the bandwidths of class-F and continuous class-F PA are analysed and discussed by Fourier series. Also, two criteria, which could reduce the continuous class-F PA’s implementation complexity, are presented and explained to investigate the overlapping area of the transistor’s current and voltage waveforms. The proposed PA design technology is based on the continuous class-F design method and divides the bandwidth into two parts: the first part covers the bandwidth from 1.3 GHz to 2.3 GHz, where the impedances are designed by the continuous class-F method; the other part covers the bandwidth from 0.4 GHz to 1.3 GHz, where the impedance to guarantee PA to be in high-efficiency over this bandwidth is selected and controlled. The improved particle swarm optimisation is employed for realising the multi-impedances of output and input network. A PA based on a commercial 10 W GaN high electron mobility transistor is designed and fabricated to verify the proposed design method. The simulation and measurement results show that the proposed PA could deliver 40–76% power added efficiency and more than 11 dB power gain with more than 40 dBm output power over the bandwidth from 0.4–2.3 GHz.     

A highly linear and fully-integrated FMCW synthesizer for 60 GHz radar applications with 7 GHz bandwidth

A highly linear and fully-integrated frequency-modulated continuous-wave (FMCW) generator based on a fractional-N phase-locked loop (PLL) that is able to synthesize modulation schemes in 57–64 GHz range is proposed in this paper. The fractional-N PLL employs Colpitts voltage-controlled oscillator (VCO) at 60 GHz with 13.5% tuning range. Automatic amplitude and frequency calibrations are implemented to avoid drifts due to process, voltage and temperature variations and to set the center frequency of the VCO. Five-stage multi-modulus divider is used for division ratio switching, controlled by the sigma-delta (\(\Sigma \Delta\)) modulator MASH 1-1-1. The frequency sweep (chirp) bandwidth and duration are fully programmable via serial peripheral interface allowing up to 16 different chirps in complex modulation scheme. The PLL reference signal is 250 MHz provided by external low-noise signal generator which is also used for digital modules clock. The overall PLL phase noise is lower than ?80 dBc/Hz at 10 kHz offset and the chirp linearity is better than 0.01%. The complete FMCW synthesizer is implemented and verified as a stand-alone chip in a commercially available SiGe HBT 130 nm BiCMOS technology. The total chip area is \(2.04\,\text {mm}^2\), and the total power consumption is 280 mW.     

New design of 3.2–4.8 GHz generator for multi-bands architecture of UWB communication

In this paper a new design of Ultra-Wide Band (UWB) generator is presented. This circuit is the most important block in multi-bands transmitter architecture of UWB communication system. The proposed UWB generator is composed of multi-bands voltage controlled oscillator (VCO), mixer and rectangular pulse generator which consist of ring oscillator, time delay and AND gate function. The UWB generator is based on multiplying the rectangular pulse envelope to a continuous sinusoidal wave in order to generate the UWB signal. This UWB generator circuit produces an output signal which is characterized by the bandwidth of 1600 MHz divided into three sub-bands of 528 MHz, centered at frequencies of 3.432, 3.96, 4.488 GHz and the limited Power Spectral Density (PSD) is −41.44 dBm/MHz. The maximum amplitude of UWB signal is 214 mV, the pulse is during of 3 ns and the pulse repetition period (PRP) is 32 ns. The power consumption is approximately equal to 26 mW at a voltage supply of 2.5 V. This topology is designed in CMOS 0.35 μm AMS process technology.     

A 6–9 GHz UWB balun-LNA employing current-reuse with preamplifier and CCC buffer

This paper presents a high-gain and low-power balun-LNA for ultra-wideband receiver operating in the upper band (6–9 GHz). Common gate (CG) preamplifier in front of the active balun can provide input matching and suppress noise from the follow-up stages. Active balun shares bias current with the CG stage to reduce power consumption. Capacitor-cross-coupled buffer is cascaded for signal amplitude and phase correction. The balun-LNA is fabricated in TSMC 130 nm CMOS technology and it consumes 5.5 mA current from a 1.3-V supply including buffer. This balun-LNA can achieve wideband gain from 6.5 to 9.0 GHz and the maximum gain is 23 dB. The input return loss is better than 20 dB from 6.5 to 9.0 GHz. The core area of the LNA is 0.53 mm². Simulated noise figure of the LNA is under 3.2 dB.     

A 0.4–3.3 GHz low-noise variable gain amplifier with 35 dB tuning range, 4.9 dB NF,and 40 dBm IIP2

This work presents a low-noise variable gain amplifier (LNVGA) in which the IIP2 is very high, and the gain control is applied to improve the system dynamic range, even with the limitations of the CMOS technology. Two stages compose the LNVGA, a low-noise amplifier, that keeps the noise figure (NF) at low values, and a variable voltage attenuator (VVA), that provides the gain variation. We have applied on the VVA the phase cancellation technique, in which the addition of two out-of-phase signals controls the gain. This technique provides a large gain tuning range only if the paths of the two signalsto be added are well balanced; hence, a precise 180 degrees phase difference is required. In this desing we propose an active balun with small imbalance, which creates those signals. The LNVGA was implemented in 130 nm CMOS with a 1.2 V supply. The measurement results show a 35 dB gain tuning range, varying from 10 to ? 25 dB, a 4.9 dB minimum NF, a ? 10 dBm IIP3, and an IIP2 as high as + 40 dBm.     

A 90–96 GHz CMOS down-conversion mixer with high conversion gain and excellent LO–RF isolation

A 90–96 GHz down-conversion mixer for 94 GHz image radar sensors using standard 90 nm CMOS technology is reported. RF negative resistance compensation technique, i.e. NMOS LC-oscillator-based RF transconductance (GM) stage load, is used to increase the output impedance and suppress the feedback capacitance C_gd of RF GM stage. Hence, conversion gain (CG), noise figure (NF) and LO–RF isolation of the mixer can be enhanced. The mixer consumes 15 mW and achieves excellent RF-port input reflection coefficient of ?10 to ?36.4 dB for frequencies of 85–105 GHz. The corresponding -10 dB input matching bandwidth is 20 GHz. In addition, for frequencies of 90–96 GHz, the mixer achieves CG of 6.3–9 dB (the corresponding 3-dB CG bandwidth is greater than 6 GHz) and LO–RF isolation of 40–45.1 dB, one of the best CG and LO–RF isolation results ever reported for a down-conversion mixer with operation frequency around 94 GHz. Furthermore, the mixer achieves an excellent input third-order intercept point of 1 dBm at 94 GHz. These results demonstrate the proposed down-conversion mixer architecture is very promising for 94 GHz image radar sensors.     

Design of 50–70 GHz Planar Wideband Bandpass Filter on Liquid Crystal Polymer Substrate

In this paper, the authors propose a novel and compact 50-70 GHz planar microstrip bandpass filter, possessing sharp-rejection, low insertion-loss and wide-band characteristics, based on Liquid Crystal Polymer (LCP) substrates. The filter is fabricated on LCP substrates by using standard processing technologies. The proposed filter exhibits a return loss level better than 10 dB, an insertion loss of 5 dB and a 3-dB bandwidth of 30%.The measured and simulated results show good agreement, proving that LCPs are potential and very promising materials for flexible millimeter-wave substrate applications.     

Synthesized Parameters of MIG for 200 kW, 42 GHz Gyrotron

In this paper, a synthesized design of the magnetron injection gun (MIG) for a 200 kW, 42 GHz gyrotron is presented. The synthesis steps involve the selection of the type of the MIG, the development of the design criteria, the selection of initial design parameters and the development of a program for the estimation of the synthesized parameters for the MIG design. The presented approach estimates the cathode, the beam and the anode parameters, enabling one to build a synthesis model of a complete MIG system.