含ROM和RAM芯片的数字电路板测试生成

针对数字电路板中含ROM和RAM芯片电路板故障诊断难的现状，采用器件等效模型方法和改进的组合时序电路测试乍成算法，研制开发了一套支持ROM／RAM器件测试生成、集电路模型输入、测试生成算法、敝障仿真及IEEE-1415标准测试数据转换功能于一体的数字电路板故障诊断测试数据自动生成系统，应用结果表明，该系统测试生成效率高、故障诊断精度高．具有一定的实州性和推广价值。     

基于K近邻的数字电路自动测试向量生成方法

基于分支限界搜索的自动测试向量生成(ATPG)是数字电路测试中的关键技术,搜索中的回溯次数对ATPG性能造成很大影响.为了减少ATPG回溯次数,提出一种基于K近邻(KNN)的数字电路ATPG方法.将机器学习中的KNN算法引入POEDM测试生成算法, KNN结合电路结构数据和可测试性度量信息来指导PODEM算法中回退路径的选择,替代传统的启发式策略,以尽快地到达有效决策点,减少回溯次数.在ISCAS85,ISCAS89和ITC99基准电路上进行验证,与传统启发式策略以及一种基于人工神经网络(ANN)的回退路径选择策略相比,所提方法在回溯次数、回退次数、运行时间和故障覆盖率指标方面分别实现了最高1 625.0%, 466.0%, 260.0%和2.2%的改进.同时,相比基于ANN的方法, KNN没有显式的训练过程,在搭建模型阶段能够节省一定的显存资源开销,并且可以使用更少的训练集样本得到有效的预测模型.     

测试访问口在DSP系统硬件设计中的应用

阐述了一种利用测试访问口开发的DSP系统的硬件设计方法.在这种硬件设计中,程序存储器配置为RAM,数据存储器留有一定的空间配置为慢速的ROM,系统程序存放在此ROM中.利用测试访问口设计了一个电路和一段程序,可以把程序从数据存储器的ROM调入程序存储器的RAM中.实践证明,这种硬件设计为系统在线调试提供了非常便利的环境,并且硬件成本很低.     

基于蚂蚁路径的时序电路故障诊断算法

提出了一种VLSI时序电路自动测试型生成(Automatic test pattern generation，ATPG)的新算法。传统ATPG算法采用局部状态转换图或收集门级电路的知识以及提取电路规则来解决时序电路ATPG的困难。本算法引入新的模型，着重解决了ATPG中的计算冗余问题。在蚂蚁路径模型的基础上，前向搜索得到了重建，故障点的前向传输和回溯归结到了单一路径之上．而该路径上可能分布着许多待测的故障点，从而改善了以往时序电路ATPG算法中搜索重复而导致的计算冗余问题，同时，最小测试向量的获取为数学定理所证明。最后在Benchmark电路上进行的与ILP算法的比较试验表明，本算法具备同样的故障覆盖率，且速度更快。     

ASIC集成电路的可测性设计与技术实现

ASIC集成电路设计开发中的隐含逻辑瑕疵与电路故障是芯片实现的最大困境,针对不同特性的电路提出了内部逻辑扫描、存储器内建自测试、边界扫描链插入以及ATPG自动测试向量生成的解决方案与技术方法,实现了SOC设计开发中逻辑与成片电路的主动侦测与跟踪寻径,经实践证明这些方法大大提高了复杂SOC研制的成功率.     

一个适于形式验证的ATPG引擎

自动测试产生(ATPG)不仅应用于芯片测试向量生成，也是芯片设计验证的重要引擎之一．提出了一种组合电路测试产生的代数方法，既可作为组合验证的ATPG引擎，又可用于通常的测试产生．该算法充分发挥了二叉判决图(BDD)及布尔可满足性(SAT)的优势，通过启发式策略实现SAT算法与BDD算法的交替，防止因构造BDD可能导致的内存爆炸，而且使用增量的可满足性算法，进一步提高了算法的效率．实验结果表明了该算法的可行性和有效性．     

快马加鞭话内存

什么是内存内存是一组或多组具备数据输入输出和数据存储功能的集成电路。按存储信息的功能可把内存分为只读存储器ROM（ReadonlyMemory）和随机存储器RAM（Ran－domAccessMemory）。ROM顾名思义它所存的信息只能被读出，而不能被修改和删除，故只用于存放固定程序（如监控程序、汇编程序等）。而RAM就是我们所说的内存，它主要用来存放各种数据、中间结果，以及与外部存储器交换信息。由于RAM由电子器件组成，所以只能用暂时存放程序和数据，如果一旦关闭电源，其中的数据就会丢失。现在的RAM多为mos型半导体电路，分为静态和动…     

一种存储器板的测试生成技术研究与实现

为了达到较高的故障覆盖率,研究了一种可把存储器板故障定位到器件级的测试生成方法;该方法首先从功能上对电路从控制总线、数据总线、地址总线以及RAM组进行分块,再结合路径敏化法使测试接近实际工作状况激活故障点的方式编写测试激励,最后通过数字仿真软件——LASAR仿真软件生成可加载到众多测试系统上的符合国际标准数字测试交换格式DTIF(IEEE 1445)的标准测试数据;仿真结果表明,该方法操作简单、有效,故障覆盖率达到了90%,是一种很可行的存储器板测试生成方法。     

基于边界扫描的单片机系统RAM芯片测试研究

存储器具有存储容量大、集成度高以及工作速度快等特点,被广泛应用于现代电路设计中;在电路中,存储器能否正常工作,将直接影响整个系统工作状态是否稳定;为了提高系统的可靠性,对存储器进行可靠性测试是十分必要的;在介绍了存储器电路结构和故障的基础上,对某含有RAM存储器的CPU板进行了基于边界扫描的BIT测试性设计和改造,并对系统中的RAM芯片进行了测试性验证;实验结果表明,改造后的电路系统能够实现RAM自测试功能,且故障定位准确,达到了预期的设计目的,可有效提高系统的可靠性。     

基于扫描森林结构的种子编码方案

扫描森林是一种有效的扫描结构，它能够大幅度地降低测试应用开销、测试功耗以及测试数据容量。该文针对采用扫描森林结构的待测电路提出了一种新的种子编码方案。在该方案中，伪随机测试向量覆盖电路中的易测故障，使用ATPG对剩余故障生成确定性测试向量，将其中某一测试向量对应的种子编码为LFSR扩展成该向量需要运行的时钟周期数。实验结果表明，提出的方案能大幅度地降低种子存储数据量，最大降幅达到了83.3％。     

Why RTL ATPG?

Register Transfer Level(RTL)Automatic Test Pattern Generation(ATPG) has been of wide conceran for two decades .Meanwhile gate-level ATPG has made remarkable progress in dealing with large circuits.An argument is then posed.Do we need RTL ATPG in the case of gate-level ATPG capable of generating tests for large circuits? This paper attempts to answer this question .The necessity,difficulty,and major interests of RTL ATPG are reviewed.     

无人机控制系统RAM芯片测试方法研究

RAM芯片在飞控系统中经常使用,在整个系统中起着数据存储和通讯的重要作用,针对某型无人机控制系统可靠性设计的要求,研究其应用RAM芯片在使用前的测试方法,以保证硬件系统的可靠性,减小调试过程中故障出现的概率;详细分析了RAM芯片故障类型,针对不同故障提供了相应的检测和定位方法,最后提出了针对无人机控制系统应用RAM芯片的综合测试方法,并通过大量的实验和使用证明,此种方法能够很好地对RAM进行全面测试,较准确地定位RAM故障。     

Advanced CMOS speech synthesizers

Employing an updated C²MOS (clocked CMOS) technique, two types of speech synthesizer LSI circuits, based on the Parcor (partial correlation) and the ADM (adoptive delta modulation) methods, and recording watch system, are introduced and described.

These LSI circuits and system have several functions

• • The new Parcor LSI circuit has the circuits needed by the Parcor synthesis algorithm. It has a 64 kbit speech data ROM, output low pass filter and preamplifier. Using only this LSI circuit, 30 s to 60 s of speech can be synthesized.

• • The new ADM LSI circuit has encoding and decoding circuits, a 64 kbit speech data ROM and RAM control circuit. The record and synthesis system can be easily constructed with this LSI circuit and RAM.

• • The recording watch system consists of the watch LSI circuit with the ADM system and the analogue LSI circuit.

In the Parcor system, various high quality and low data-rate speech outputs are obtainable. The ADM system is applied for recording and synthesizing. By applying these systems to meet market needs, it is possible to achieve good cost performance in a simple system.     

Simulation of ATPG Neural Network and Its Experimental Results

This paper first establishes a neural network model for logic circuits from the truth tableby using linear equations theory,presents a kind of ATPG neural network model,and investigates energy local minima for the network.And then,it proposes the corresponding techniques to reduce the number of energy local minima as well as some approaches to escaping from local minimum of energy.Finally,two simulation systems,the binary ATPG neural network and the continuous ATPG neural network,are implemented on SUN 3/260 workstation in C language.The experimental results and their analysis and discussion are given.The preliminary experimental results show that this method is feasible and promising.     

IDDQ test and diagnosis of CMOS circuits

Designers must target realistic faults if they desire high-quality test and diagnosis of CMOS circuits. The authors propose a strategy for generating high-quality I_DDQ test patterns for bridging faults. They use a standard ATPG tool for stuck-at faults that adapts to target bridging faults via I_DDQ testing. The authors discuss I_DDQ test set diagnosis capability and specifically generated vectors that can improve diagnosability, and provide test and diagnosis results for benchmark circuits     

蚁群优化在组合电路测试生成中的应用

如何高效地解决数字电路测试生成问题是VLSI领域中的核心。通过对蚁群算法在不同类型的组合优化和搜索问题上的应用研究,基于组合电路测试的路径敏化方法,借助SAT确定性算法工具,提出了一个新的蚁群算法模型来解决组合电路测试生成问题,并通过实验验证其可行性。     

A test-pattern-generation algorithm for sequential circuits

A deterministic test-pattern-generation algorithm for synchronous sequential circuits is presented. The algorithm, called Essential, takes advantage of a procedure for learning global implications. It uses static and dynamic dominance relationships among signals, the concept of the potential propagation path, and intelligent heuristics to guide and accelerate the decision-making process for deterministic automatic test pattern generation (ATPG). Essential is based on the well-known method of reverse time processing, but it applies forward processing within time frames to avoid disadvantageous a priori determination of a path to be sensitized or of a primary output to which the fault effects must be propagated. It is designed to exploit fully the sophisticated techniques used for combinational circuits in the Socrates ATPG system. Experimental results for sequential ATPG obtained with Essential (implemented in C on a Sequent Symmetry computer) are reported     

Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis

Efficient utilization of the inherent parallelism of multi-core architectures is a grand challenge in the field of electronic design automation (EDA). One EDA algorithm associated with a high computational cost is automatic test pattern generation (ATPG). We present the ATPG tool TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully chosen mix of various optimization techniques, multi-million-gate industrial circuits are handled without aborts. TIGUAN supports both conventional single-stuck-at faults and sophisticated conditional multiple stuck-at faults which allows to generate patterns for non-standard fault models. We demonstrate how TIGUAN can be combined with conventional structural ATPG to extract full benefit of the intrinsic strengths of both approaches.