High-mobility ultrathin strained Ge MOSFETs on bulk and SOI with low band-to-band tunneling leakage: experiments

For the first time, the tradeoffs between higher mobility (smaller bandgap) channel and lower band-to-band tunneling (BTBT) leakage have been investigated. In particular, through detailed experiments and simulations, the transport and leakage in ultrathin (UT) strained germanium (Ge) MOSFETs on bulk and silicon-on-insulator (SOI) have been examined. In the case of strained Ge MOSFETs on bulk Si, the resulting optimal structure obtained was a UT low-defect 2-nm fully strained Ge epi channel on relaxed Si, with a 4-nm Si cap layer. The fabricated device shows very high mobility enhancements >3.5/spl times/ over bulk Si devices, 2/spl times/ mobility enhancement and >10/spl times/ BTBT reduction over 4-nm strained Ge, and surface channel 50% strained SiGe devices. Strained SiGe MOSFETs having UT (T/sub Ge/<3 nm) very high Ge fraction (/spl sim/ 80%) channel and Si cap (T/sub Si cap/<3 nm) have also been successfully fabricated on thin relaxed SOI substrates (T/sub SOI/=9 nm). The tradeoffs in obtaining a high-mobility (smaller bandgap) channel with low tunneling leakage on UT-SOI have been investigated in detail. The fabricated device shows very high mobility enhancements of >4/spl times/ over bulk Si devices, >2.5/spl times/ over strained silicon directly on insulator (SSDOI; strained to 20% relaxed SiGe) devices, and >1.5/spl times/ over 60% strained SiGe (on relaxed bulk Si) devices.     

Self-Assembled Germanium Quantum-Dot Supercrystals in Silicon with Extremely Low Thermal Conductivities for Thermoelectrics

Superlattices with one-dimensional (1D) phonon confinement were studied to obtain a low thermal conductivity for thermoelectrics. Since they are composed of materials with a lattice mismatch, they often show dislocations. Like 1D nanowires, they also decrease heat transport in only one main propagation direction. It is therefore challenging to design superlattices with a thermoelectric figure of merit ZT higher than unity. Epitaxial self-assembly is a major technology to fabricate three-dimensional (3D) Ge quantum-dot (QD) arrays in Si. They have been used for quantum and solar-energy devices. Using the atomic-scale phononic crystal model, 3D Ge QD supercrystals in Si also present an extreme reduction of the thermal conductivity to a value that can be under 0.04 W/m/K. Owing to incoherent phonon scattering, the same conclusion holds for 3D supercrystals with moderate QD disordering. As a result, they might be considered for the design of highly efficient complementary metal–oxide–semiconductor (CMOS)-compatible thermoelectric devices with ZT possibly much higher than unity. Such a small thermal conductivity was only obtained for two-dimensional layered WSe₂ crystals in an experimental study. However, electronic conduction in the Si/Ge compounds is significantly enhanced. The 0.04 W/m/K value can be computed for different Ge QD filling ratios of the Si/Ge supercrystal with size parameters in the range of current fabrication technologies.     

Comparative analysis of radiation effects on the electroluminescence of Si and SiGe/Si(001) heterostructures with self-assembled Islands

The effect of neutron radiation on the electroluminescence of the Si p-i-n diode containing a multilayered Ge/Si heterostructure with self-assembled nanoislands is studied. In comparison with bulk Si, the diodes containing Ge(Si) nanoislands exhibit a higher radiation hardness of the electroluminescence signal, which is attributed to spatial localization of charge carriers in the Ge/Si nanostructures. The spatial localization of charge carriers impedes their diffusion to radiation defects followed by nonradiative recombination at the defects. The results show the possibilities of using Ge/Si heterostructures with self-assembled nanoislands for the development of optoelectronic devices resistant to radiation.     

Base resistance and effective bandgap reduction in n-p-nSi/Si1-xGex/Si HBTs with heavy base doping

This paper presents a comprehensive study of the effects of heavy doping and germanium in the base on the dc performance of Si/Si_1-x Ge_x/Si npn Heterojunction Bipolar Transistors (HBTs). The lateral drift mobility of holes in heavily doped epitaxial SiGe bases affects the base sheet resistance while the effective bandgap is crucial for the vertical minority carrier transport. The devices used in this study were Si_1-xGe_x npn HBTs with flat Ge and B profiles in the base grown by Rapid Thermal Chemical Vapor Deposition (RTCVD). Hall and drift lateral hole mobilities were measured in a wide range of dopings and Ge concentrations. The drift mobility was indirectly measured based on measured sheet resistivity and SIMS measurements, and no clear Ge dependence was found. The Hall scattering factor is less than unity and decreases with increasing Ge concentration. The effective bandgap narrowing, including doping and Ge effects, was extracted from the room temperature collector current measurements over a wide range of Ge and heavy doping for the first time. We have observed bandgap narrowing due to heavy base doping which is, to first order, independent of Ge concentration, but less than that observed in silicon, due to the effect of a lower density of states. A model for the collector current enhancement with respect to Si devices versus base sheet resistance is presented     

La/sub 2/O/sub 3//Si/sub 0.3/Ge/sub 0.7/ p-MOSFETs with high hole mobility and good device characteristics

We have studied high-k La/sub 2/O/sub 3/ p-MOSFETs on Si/sub 0.3/Ge/sub 0.7/ substrate. Nearly identical gate oxide current, capacitance density, and time-dependent dielectric breakdown (TDDB) are obtained for La/sub 2/O/sub 3//Si and La/sub 2/O/sub 3//Si/sub 0.3/Ge/sub 0.7/ devices, indicating excellent Si/sub 0.3/Ge/sub 0.7/ quality without any side effects. The measured hole mobility in nitrided La/sub 2/O/sub 3//Si p-MOSFETs is 31 cm/sup 2//V-s and comparable with published data in nitrided HfO/sub 2//Si p-MOSFETs. In sharp contrast, a higher mobility of 55 cm/sup 2//V-s is measured in La/sub 2/O/sub 3//Si/sub 0.3/Ge/sub 0.7/ p-MOSFET, an improvement by 1.8 times compared with La/sub 2/O/sub 3//Si control devices. The high mobility in Si/sub 0.3/Ge/sub 0.7/ p-MOSFETs gives another step for integrating high-k gate dielectrics into the VLSI process.     

Hole transport in UTB MOSFETs in strained-Si directly on insulator with strained-Si thickness less than 5 nm

Hole transport is studied in ultrathin body (UTB) MOSFETs in strained-Si directly on insulator (SSDOI) with a Si thickness down to 1.4 nm. In these Ge-free SSDOI substrates, the Si is strained in biaxial tension with strain levels equivalent to strained-Si on relaxed SiGe, with Ge contents of 30 and 40% Ge. The hole mobility in SSDOI decreases slowly for Si thicknesses above 4 nm, but drops rapidly below that thickness. Relative to silicon-on-insulator control devices of equal thickness, SSDOI displays significant hole mobility enhancement for Si film thicknesses above 3.5 nm. Peak hole mobility is improved by 25% for 40% SSDOI relative to 30% SSDOI fabricated by the same method, demonstrating the benefits of strain engineering for 3.1-nm-thick UTB MOSFETs.     

Effect on ion implanted germanium profile on the characteristics of Si/sub 1-x/Ge/sub x//Si heterojunction bipolar transistors

An optimum profile for Ge ion implantation in SiGe/Si heterojunction bipolar transistors is determined by using a two-dimensional simulator code for advanced semiconductor devices. The simulation code is based on a two-dimensional drift-diffusion model for heterostructure degenerate semiconductors with nonparabolicity included in the energy band structure. The model allows accurate simulations of carrier transport in short base devices. The simulation results indicate that for high current gain the Ge profile maximum must be close to the base-collector junction, and that the unavoidable tail of the implanted germanium in the collector region does not deteriorate the gain.<>     

Simulation study of Short-Channel Effects and quantum confinement in double-gate FinFET devices with high-mobility materials

We developed a quantum-mechanical simulation code to study subthreshold performances and carrier quantum confinement in double-gate MOSFETs with high-mobility channel materials like Ge and III-V semiconductors. The code is based on the two-dimensional and self-consistent numerical solving of Poisson and Schrödinger equations coupled with the drift-diffusion transport equation. We systematically evaluate and analyze drain-induced barrier lowering and carrier quantum confinement in Si, Ge, In_0.53Ga_0.47As and GaAs based double-gate devices. Results show that SCEs in In_0.53Ga_0.47As and GaAs devices are lower than in Si and Ge counterparts. However, when the channel film thickness is reduced, carrier confinement is found to strongly impact double-gate device operation with high-mobility materials owing to their low confinement effective mass in the lowest energy valley.     

Research progress of Si-based germanium materials and devices

Si-based germanium is considered to be a promising platform for the integration of electronic and photonic devices due to its high carrier mobility, good optical properties, and compatibility with Si CMOS technology. However, some great challenges have to be confronted, such as: (1) the nature of indirect band gap of Ge; (2) the epitaxy of dislocation-free Ge layers on Si substrate; and (3) the immature technology for Ge devices. The aim of this paper is to give a review of the recent progress made in the field of epitaxy and optical properties of Ge heterostructures on Si substrate, as well as some key technologies on Ge devices. High crystal quality Ge epilayers, as well as Ge/SiGe multiple quantum wells with high Ge content, were successfully grown on Si substrate with a low-temperature Ge buffer layer. A local Ge condensation technique was proposed to prepare germanium-on-insulator (GOI) materials with high tensile strain for enhanced Ge direct band photoluminescence. The advances in formation of Ge n⁺p shallow junctions and the modulation of Schottky barrier height of metal/Ge contacts were a significant progress in Ge technology. Finally, the progress of Si-based Ge light emitters, photodetectors, and MOSFETs was briefly introduced. These results show that Si-based Ge heterostructure materials are promising for use in the next-generation of integrated circuits and optoelectronic circuits.     

Electrical characterization of germanium p-channel MOSFETs

In this letter, we report germanium (Ge) p-channel MOSFETs with a thin gate stack of Ge oxynitride and low-temperature oxide (LTO) on bulk Ge substrate without a silicon (Si) cap layer. The fabricated devices show 2 /spl times/ higher transconductance and /spl sim/ 40% hole mobility enhancement over the Si control with a thermal SiO/sub 2/ gate dielectric, as well as the excellent subthreshold characteristics. For the first time, we demonstrate Ge MOSFETs with less than 100-mV/dec subthreshold slope.     

Study of single- and dual-channel designs for high-performance strained-Si-SiGe n-MOSFETs

Results comparing strained-Si-SiGe n-channel MOSFET performance of single-and dual-surface channel devices fabricated using 15% Ge content SiGe virtual substrates are presented. Device fabrication used high thermal budget processes and virtual substrates were not polished. Mobility enhancement factors exceeding 1.6 are demonstrated for both single-and dual-channel device architectures compared with bulk-Si control devices. Single-channel devices exhibit improved gate oxide quality, and larger mobility enhancements, at higher vertical effective fields compared with the dual-channel strain-compensated devices. The compromised performance enhancements of the dual-channel devices are attributed to greater interface roughness and increased Ge diffusion resulting from the Si/sub 0.7/Ge/sub 0.3/ buried channel layer.     

Characteristics of Self-Aligned Gate-First Ge p- and n-Channel MOSFETs Using CVD HfO2 Gate Dielectric and Si Surface Passivation

The electrical properties of p- and n-MOS devices fabricated on germanium with metal-organic chemical-vapor-deposition HfO₂ as gate dielectric and silicon passivation (SP) as surface treatment are extensively investigated. Surface treatment prior to high-K deposition is critical to achieve small gate leakage currents as well as small equivalent oxide thicknesses. The SP provides improved interface quality compared to the treatment of surface nitridation, particularly for the gate stacks on p-type substrate. Both Ge p- and n-MOSFETs with HfO₂ gate dielectrics are demonstrated with SP. The measured hole mobility is 82% higher than that of the universal SiO₂/Si system at high electric field (~0.6 MV/cm), and about 61% improvement in peak electron mobility of Ge n-channel MOSFET over the CVD HfO₂ /Si system was achieved. Finally, bias temperature-instability (BTI) degradation of Ge MOSFETs is characterized in comparison with the silicon control devices. Less negative BTI degradation is observed in the Ge SP p-MOSFET than the silicon control devices due to the larger valence-band offset, while larger positive BTI degradation in the Ge SP n-MOSFET than the silicon control is characterized probably due to the low-processing temperature during the device fabrication     

Interaction of self-assembled Ge islands and adjacent Si layers grown on unpatterned and patterned Si(001) substrates

For use in electronic devices, self-assembled Ge islands formed on Si(001) must be covered with an additional Si layer. Chemically vapor deposited Si layers initially grow very rapidly over Ge islands because of the catalytic effect of Ge on the reaction of the Si-containing gas. The edges of the Si features covering Ge “pyramids” are rotated by 45° with respect to the edges of the Ge pyramids because of the different mechanisms orienting the Ge islands and the Si features. When multiple layers of islands are formed, the in-plane ordering of the Ge islands depends on the thickness of the Si interlayer separating the island layers. When selective Si is grown on a patterned Si wafer to form the underlying structure for the Ge islands, the position of the islands is influenced by the detailed shape of the Si near the edges, which in turn depends on the thickness of the selectively deposited Si, the pattern size, and the amount of surrounding oxide.     

锗纳米线的性能与应用

重点分析讨论了锗纳米线在电学、光学、光电导等特性及其在场效应晶体管制造方面的研究应用现状与最新进展。综合分析表明,未经处理的锗纳米线表面存在一层氧化物及缺陷,与电极连接时欧姆接触性能较差,在制备锗纳米线器件以前必须对锗纳米线表面进行钝化以便沉积电极;对锗纳米线进行掺杂可以改善Ge纳米线的性能,制造出实用Ge纳米线器件。指出在一根纳米线上生长硅/锗半导体纳米线形成硅/锗半导体界面,直接用单根纳米线制造具有完整功能的电子器件是将来重要的研究方向。     

Electron mobility enhancement using ultrathin pure Ge on Si substrate

We demonstrate enhancement of electron mobility in nMOSFET using an ultrathin pure Ge crystal channel layer directly grown on a bulk Si wafer. A thin Si crystal layer is also grown on top of a Ge crystal channel layer as a capping layer. Using the Si/Ge/Si structure, a maximum 2.2X enhancement in electron mobility is achieved while good gate dielectric properties and junction qualities of bulk Si devices are maintained.     

Si基外延Ge薄膜及退火对其特性的影响研究

采用超高真空化学气相沉积(UHV-CVD)系统,用低温Ge缓冲层技术在Si衬底上外延了张应变Ge薄膜.扫描电镜(TEM)图表明Si基外延Ge薄膜拥有低的位错密度,原子力显微镜(AFM)测试Ge层表面粗糙度仅为1.2 nm.对Si基外延Ge薄膜进行了不同温度下的退火,并用双晶X射线衍射(DCXRD)曲线和Raman谱进行...     

Electrical properties of GeSi surface- and buried-channel p-MOSFETsfabricated by Ge implantation

The electrical properties of surface- and buried-channel p-MOSFETs containing strained GeSi heterostructures synthesized by high-dose Ge implantation and solid phase epitaxial growth have been investigated. Compared with Si control devices on the same chips, GeSi transistors exhibited improved performance: the channel hole mobility and linear transconductance was up to 18% higher for surface-channel GeSi transistors, and up to 12% higher for buried-channel GeSi p-MOSFETs, than for equivalent Si devices. Ion-beam synthesis of GeSi strained layers therefore offers an attractive means for realising improved device performance in conventional Si device structures     

Ge outdiffusion effect on flicker noise in strained-Si nMOSFETs

The flicker noise characteristics of strained-Si nMOSFETs are significantly dependent on the gate oxide formation. At high temperature (900/spl deg/C) thermal oxidation, the Si interstitials at the Si/oxide interface were injected into the underneath Si-SiGe heterojunction, and enhanced the Ge outdiffusion into the Si/oxide interface. The Ge atoms at Si/oxide interface act as trap centers, and the strained-Si nMOSFET with thermal gate oxide yields a much larger flicker noise than the control Si device. The Ge outdiffusion is suppressed for the device with the low temperature (700/spl deg/C) tetraethylorthosilicate gate oxide. The capacitance-voltage measurements of the strained-Si devices with thermal oxide also show that the Si/oxide interface trap density increases and the Si-SiGe heterojunction is smeared out due to the Ge outdiffusion.     

Improvement in NBTI reliability of Si-passivated Ge/high-k/metal-gate pFETs

State-of-the-art germanium-based p-channel FET devices are shown to have normal Negative Bias Temperature Instability (NBTI) behavior typically observed in Silicon-based pFETs. Furthermore, NBTI in Ge pFETs is reduced with respect to their Si counterparts. This improvement quantitatively corresponds to the reduction due to the tunneling barrier for holes formed by the Si passivation layer. A strong reduction in the permanent NBTI component is ascribed to a higher initial number of interface states.     

Research and Design of Ge0.6Si0.4／Si Strained—layer Superlattice Planar Optical Waveguide

Calculation shows that the refraction index of Ge0.6Si0.4/Si strained-layer superlattice n≈3.64,when Lw=9 nm and Lb=24 nm.An algorithm of numerical iteration for effective refraction index is emploted to obtain different effective refraction indexes at different thickness(L) .As a result, the thickness of Ge0.6Si0.4/Si strained-layer superlattice optical waveguide,L≤363 nm, can be determlned, which is very important for designing waveguide devices.An optical waveguidecan be madeinto a nanometer device by using Ge0.6Si0.4/Si strained-layer superlattice.