共查询到20条相似文献,搜索用时 15 毫秒
1.
Lin W.H. Pey K.L. Dong Z. Chooi S.Y.M. Ang C.H. Zheng J.Z. 《Electron Device Letters, IEEE》2003,24(5):336-338
Soft breakdown in ultrathin gate oxide has been studied using constant voltage stressing. The behavior of current increments resulting from a number of soft breakdown events has been characterized by statistical distribution. It is shown that the distribution of the current increment follows Weibull distribution rather than log normal distribution. The newly established Weibull slope is shown to be independent of the stressed voltage in the range investigated between 4.5 and 5.1 V. The temperature effect study shows that the Weibull slope reduces with increasing testing temperature. Furthermore, a strong dependence of the Weibull slope on the oxide thickness has been found. These observations can be explained well by geometrical configurations of the percolation path. 相似文献
2.
Time dependent breakdown of ultrathin gate oxide 总被引:3,自引:0,他引:3
Yassine A.M. Nariman H.E. McBride M. Uzer M. Olasupo K.R. 《Electron Devices, IEEE Transactions on》2000,47(7):1416-1420
Time dependent dielectric breakdown (TDDB) of ultrathin gate oxide (<40 Å) was measured for a wide range of oxide fields (3.4<|Eox|<10.3 MV/cm) at various temperatures (100⩽T⩽342°C). It was found that TDDB of ultrathin oxide follows the E model. It was also found that TDDB t50 starts deviating from the 1/E model for fields below 7.2 MV/cm. Below 4.8 MV/cm, TDDB t50 of intrinsic oxide increased above the value predicted by the E model obtained for fields >4.8 MV/cm. The TDDB activation energy for this type of gate oxide was found to have linear dependence on oxide field. In addition, we found that γ (the field acceleration parameter) decreases with increasing temperature. Furthermore, it was found that testing at high temperatures (up to 342°C) and low electric field values did not introduce new gate oxide failure mechanism. It is also shown that TDDB data obtained at very high temperature (342°C) and low fields can be used to generate TDDB model at lower temperatures and low fields. Our results (an enthalpy of activation of 1.98 eV and dipole moment of 12.3 eÅ) are in complete agreement with previous results by McPherson and Mogul. Additionally, it was found that TDDB is exponentially dependent on the gate voltage 相似文献
3.
In this work, a quantitative analysis is applied to resolve the newly reported polarity-dependent charge-to-breakdown (Q/sub BD/) data from thick oxides of 6.8 nm down to ultrathin oxides of 1.9 nm. Three independent sets of Q/sub BD/ data, i.e., n/sup +/poly/NFET stressed under inversion and accumulation, and p/sup +/ poly/PFET under accumulation are carefully investigated. The Q/sub BD/ degradation observed for p-type anodes, either poly-Si or Si-substrate, can be nicely understood with the framework of maximum energy released by injected electrons. Thus, this work provides a universal and quantitative account for a variety of experimental observations in the time-to-breakdown (T/sub BD/) and Q/sub BD/ polarity-dependence of oxide breakdown. 相似文献
4.
Jonghwan Lee Bosman G. Green K.R. Ladwig D. 《Electron Devices, IEEE Transactions on》2002,49(7):1232-1241
An analytical model of the gate leakage current in ultrathin gate nitrided oxide MOSFETs is presented. This model is based on an inelastic trap-assisted tunneling (ITAT) mechanism combined with a semi-empirical gate leakage current formulation. The tunneling-in and tunneling-out current are calculated by modifying the expression of the direct tunneling current model of BSIM. For a microscopic interpretation of the ITAT process, resonant tunneling (RT) through the oxide barrier containing potential wells associated with the localized states is proposed. We employ a quantum-mechanical model to treat electronic transitions within the trap potential well. The ITAT current model is then quantitatively consistent with the summation of the resonant tunneling current components of resonant energy levels. The 1/f noise observed in the gate leakage current implies the existence of slow processes with long relaxation times in the oxide barrier. In order to verify the proposed ITAT current model, an accurate method for determining the device parameters is necessary. The oxide thickness and the interface trap density of the gate oxide in the 20-30 Å thickness range are evaluated by the quasi-static capacitance-voltage (C-V) method, dealing especially with quantum-mechanical and polysilicon effects 相似文献
5.
The results of an investigation of time-dependent breakdown (TDDB) of intrinsic ultrathin gate oxide are presented for a wide range of oxide fields 4.6ox<10.4 MV/cm at elevated temperatures. It was found that TDDB of ultrathin oxide follows the E model down to 4.6 MV/cm. The data show that TDDB t50 starts deviating from the 1/E model for fields below 7.2 MV/cm. The data also show that the TDDB activation energy for this type of gate oxide is linearly dependent on oxide field. In addition, we show that the field acceleration parameter γ decreases as temperature increases 相似文献
6.
7.
Wei Yip Loh Byung Jin Cho Ming Fu Li Chan D.S.H. Chew Hoe Ang Jia Zhen Zheng Dim Lee Kwong 《Electron Devices, IEEE Transactions on》2003,50(4):967-972
Conventional oxide reliability studies determine oxide lifetime by measuring the time to breakdown or quasi-breakdown (QB). In ultrathin gate oxides with T/sub ox/<14 /spl Aring/, however, it is hard to observe breakdown or QB under typical stress conditions. Instead, the gate leakage current shows a continuous increase over the entire time period of electrical stress. As the magnitude of the gate current density increase eventually becomes too high to be acceptable for normal device operation, a lifetime criterion based on the increase in gate leakage current is proposed. Our paper also shows that the area-dependence of the gate leakage current density increase in 13.4 /spl Aring/ oxides is different from that in thicker oxide films, indicating a localized and discrete property of the leakage current. It has also been observed that the oxide lifetime based on the new lifetime criterion is shorter when the gate area is smaller, as opposed to the conventional area dependence of time-to-breakdown test. A simple model consisting of multiple degraded spots is proposed and it has been shown that localized gate leakage current can be described by Weibull's statistics for multiple degraded spots. 相似文献
8.
Tien-Chun Yang Sachdev P. Saraswat K.C. 《Electron Devices, IEEE Transactions on》1999,46(7):1457-1463
In this work, we demonstrate that the reliability of ultrathin (<10 nm) gate oxide in MOS devices depends on the Fermi level position at the gate, and not on its position at the substrate for constant current gate injection (υg-). The oxide breakdown strength (Qbd) is less for p+ poly-Si gate than for n+ poly-Si gate, but, it is independent of the substrate doping type. The degradation of an oxide is closely related to the electric field across it, which is influenced by the cathode Fermi level for constant current injection. P+ poly-Si gate has higher barrier height for tunneled electrons, therefore, the cathode electric field is higher to give the same injection current density. A higher electric field gives more high-energy electrons at the anode, and therefore the damage is more at the substrate interface. We have also shown that oxide degradation is independent of the testing methodology, i.e., constant current or constant voltage stress. It depends mainly on the electric field in the oxide 相似文献
9.
Semiconductor thickness and back-gate voltage effects on the gate tunnel current in the MOS/SOI system with an ultrathin oxide 总被引:1,自引:0,他引:1
The effects of the semiconductor layer thickness and the back-gate voltage on the current-voltage (I-V) characteristics of the MOS/SOI tunnel diode with an aluminum gate and n-type semiconductor layers are theoretically investigated. If the semiconductor thickness is reduced or the back-gate voltage is more negative, the total thermal generation current decreases and the gate-oxide thickness critical for transition from the quasiequilibrium strong inversion state to the nonequilibrium state increases. If the MOS/SOI tunnel diode is in the transition range between the nonequilibrium and quasiequilibrium states, a positive increase of the back-gate voltage V/sub BG/ results in a strong increase of the majority carrier tunnel current. This back-gate effect may be exploited in more functional devices based on the MOS/SOI tunnel diode. 相似文献
10.
In this paper, the influence of poly-Si-gate impurity concentration, N/sub poly/, on inversion-layer electron mobility is experimentally investigated in MOSFETs with ultrathin gate oxide layer. The split capacitance-voltage C-V method is modified to directly measure an effective mobility, paying attention to both 1) accurate current-voltage I-V and capacitance-voltage (C-V) measurements with high gate leakage current and 2) correct surface carrier density, N/sub s/, estimation at a finite drain bias. It is demonstrated that the mobility in ultrathin gate oxides becomes low significantly for highly doped gate, strongly suggesting the contribution of remote Coulomb scattering due to the gate impurities, which is quantitatively discriminated from that of Coulomb scattering due to substrate impurities and interface states. It is also found that the mobility lowering becomes significant rapidly at T/sub ox/ of 1.5 nm or less. The mobility-lowering component is weakly dependent on N/sub s/, irrespective of N/sub poly/, which cannot be fully explained by the existing theoretical models of remote impurity scattering. 相似文献
11.
Noise model of gate-leakage current in ultrathin oxide MOSFETs 总被引:2,自引:0,他引:2
A physics-based analytical model of the gate-leakage current noise in ultrathin gate oxide MOSFETs is presented. The noise model is based on an inelastic trap-assisted tunneling transport. We employ the barrier height fluctuation model and the Lorentzian-modulated shot noise of the gate-leakage current stemming from the two-dimensional electron gas channel to explain the excess noise behavior. The excess noise can be interpreted as the sum of 1/f/sup /spl gamma// noise and the Lorentzian-modulated shot noise. Trap-related processes are the most likely cause of excess current noise because slow traps in the oxide can result in low-frequency dissipation in the conductance of oxides and fast traps can produce the Lorentzian-modulated shot noise associated with generation-recombination process at higher frequencies. In order to verify the proposed noise model, the simulation results are compared with experimental data, and excellent agreement is observed. 相似文献
12.
Ghibaudo G. Bruyere S. Devoivre T. DeSalvo B. Vincent E. 《Semiconductor Manufacturing, IEEE Transactions on》2000,13(2):152-158
An improved method for the assessment of the oxide thickness applicable to advanced CMOS technologies is proposed. To this end, a proper combination of Maserjian's technique and of Vincent's method is used to alleviate the unknown parameter inherent to both extraction procedures and which depends on the employed carrier statistics. The new method has been successfully applied to various technologies with gate oxide thickness ranging from 7 nm to 1.8 nm 相似文献
13.
Chein-Hao Chen Yean-Kuen Fang Chih-Wei Yang Shyh-Fann Ting Yong-Shiuan Tsair Ming-Fang Wang Tuo-Hong Hou Mo-Chiun Yu Shih-Chang Chen Jang S.M. Yu D.C.H. Mong-Song Liang 《Electron Devices, IEEE Transactions on》2001,48(12):2769-2776
The electrical properties affected by the bottom oxide materials and the post-deposition treatment on the ultrathin (down to 1.6 nm) nitride/oxide (N/O) stacks, prepared by rapid thermal chemical vapor deposition (RTCVD) with two-step NH3/N2O post-deposition annealing, for deep submicrometer dual-gate MOSFETs have been studied extensively. N/O stack with NO-grown bottom oxide exhibits fewer flat-band voltage shifts and higher hole and electron mobility, but suffers from worse leakage current than that with conventional O2-grown bottom oxide. In post-deposition treatment, increasing NH3 nitridation temperature can effectively reduce the equivalent oxide thickness (EOT) and improve leakage current reduction rate, but can result in worse mobility. Furthermore, the subsequent N2O annealing eliminates the defects and offers a contrary effect on the N/O stack in comparison with the NH3 nitridation step 相似文献
14.
Scaling rules for sub-micrometric MOS devices have led to the necessity of ultrathin dielectric films and high-k dielectric layers. In this paper we present first results of room temperature plasma oxidation to obtain ultrathin layers of SiO2 and TiO2. The oxidation process in O2 and N2O shows a power law dependence with time and inverse proportionality with pressure. The oxidation rate is inversely proportional to pressure for both high and medium resistivities substrates. An oxidation model is proposed to explain this behavior. Ellipsometric and C–V characterization show complete oxidation of titanium verifying that a dielectric layer is formed. 相似文献
15.
The correlation between gate and substrate currents in NMOSFET's with effective channel length, Leff, down to 0.1 μm is investigated within the general framework of the lucky-electron model. It Is found that the correlation coefficient, Φb/Φi, decreases with decreasing Leff in the 0.1 μm regime, where Φb is the effective Si-SiO2 barrier height for channel hot-electrons, and Φi is the effective threshold potential for impact ionization. Furthermore, this effect becomes stronger in NMOSFET's with shorter Leff. These experimental results suggest the need for further investigation on specific assumptions in the lucky-electron model to understand hot-electron behavior and impact ionization-mechanisms in 0.1 μm-scale NMOSFET's 相似文献
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17.
Nara A. Yasuda N. Satake H. Toriumi A. 《Semiconductor Manufacturing, IEEE Transactions on》2002,15(2):209-213
Reliable techniques for extracting the gate dielectric layer thickness from capacitance-voltage (C-V) characteristics are essential for manufacturing process quality control. Continued reduction of the dielectric layer thickness has brought about a need for new measurement procedures which can account for the direct tunneling currents through the gate insulator. We present a guideline for performing two-frequency C-V analysis of sub-2 nm gate oxides and show that it is possible to extract the dielectric layer thickness with an error of less than 4%. We show that in order to achieve this level of accuracy, it is necessary to choose the measurement frequencies and the test device size so that the dissipation remains below 1.1 at least at one of the two measurement frequencies 相似文献
18.
S. Bruyre F. Guyader W. De Coster E. Vincent M. Saadeddine N. Revil G. Ghibaudo 《Microelectronics Reliability》2000,40(4-5)
In this study, wet and dry oxidation processes for 3.5 nm ultrathin dielectrics are compared in terms of oxide and device reliability. It is demonstrated that a wet oxidation enables to strongly improve the oxide lifetime. On the contrary, the device reliability has been found to be slightly affected by the process choice. Finally, these results associated with charge pumping and stress induced leakage current measurements indicate that the bulk oxide, more than the Si/SiO2 interface, is affected by the growth process ambience (wet or dry oxidation). 相似文献
19.
For applications in the MOS device fabrication the interface properties of sputtered SiO2 and SiO2-polycrystalline silicon layers on silicon substrates were investigated and improved to a quality which is equivalent to those of thermally grown SiO2 with pyrolytical polycrystalline silicon (polySi). For testing these layers as gate oxide and Si electrodes of MOS transistors the well known Si gate process was varied to include sputter deposition and the optimal deposition, annealing and diffusion parameters were integrated.MOS transistors with sputtered SiO2 and Si gate material layers and for comparison Al gate devices with sputtered SiO2 have been fabricated and their threshold voltage behavior was tested. 相似文献
20.
Gupta A. Peng Fang Song M. Ming-Ren Lin Wollesen D. Chen K. Hu C. 《Electron Device Letters, IEEE》1997,18(12):580-582
We present an efficient and accurate method to characterize the physical thickness of ultrathin gate oxides (down to 25 Å) and the effective polysilicon doping of advanced CMOS devices. The method is based on the model for Fowler-Nordheim (F-N) tunneling current across the gate oxide with correction in gate voltage to account for the polysilicon-gate depletion. By fitting the model to measured data, both the gate oxide thickness and the effective poly doping are unambiguously determined. Unlike the traditional capacitance-voltage (C-V) technique that overestimates thin-oxide thickness and requires large area capacitor, this approach results in true physical thickness and the measurement can be performed on a standard sub-half micron transistor. The method is suitable for oxide thickness monitoring in manufacturing environments 相似文献