Parametric yield optimization of CMOS analogue circuits by quadratic statistical circuit performance models

A major bottleneck in the design and parametric yield optimization of CMOS integrated circuits lies in the high cost of the circuit simulations. One method that significantly reduces the simulation cost is to approximate the circuit performances by fitted quadratic models and then use these computationally inexpensive models to optimize the parametric yield. In this paper quadratic statistical circuit performance models are applied to maximize the parametric yield of CMOS analogue circuits. It is found that quadratic polynomials may not always model the circuit performances well. However, with engineering knowledge applied to identify and reduce the causes of the errors, accurate performance models and yield maximization can be achieved with a reasonably small number of circuit simulations, as illustrated through examples. Distinctions between the present method and previous applications of quadratic modelling to statistical circuit design are made.     

Optimal sizing and design of CMOS analogue amplifier circuits using craziness‐based particle swarm optimization

This paper presents the optimal designs of two analogue complementary metal–oxide–semiconductor (CMOS) amplifier circuits, namely differential amplifier with current mirror load and two‐stage operational amplifier. A modified Particle Swarm Optimization (PSO), called Craziness‐based Particle Swarm Optimization (CRPSO) technique is applied to minimize the total MOS area of the designed circuits. CRPSO is a highly modified version of conventional PSO, which adopts a number of random variables and has a better and faster exploration and exploitation capability in the multidimensional search space. Integration of craziness factor in the fundamental velocity term of PSO not only brings diversity in particles but also pledges convergence close to global best solution. The proposed CRPSO‐based circuit optimization technique is reassured to be free from the intrinsic disadvantages of premature convergence and stagnation, unlike Differential Evolution (DE), Harmony Search (HS), Artificial Bee Colony (ABC) and Particle Swarm Optimization (PSO). The simulation results achieved for the two analogue CMOS amplifier circuits establish the efficacy of the proposed CRPSO‐based approach over those of DE, HS, ABC and PSO in terms of convergence haste, design conditions and design goals. The optimally designed analogue CMOS amplifier circuits occupy the least MOS area and show the best performance parameters like gain and power dissipation, in compared with the other reported literature. Copyright © 2016 John Wiley & Sons, Ltd.     

PastA—the characterization of the inherent fluctuations in the fabrication process for circuit simulation

For worst-case analysis, Monte Carlo analysis, yield optimization and design centring, the variations and correlations of the device model parameters in the electrical circuit simulation are of fundamental significance. This paper describes a method for the complete characterization of the inherent fluctuations in the fabrication process for the simulation in IC design. the emphasis is placed on analogue simulation owing to the complex connections between circuit design and technology and the multitude of devices with correlated parameters; nevertheless, statistical requirements for digital simulation can be fully covered. This characterization works with all technologies whether CMOS, BiCMOS or bipolar. the prerequisites are accurate nominal device model parameters for the circuit simulation and information about fabrication statistics, e.g. process control monitor measurements. A new approach with connection coefficients for the calculation of the correlation coefficients is presented. Dependent parameters can be easily defined through a connection hierarchy. With the presented approach the variations and correlations of model parameters for simulation can be generated from estimates or measurements of the fabrication process. Based on sensitivity analysis, the variations and correlations of design objectives can be estimated. This enables the designer to do circuit analysis and optimization (limit parameters, worst-case distances) as well as Monte Carlo analysis.     

Very-high-output-impedance cascode current sources/current mirrors/transresistance stages and their applications

A reconfigurable MOS/BiMOS cascode current source/transresistance stage with very high output impedance is presented in this paper. A cascode active feedback circuit has been employed to achieve such a high output impedance, which approaches the leakage resistance of a reverse-biased junction, assuming that the MOS devices have a large channel length and do not exhibit the short-channel effect. Through small-signal analysis and SPICE simulation it is shown that the proposed current source/transresistance stage provides an output open-circuit Thevinin voltage greater than 10⁸ V. This is an increase of about four orders of magnitude as compared with the conventional cascode current source with the same output voltage range. For scaled technologies this current source/transresistance stage is shown to be ideal for practical high-performance analogue circuit design. We have incorporated the current sources with active feedback in the output stage of a folded cascode op amp and obtained a large DC gain improvement without significantly affecting its high-frequency/transient behaviour.     

输出信号变化率的电压温度自动补偿

数据输出电路在电源电压升高而温度很低的情况下，MOS管工作速度快，会使输出信号变化率过大而产生许多干扰信号。若情况相反，又会使电路性能指标不能达到标准。解决上述问题的方法是自动控制输出电路MOS管的栅极电压变化率。在电路中设置电源电压检测电路，使其输出电压信号反映电源电压的变化，并且用于控制数据输出电路MOS管的栅极电压变化率．在电路中设置温度检测电路，使其输出电压信号反映温度的变化，并且用于控制输出电路MOS管的栅极电压变化率．上述双重控制可以自动补偿数据输出信号变化率的偏移．     

Concurrent analogue fault simulation,the equation formulation aspect

Fault simulation is an essential tool for developing test patterns for circuits. Because the potential number of faults in a circuit is potentially very large, computational efficiency is an important consideration. In the digital domain, concurrent fault simulation is well‐established as an efficient tool. For analogue circuits, fault simulation is often performed by repeated insertion of possible faults and resimulation of the circuit. Consequently, methods for efficient concurrent analogue fault simulation are attracting attention. A review of existing methods of concurrent analogue fault simulation shows that most are based on a similar fundamental perturbation of the original fault‐free circuit equations, although the methods differ in the procedure applied after the circuit equations are formulated. We develop here a comprehensive set of element stamps, describing faulty elements, enabling effective and routine equation formulation for faulty circuits. These may be used no matter what method of fault simulation is later applied. These stamps are used in a new technique for concurrent analogue fault simulation, based on modified nodal analysis. A significant improvement in efficiency, compared with other methods, is demonstrated. Copyright © 2004 John Wiley & Sons, Ltd.     

CMOS current mirror with enhanced input dynamic range

A novel CMOS cascode current mirror configuration with enhanced input dynamic range is presented. The proposed mirror circuit combines the advantages of wide input swing, wide output swing and large output resistance capability, which make it attractive for practical application. Based on 0.18 µm MOS model parameters, HSPICE simulation results show that the input current ranges from 1 µA to 1 mA with large bandwidth for the proposed circuit. The simulation results confirm the theoretical prediction. Copyright © 2009 John Wiley & Sons, Ltd.     

Proposal of a Hamming distance detector using neuron MOS transistors

A neuron MOS transistor has been proposed which operates more “intelligently” than a conventional MOS transistor. In this paper, we propose a Hamming distance detector with a large noise margin using the neuron MOS transistors. The proposed circuit accepts two bitstreams to be compared in parallel, and makes it possible to determine if the two bitstreams are identical (“exact match”) or if the Hamming distance between the two bitstreams is within a certain range (“near match”). Moreover, the “acceptable” range of the Hamming distance (in the case of “near match”) can be soft‐programmed. The operating characteristics of the circuit are also analyzed in detail. Furthermore, these analyses are fully confirmed by simulation using the circuit analysis program HSPICE. © 2006 Wiley Periodicals, Inc. Electr Eng Jpn, 155(1): 44–51, 2006; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20223     

新型游戏机用直流伺服电动机的电路设计及其仿真建模

本文设计出了一种新型电路,从电气和机械结构上解决了能用于电路仿真软件LTspice的直流伺服电动机的电路模型。基于这个有效的电路理论模型,对实际的新型游戏手柄中所使用的直流伺服电动机驱动电路进行了优化设计。通过一系列分离电子元器件组成的模拟电路来仿真电动机的运行机理,模拟电动机的电参数和机械参数的变化,解决了仿真设计电动机的等值电路及其建模瓶颈。仿真结果验证了直流电动机模型的有效性,生产实际中既降低了产品的成本,又改善了产品的性能。     

MOS‐integrable circuitry for multi‐scroll chaotic grid realization: A SPICE‐assisted proof

A MOS‐integrable circuit realization of the class of Multi‐Scroll Grid attractor using an implementation of nonlinear transconductor is presented. The design can be seen as the MOS‐integrable circuit implementation of modified jerk equations presented in the literature (Int. J. Bifurcat. Chaos 2002; 12 (1):23–41). The proposed design of Multi‐Scroll Grid attractor is adequately supported by SPICE simulation results. Copyright © 2008 John Wiley & Sons, Ltd.     

A MODIFIED EQUIVALENT CIRCUIT FOR THREE-PHASE INDUCTION MOTORS WITH BALANCED NONSINUSOIDAL VOLTAGE SOURCE

Abstract

In this paper, the equivalent circuit model of a three-phase induction motor with balanced nonsinusoidal voltage waveform is solved by the experimental test of a 3-phase, 3-hp induction motor with a variable voltage, variable frequency (VVVF) voltage source. The parameters are calculated by analyzing the test results with statistical methods.

The performance of an induction motor with nonsinusoidal voltage source is calculated by the computer simulation based on the circuit model derived. The simulation results are compared with the laboratory test to verify the accuracy of the equivalent circuit model.     

双绕组高压发电机外部故障仿真模型

建立了双绕组高压发电机的详细电路分析数学模型。模型可以用来分析双绕组高压发电机的稳态运行、外部相间故障或接地故障。采用理论分析方法计算了高压发电机的两套三相定子绕组的自感和互感,并且以11 MW、45 kV的双绕组高压发电机为模型,给出了稳态运行和故障时的仿真结果。利用该模型可以对高压发电机的保护方案进行有效的验证或者作相应的改进。     

基于回路平衡方程和励磁电感的特高压变压器保护

谐波制动原理的变压器差动保护受谐波影响大,动作时间过长,难以满足特高压变压器保护的需求,针对此问题,提出了基于T型等效电路的特高压变压器保护方案。建立变压器T型等效电路模型,该模型不受变压器运行状态的影响,其参数能够唯一确定,并提出基于变压器等值回路平衡方程判据和等效励磁电感判据的保护方案。使用Matlab仿真工具,依据中国第一条特高压输电线路的系统参数搭建了特高压输电模型,分别仿真了特高压变压器空载投入、区外故障、区内故障和正常运行的各种工况,验证了所提出的保护方案在特高压输电系统中运用的可行性。该保护方案不受励磁涌流的影响、动作速度快、灵敏度高。     

MASH结构ADC中的自适应校正系统设计

随着大规模集成电路的快速发展,Delta-Sigma（∑-△）模数转换技术因为它的良好性能和易集成的优势,越来越受到广泛的关注和应用。本文针对实际电路相对于理想设计的性能下降来分析其原因。同时针对主要来自模拟电路的诸如实际电容的不精确匹配、放大器的有限增益等因素,通过MATLAB模型来详细分析这些模拟电路误差会对于电路性能产生的影响。本文同时提出了一种自适应校正系统,通过将LMS自适应算法应用于ADC电路,来获得对模拟电路误差的校正。并通过MATLAB分析获得理想状态、无校正系统和校正系统的性能比较来体现校正系统的实际应用价值。     

基于相量测量的输电线路故障测距新算法

提出了一种新的基于相量测量的输电线路故障测距的自适应算法,对于单回线和同杆双回线均适用.该算法利用输电线路两端的电压和电流相量并采用集中参数模型对∏型等值线路的正序参数进行了在线计算以用于故障测距,解决了线路参数在运行过程中的不确定性问题.为了实现双端测距,通过故障前后线路两端的采样数据获取突变量,并采用对称分量和六序分量分别计算了单回线和同杆双回线的等效系统阻抗.大量的EMTP仿真计算结果和实际系统数据验证结果表明,该测距算法能适应系统运行方式的变化,不受故障点过渡电阻、故障类型、故障距离等因素的影响,具有很高的测距精度.     

并联混合型电力滤波器的仿真研究

并联混合型电力滤波器能够很好地改善无源滤波器的滤波性能,实现在大功率场合下的谐波抑制和无功补偿。通过建立混合系统的单相等效电路图,分析了并联混合型电力滤波器的补偿原理和补偿特性;通过研究主电路拓扑结构,给出了主电路各个组成部分的设计方法,其中包括无源滤波器设计、耦合变压器设计、输出滤波器设计及有源滤波器控制策略设计。文章利用Matlab/Simulink构建了仿真模型,给出了仿真模型中各部分的参数,得到了仿真结果。仿真结果表明这种混合型电力滤波器可有效地改善无源滤波器的滤波性能,证明了设计方法的有效性。     

Improved analogue fault coverage estimation using probabilistic analysis

A method for fault detection probability estimation using statistical multi‐parameter circuit simulation is proposed, in order to check circuits for which double or multiple analogue measurements are utilized. Theoretical analysis for the estimation of the fault coverage is given, based on conditional probability calculations. The proposed method can be applied for both test measurement and input stimulus selection. Simulation results from the application of the method on typical analogue circuits—filter and amplifier—are given, showing a sufficient improvement over the fault coverage achieved by single measurements. Copyright © 2009 John Wiley & Sons, Ltd.     

Layout including parasitics for printed circuit boards

An automatic layout system is developed for optimal simultaneous placement of elements and equipotential nodes and routing interconnection paths that can be applied to multilayer analogue printed circuit boards (PCBs) including parasitic couplings. the objective is to minimize the influence of parasitic capacitance and inductance couplings of printed paths on performance of analogue circuits as an electrical criterion. A force model has been used to determine optimal placement where the sensitivities of network function on parasitic capacitances and inductances are the sets of weighted coefficients between forces of attractions and repulsions. the routing algorithm is a combination of topographic simulation method with minimum length connection path. the topography of predicted parasitic couplings is formed before each connection path is routed where the sensitivities of the network function on parasitic capacitances and inductances create the heights of tops. Placement and routing algorithms have been developed, programmed and compared with conventional force algorithm and the Lee algorithm. Practical results of frequency characteristics of printed circuit boards of a wide-band HF amplifier have been obtained and presented.     

基于KEIL及PROTEUS的继电控制系统功能仿真与检测

继电器接触器的工作时间不尽相同,很有可能会引发竞争冒险现象,导致控制线路不能正常工作,由此介绍了一种实用的继电控制线路功能仿真与检测方法。用KEIL及PROTEUS软件建立了继电器模型,提出了继电器动作时四个不同的延时时间。根据一个现场实例建立了继电控制线路模型,提出了接近实际线路工作状况的算法。进行了功能仿真,证明利用所建立的模型可以仿真控制线路功能并检测到竞争冒险现象。该方法简单,效果明显直观,可用于基于继电器动作的电气控制回路动作性能分析。     

基于Maxwell的永磁同步电机特性常数分析

基于磁路法求取电机特性是传统电机设计的一种基本手段。该方法涉及到磁路计算,针对该方法应用在复杂结构或异型结构电机设计时效率较低的问题,本文基于测试发电机法,采用Maxwell 2D和Maxwell circuit editor联合仿真的方法求取外转子永磁同步电机特性常数。样机试验结果表明该方法求取的电机特性常数与真实实验结果基本吻合。反电势常数仿真计算值与磁路法计算值对比,误差小于1%。对于电机性能要求较宽松的设计,可利用该方法代替理论计算求取电机特性,提高电机设计效率。