MPEG-2编码解码系统设计和调试

从理论和软件的角度讨论 Ｍ Ｐ Ｅ Ｇ２ 算法的论文已有很多,把算法作硬件实现的论述是文中的重点。在实际的硬件系统中会遇到实现上的各种问题,理论上的概念在实际的操作中有些是无法实现的。文中论述了采用硬件技术实现的一套实用化的数字电视编码和解码系统,较好地解决了系统的复杂性、可靠性和可实现性等方面的矛盾。从硬件开发的角度,对设计的调试方案作了较详细的描述。在仔细分析数字电视的系统结构的基础上,对于硬件实现中遇到的问题作了具体分析,并提出了解决的方法。在实际应用中取得了很好的效果。     

Application Specific Processor Design for H.264 Decoder with a Configurable Embedded Processor

An application specific processor for an H.264 decoder with a configurable embedded processor is designed in this research. The motion compensation, inverse integer transform, inverse quantization, and entropy decoding algorithm of H.264 decoder software are optimized. We improved the performance of the processor with instruction‐level hardware optimization, which is tailored to configurable embedded processor architecture. The optimized instructions for video processing can be used in other video compression standards such as MPEG 1, 2, and 4. A significant performance improvement is achieved with high flexibility. Experimental results show that we could achieve 300% performance for the H.264 baseline profile level 2 decoder.     

Pipelined Scheduling of Functional HW/SW Modules for Platform‐Based SoC Design

We developed a pipelined scheduling technique of functional hardware and software modules for platform‐based system‐on‐a‐chip (SoC) designs. It is based on a modified list scheduling algorithm. We used the pipelined scheduling technique for a performance analysis of an MPEG4 video encoder application. Then, we applied it for architecture exploration to achieve a better performance. In our experiments, the modified SoC platform with 6 pipelines for the 32‐bit dual layer architecture shows a 118% improvement in performance compared to the given basic SoC platform with 4 pipelines for the 16‐bit single‐layer architecture.     

A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessorfor multimedia applications

We have designed a microprocessor that is based on a single instruction multiple data stream (SIMD) architecture. It features a two-way superscalar architecture for multimedia embedded systems that need to support especially MPEG2 video decoding/encoding and 3DCG image processing. This microprocessor meets all requirements of embedded systems, including (a) MPEG2 (MP@ML) decoding and graphic processing capabilities for three-dimensional images, (b) programming flexibility, and (c) low power consumption and low manufacturing cost. High performance was achieved by enhanced parallel processing capabilities while adopting a SIMD architecture and a two-way superscalar architecture. Programming flexibility was increased by providing 170 dedicated multimedia instructions. Low power consumption was achieved by utilizing advanced process technology and power-saving circuits. The processor supports a general-purpose RISC instruction set. This feature is important, as the processor will have to work as a controller of various target systems. The processor has been fabricated by 0.21-μm CMOS four-metal technology on a 9.84×10.12 mm die. It performs 2.16 GOPS/720 MFLOPS at an operating frequency of 180 MHz, with a power consumption of 1.2 W and a power supply of 1.8 V     

一种H.264运动估计器的VLSI设计

MPEG4AVC／ITU—T H．264视频编码标准中所采用的多模式运动估计算法与传统的MPEG4、H．263 高级预测模式相比较而言，编码效率和性能都大大提高。但其诸如模式决策等问题却给运动估计器，特别是硬件运动估计器带来非常大的运算复杂度。本文提出一种H．264运动估计器硬件结构，它采用了新的模式决策算法和快速运动估计算法。仿真结果证明，这两种算法不但能使运动估计器降低其硬件实现成本，而且能减少模式决策和运动估计的时间。     

Flexible and robust packet transport for digital HDTV

The packet-oriented transport approach used in the advanced digital television (ADTV) system for terrestrial HDTV broadcast is described. ADTV achieves robust HDTV delivery on terrestrial simulcast channels via MPEG video compression, prioritization of MPEG data, and `cell-relay' type packet transport in conjunction with a two-tier physical transmission scheme. General design issues relevant to the development of the proposed transport protocol are discussed. ADTV's prioritization algorithm for partitioning MPEG-encoded video into high-priority (HP) and standard-priority (SP) bit streams is outlined. The data transport format supporting these prioritized compressed video bit streams is described. The three principal sublayers of the ADTV transport protocol are discussed in terms of specific functions, impact of system performance, and hardware implementation factors. A proof-of-concept simulation model that incorporates transport encoding and decoding functionality is outlined, and performance evaluation results are given for illustrative transmission scenarios     

MPI系统中共享内存通信技术研究

MPI是消息传递并行程序设计接口,目前已经成为主流的并行编程模式。多核处理系统的出现,使得高性能计算更加关注节点内的进程通信性能。介绍多种节点内通信协议,以及两种MPI实现（OpenMPI和MPICH2）的结构,并对其中基于共享内存的消息传递功能采用的通信协议进行了研究,最后对两者的点点通信性能测试结果进行了比较和分析同时提出了优化策略。     

A network processor‐based architecture for multi‐gigabit traffic analysis

The wide availability of cheap and effective commodity PC hardware has driven the development of versatile traffic monitoring software such as protocol analyzers, traffic characterizers and intrusion detection systems. Most of them are designed to run on general purpose architectures and are based on the well‐known libpcap API, which has rapidly become a de facto standard. Although many improvements have been applied to packet capturing software, it still suffers from several performance flaws, mainly due to the underlying hardware bottlenecks. To overcome these issues, this paper proposes a system architecture, which combines the high performance of a Network Processor card with the flexibility of software‐based solutions. It allows for removing most part of the hardware limitations exhibited by a purely PC‐based architecture, while preserving the full compliance to any software applications based on libpcap. In addition, the proposed system enables the use of monitoring applications at the wire speed, with the possibility of on‐the‐fly data processing. The system performance has been thoroughly assessed: the results show that it clearly outperforms the previous PC‐based solutions in terms of packet capturing power, while the timestamping accuracy is as good as that achieved by DAG cards. Copyright © 2009 John Wiley & Sons, Ltd.     

一种基于嵌入式的视频音频采集系统

给出了一种基于嵌入式硬件平台和Linux操作系统,采用MPEG4视频压缩标准和PCM音频标准的视频和音频采集系统的实现方案。通过对硬件和软件的设计实现了数据的实时压缩和采集。给出了整个系统的逻辑结构,并分别详细论述了硬件和软件的设计流程,着重介绍了如何将MPEG4视频流和PCM音频流保存成AVI格式以及如何实现格式转换的过程。     

Design of an MPEG-2 codec

We review the design of a single-chip MPEG-2 a/v codec, covering the design process from the MPEG specifications and system requirements to the final design. After a brief overview of MPEG-1 and MPEG-2 standards, we examine the system requirements using as an example a universal serial bus (USB)-based MPEG-2 real-time digital video recorder. Finally, we present in more detail the hardware and software architecture of a specific MPEG a/v codec     

一种MPEG2视频解码器的系统设计

对于设计像 MPEG2视频解码器的复杂系统 ,关键的难点是其系统结构的设计。文中设计了一种适合 VL SI实现的 MPEG2解码器的系统结构。它支持 MPEG2 (MP@ML)码流 ,并且兼容 MPEG1码流。为了设计和优化这个结构 ,采用硬件描述语言 VHDL 设计了系统级的 MPEG2视频解码器。此解码器在 Viewlogic系统中进行了模拟 ,并且对一些码流进行了测试验证。     

Bandwidth-efficient PON system for broad-band access and local customer Internetworking

We present a new passive optical network (PON) architecture for broad-band access and local customer networking. It provides high bandwidth efficiency for delivering both PON and customer internetworking services. The architecture separates the local optical network from the PON system, thereby enhancing security, flexibility, and allowing the use of any media access control protocol. The local customer internetworking feature is demonstrated with insignificant penalty to the overall PON system performance.     

Compiler-Based Performance Evaluation of an SIMD Processor with a Multi-Bank Memory Unit

The single instruction multiple data (SIMD) architecture is very efficient for executing arithmetic intensive programs, but frequently suffers from data-alignment problems. The data-alignment problem not only induces extra time overhead but also hinders automatic vectorization of the SIMD compiler. In this paper, we compare three on-chip memory systems, which are single-bank, multi-bank, and multi-port, for the SIMD architecture to resolve the data-alignment problems. The single-bank memory is the simplest, but supports only the aligned accesses. The multi-bank memory requires a little higher complexity, but enables the unaligned accesses and the stride accesses with a bank-conflict limitation. The multi-port memory is capable of both the unaligned and stride accesses without any restriction, but needs quite much expensive hardware. We also developed a vectorizing compiler that can conduct dynamic memory allocation and SIMD code generation. The performances of the three memory systems with our SIMD compiler are evaluated using several digital signal processing kernels and the MPEG2 encoder. The experimental results show that the multi-bank memory can carry out MPEG2 encoding 5.8 times faster, whereas the single-bank memory only achieves 2.9 times speed-up when employed in a multimedia system with a 2-issue host processor and an 8-way SIMD coprocessor. The multi-port memory obviously shows the best performance, which is however an impractical improvement over the multi-bank memory when the hardware cost is considered.     

Systolic algorithms and a memory-based design approach for a unified architecture for the computation of DCT/DST/IDCT/IDST

In this paper, an efficient design approach for a unified very large-scale integration (VLSI) implementation of the discrete cosine transform/discrete sine transform/inverse discrete cosine transform/inverse discrete sine transform based on an appropriate formulation of the four transforms into cyclic convolution structures is presented. This formulation allows an efficient memory-based systolic array implementation of the unified architecture using dual-port ROMs and appropriate hardware sharing methods. The performance of the unified design is compared to that of some of the existing ones. It is found that the proposed design provides a superior performance in terms of the hardware complexity, speed, I/O costs, in addition to such features as regularity, modularity, pipelining capability, and local connectivity, which make the unified structure well suited for VLSI implementation.     

用COTS多处理机实现红外成像跟踪系统

研究了一种基于COTS多处理器的实时红外多目标成像跟踪处理系统，详细描述了在COTS多处理器上实现的跟踪处理算法，同时给出了整个系统的软硬件框架，这种基于编程的图像处理系统具有高效，灵活的特点，修改起来非常方便，该系统自研制成功以来已进行了多次试验，取得了良好的结果。     

Very high speed and high capacity packet switching for broadbandISDN

The authors discuss and propose a very-high-speed and high-capacity packet-switching (HPS) architecture for a future broadband ISDN (integrated-services digital network). The HPS network accommodates various communication services, such as voice, high-speed data, high-speed still picture, and video services. The proposed architecture has three significant principles: a high-speed oriented simple network protocol, separation of signaling and network control from data transfer, and hardware switching. These principles provide fast- and high-throughput transmission for data packets and reliable transmission and processing for call-control packets. The HPS protocol structure is addressed, which provides high flexibility for various communications services as well as high-speed capability. A 3-Gb/s capacity and building-block-structured packet-switching system architecture, using bus- and loop-type switch fabric, is also presented     

Design and Implementation of the Ensemble Remultiplexer for DMB Service Based on Eureka‐147

A new transmission system is necessary for the Digital Multimedia Broadcasting (DMB) service in Korea. Therefore, in this paper, we propose a new architecture for the implementation of a DMB transmission system based on Eureka‐147. We describe the design and implementation of the Ensemble remultiplexer, which is essential to the proposed system for remultiplexing ETI frames and MPEG‐2 transport streams. The proposed system provides a solution with high flexibility and low cost for multimedia broadcasting service. The functions of this transmission system have been verified by using our DMB receiver and other related systems.     

IDCT IP核的VLSI结构

摘介绍了一种新型的IDCT IP核的VLSI结构，这种并行结构结合分布式算法和基于存储器的查找表，系统自顶向下分解为模块，设计出一个不需要乘法器的高性能IP核，可以实时处理MPEG2 MP@ML。     

一种高性能并行计算架构的FPGA实现

针对传统的现场可编程门阵列（Field Programmable Gate Array,FPGA）开发方法效率低、不能充分利用芯片逻辑资源等问题,提出了一种高性能并行计算架构。设计了统一的软件、硬件编程模型,并提供FPGA操作系统层级的支持,将部分可重构技术应用于硬件线程的开发,使该架构具备资源管理和复用的能力。同时还设计了软件、硬件协同开发的流程。在开发板ZC702上进行了设计验证,评估了架构的额外资源消耗情况,并以排序算法为例展示了该架构多线程设计的灵活性。     

DCT-Domain Embedded Memory Compression for Hybrid Video Coders

Hybrid video compression schemes such as MPEG2 and H.263 use an image memory for motion-compensated coding. In VLSI implementations, this image is usually stored in external RAM because of its large size. To reduce the overall system costs, we propose to compress the image by a factor of 4 to 5 before storage, which then enables embedding of the image memory on the encoder IC itself. The proposed encoder architecture remains in the DCT-domain, so motion estimation and compensation are now performed from this domain. To control and guarantee the actual storage, scalable compression is used. A hardware implementation is feasible and worthwhile compared to traditional encoders with no noticeable loss in performance.