A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-bthird-order ΔΣ modulator

A 1.1-GHz fractional-N frequency synthesizer is implemented in 0.5-μm CMOS employing a 3-b third-order ΔΣ modulator. The in-band phase noise of -92 dBc/Hz at 10-kHz offset with a spur of less than -95 dBc is measured at 900.03 MHz with a phase detector frequency of 7.994 MHz and a loop bandwidth of 40 kHz. Having less than 1-Hz frequency resolution and agile switching speed, the proposed system meets the requirements of most RF applications including multislot GSM, AMPS, IS-95, and PDC     

A CMOS monolithic ΔΣ-controlled fractional-N frequencysynthesizer for DCS-1800

A monolithic 1.8-GHz ΔΣ-controlled fractional-N phase-locked loop (PLL) frequency synthesizer is implemented in a standard 0.25-μm CMOS technology. The monolithic fourth-order type-II PLL integrates the digital synthesizer part together with a fully integrated LC VCO, a high-speed prescaler, and a 35-kHz dual-path loop filter on a die of only 2×2 mm². To investigate the influence of the ΔΣ modulator on the synthesizer's spectral purity, a fast nonlinear analysis method is developed and experimentally verified. Nonlinear mixing in the phase-frequency detector (PFD) is identified as the main source of spectral pollution in ΔΣ fractional-N synthesizers. The design of the zero-dead zone PFD and the dual charge pump is optimized toward linearity and spurious suppression. The frequency synthesizer consumes 35 mA from a single 2-V power supply. The measured phase noise is as low as -120 dBc/Hz at 600 kHz and -139 dBc/Hz at 3 MHz. The measured fractional spur level is less than -100 dBc, even for fractional frequencies close to integer multiples of the reference frequency, thereby satisfying the DCS-1800 spectral purity constraints     

A GMSK modulator using a ΔΣ frequencydiscriminator-based synthesizer

This paper describes a new transmitter architecture suitable for wideband GMSK modulation. The technique uses direct modulation of ΔΣ frequency discriminator (ΔΣFD)-based synthesizer to produce the modulated RF signal without any up-conversion. Digital equalization is used to extend the modulation data rate far beyond the synthesizer closed-loop BW. A prototype 1.9-GHz GSM transmitter was constructed consisting of a ΔΣFD-based synthesizer and a digital transmit filter. The synthesizer consists of an 0.8-μm BiCMOS ΔΣFD chip, a digital signal processor FPGA, and an off-chip D/A converter, filter, and VCO. Measured results, using 271-kbit/s GSM modulation, demonstrate data rates well in excess of the 30-kHz synthesizer closed-loop BW are possible with digital equalization. Without modulation, the synthesizer exhibits a -76-dBc spurious noise level and a close-in phase noise of -74 dBc/Hz     

A /spl Sigma/-/spl Delta/ fractional-N frequency synthesizer using a wide-band integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications

A fractional-N frequency synthesizer (FNFS) in a 0.5-/spl mu/m SiGe BiCMOS technology is implemented. In order to operate in a wide-band frequency range, a switched-capacitors bank LC tank voltage-controlled oscillator (VCO) and an adaptive frequency calibration (AFC) technique are used. The measured VCO tuning range is as wide as 600 MHz (40%) from 1.15 to 1.75 GHz with a tuning sensitivity from 5.2 to 17.5 MHz/V. A 3-bit fourth-order /spl Sigma/-/spl Delta/ modulator is used to reduce out-of-band phase noise and to meet a frequency resolution of less than 3 Hz as well as agile switching time. The experimental results show -80 dBc/Hz in-band phase noise within the loop bandwidth of 25 kHz and -129 dBc/Hz out-of-band phase noise at 400-kHz offset frequency. The fractional spurious is less than -70 dBc/Hz at 300-kHz offset frequency and the reference spur is -75 dBc/Hz. The lock time is less than 150 /spl mu/s. The proposed synthesizer consumes 19.5 mA from a single 2.8-V supply voltage and meets the requirements of GSM/GPRS/WCDMA applications.     

Design and realization of a digital ΔΣ modulator forfractional-n frequency synthesis

The basic operation of a fractional-n frequency synthesizer has been published, but to date little has been presented on the digital ΔΣ modulators which are required to drive such synthesizers. This paper provides a tutorial overview, which relates digital ΔΣ modulation to other applications of ΔΣ modulation where the literature is more complete. The paper then presents a digital ΔΣ modulator architecture which is economical and efficient and which is practical to realize with commercially available components in comparison with other possible implementations which require extensive custom very large-scale integration (VLSI). A demonstration is made of a 28-b modulator using the architecture presented, which provides a 25-MHz tuning bandwidth and <1-Hz frequency resolution. The modulator is demonstrated in an 800-MHz frequency synthesizer having phase noise of -90 dBC/Hz at a 30-kHz offset     

U波段小数分频锁相环型频率综合器

使用0.18μm1.8VCMOS工艺实现了U波段小数分频锁相环型频率综合器,除压控振荡器(VCO)的调谐电感和锁相环路的无源滤波器外,其他模块都集成在片内。锁相环采用了带有开关电容阵列(SCA)的LC-VCO实现了宽频范围,使用3阶MASHΔ-Σ调制技术进行噪声整形降低了带内噪声。测试结果表明,频率综合器频率范围达到650～920MHz;波段内偏离中心频率100kHz处的相位噪声为-82dBc/Hz,1MHz处的相位噪声为-121dBc/Hz;最小频率分辨率为15Hz;在1.8V工作电压下,功耗为22mW。     

一种高分辨率∑△小数分频频率合成器

提出了一种采用新型分频器的小数分频频率合成器。该频率合成器与传统的小数分频频率合成器相比具有稳定时间快、工作频率高和频率分辨率高的优点。设计基于TSMC0.25μm2.5V1P5MCMOS工艺,采用sig-ma-delta调制的方法实现。经测量得到该频率合器工作频率在2.400～2.850GHz之间,相位噪声低于-95dBc/Hz@100kHz,最小频率步进小于30Hz,开关时间小于50μs,满足多数无线通信系统的要求。     

使用三位三阶Δ∑调制器的集成1GHz小数频率合成器

本文实现了一个采用三位三阶Δ∑调制器的高频谱纯度集成小数频率合成器.该频率合成器采用了模拟调谐和数字调谐组合技术来提高相位噪声性能,优化的电源组合可以避免各个模块之间的相互干扰,并且提高鉴频鉴相器的线性度和提高振荡器的调谐范围.通过采用尾电流源滤波技术和减小振荡器的调谐系数,在片压控振荡器具有很低的相位噪声,而通过采用开关电容阵列,该压控振荡器达到了大约100MHz的调谐范围,该开关电容阵列由在片数字调谐系统进行控制.该频率合成器已经采用0.18μm CMOS工艺实现,仿真结果表明,该频率频率合成器的环路带宽约为14kHz,最大带内相位噪声约为-106dBc/Hz;在偏离载波频率100kHz处的相位噪声小于-120dBc/Hz,具有很高的频谱纯度.该频率合成器还具有很快的反应速度,其锁定时间约为160μs.     

全集成低噪声CMOS宽带分数分频频率综合器

设计了一款应用于CMMB数字电视广播接收的全集成低噪声宽带频率综合器。采用三阶ΣΔ调制器小数分频器完成高精度的频率输出,使用仅一个低相位噪声的宽带VCO输出频率范围覆盖900~1 600 MHz,产生的本振信号覆盖UHF的数字电视频段(470~790 MHz)。设计中的频率综合器能在所有的频道下保证环路的稳定以及最小的环路性能偏差。测试结果表明,整个频率综合器的带内相位噪声小于-85 dBc/Hz,并且带外相位噪声在1MHz时均小于-121 dBc/Hz,总的频率综合器锁定时间小于300μs。设计在UMC 0.18μm RFCMOS工艺下实现,芯片面积小于0.6 mm2,在1.8 V电源电压的测试条件下,总功耗小于22 mW。     

A 700-kHz bandwidth /spl Sigma//spl Delta/ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications

A /spl Sigma//spl Delta/ fractional-N frequency synthesizer targeting WCDMA receiver specifications is presented. Through spurs compensation and linearization techniques, the PLL bandwidth is significantly extended with only a slight increase in the integrated phase noise. In a 0.18-/spl mu/m standard digital CMOS technology a fully integrated prototype with 2.1-GHz output frequency and 35 Hz resolution has an area of 3.4 mm/sup 2/ PADs included, and it consumes 28 mW. With a 3-dB closed-loop bandwidth of 700 kHz, the settling time is only 7 /spl mu/s. The integrated phase noise plus spurs is -45 dBc for the first WCDMA channel (1 kHz to 1.94 MHz) and -65 dBc for the second channel (2.5 to 6.34 MHz) with a worst case in-band (unfiltered) fractional spur of -60 dBc. Given the extremely large bandwidth, the synthesizer could be used also for TX direct modulation over a broad band. The choice of such a large bandwidth, however, still limits the spur performance. A slightly smaller bandwidth would fulfill WCDMA requirements. This has been shown in a second prototype, using the same architecture but employing an external loop filter and VCO for greater flexibility and ease of testing.     

A 1.8-GHz Spur-Cancelled Fractional-N Frequency Synthesizer With LMS-Based DAC Gain Calibration

A 1.8-GHz wideband DeltaSigma fractional-N frequency synthesizer achieves the phase noise performance of an integer-N synthesizer using a spur-cancellation digital-to-analog converter (DAC). The DAC gain is adaptively calibrated with a least-mean-square (LMS) sign-sign correlation algorithm for better than 1% DAC and charge pump (CP) gain matching. The proposed synthesizer phase-locked loop (PLL) is demonstrated with a wide 400-kHz loop bandwidth while using a low 14.3-MHz reference clock, and offers a better phase noise and bandwidth tradeoff. Using an 8-bit gain-calibrated DAC, DeltaSigma-shaped divider ratio noise is suppressed by as much as 30 dB. The second-order DeltaSigma fractional-N PLL exhibits in-band and integrated phase noises of -98 dBc/Hz and 0.8deg. The chip, fabricated in 0.18-mum CMOS, occupies 2 mm², and consumes 29 mW at 1.8-V supply. The spur cancellation and correlation function consumes 30% additional power     

具有量化噪声抑制的小数分频器

介绍了一款用于分数分频频率综合器的具有量化噪声抑制功能的小数分频器。使用4/4.5双模预分频器,将分频步长降为0.5,使带外相位噪声性能提高6 dB。ΣΔ调制器和分频器的配合使用一种非常简单的编程方式。采用同步电路消除异步分频器的抖动。采用该分频器的频率综合器在SMIC 0.18μm RF工艺下实现,芯片面积为1.47 mm×1 mm。测试结果表明,该频率综合器可以输出1.2～2.1 GHz范围的信号。测试的带内相位噪声小于-97 dBc/Hz,在1 MHz频偏处的带外相位噪声小于-124 dBc/Hz。在1.8 V的电源电压下,消耗的电流为16 mA。     

A 2-V, 1.8-GHz BJT phase-locked loop

This paper describes the design of a bipolar junction transistor phase-locked loop (PLL) for ΣΔ fractional-N frequency-synthesis applications. Implemented in a 0.8-μm BiCMOS technology, the PLL can operate up to 1.8 GHz while consuming 225 mW of power from a single -2-V supply. The entire LC-tuned negative-resistance variable-frequency oscillator is integrated on the same chip. A differential low-voltage current-mode logic circuit configuration is used in most of the PLL's functional blocks to minimize phase jitter and achieve low-voltage operation. The multimodulus frequency divider is designed to support multibit digital modulation. The new phase and frequency detector and loop filter contain only npn transistors and resistors and thus achieve excellent resolution in phase comparison. When phase locked to a 53.4-MHz reference clock, the measured phase noise of the 16-GHz output is -91 dBc/Hz at 10-kHz offset. The frequency switching time from 1.677 to 1.797 GHz is 150 μs. Die size is 4300×4000 μm², including the passive loop filter     

一种UHF频段小数分频频率综合器设计与实现

基于130 nm CMOS工艺设计了一款特高频(UHF)频段的锁相环型小数分频频率综合器.电感电容式压控振荡器(LC VCO)片外调谐电感总值为2 nH时,其输出频率范围为1.06～1.24 GHz,调节调谐电感拓宽了频率输出范围,并利用开关电容阵列减小了压控振荡器的增益.使用电荷泵补偿电流优化了频率综合器的线性度与带内相位噪声.此外对电荷泵进行适当改进,确保了环路的稳定.测试结果表明,通过调节电荷泵补偿电流,频率综合器的带内相位噪声可优化3 dB以上,中心频率为1.12 GHz时,在1 kHz频偏处的带内相位噪声和1 MHz频偏处的带外相位噪声分别为-92.3和-120.9 dBc/Hz.最小频率分辨率为3 Hz,功耗为19.2 mW.     

A 4 GHz quadrature output fractional-N frequency synthesizer for an IR-UWB transceiver

This paper describes a 4 GHz fractional-N frequency synthesizer for a 3.1 to 5 GHz IR-UWB transceiver.Designed in a 0.18μm mixed-signal & RF 1P6M CMOS process, the operating range of the synthesizer is 3.74 to 4.44 GHz. By using an 18-bit third-order ∑-△ modulator, the synthesizer achieves a frequency resolution of 15 Hz when the reference frequency is 20 MHz. The measured amplitude mismatch and phase error between I and Q signals are less than 0.1 dB and 0.8° respectively. The measured phase noise is -116 dBc/Hz at 3 MHz offset for a 4 GHz output.Measured spurious tones are lower than -60 dBc. The settling time is within 80 μs. The core circuit conupSigmaes only 38.2 mW from a 1.8 V power supply.     

A 0.13μm CMOS △∑ fractional-N frequency synthesizer for WLAN transceivers

A fractional-N frequency synthesizer fabricated in a 0.13 μm CMOS technology is presented for the application of IEEE 802.11 b/g wireless local area network (WLAN) transceivers.A monolithic LC voltage controlled oscillator (VCO) is implemented with an on-chip symmetric inductor.The fractional-N frequency divider consists of a pulse swallow frequency divider and a 3rd-order multistage noise shaping (MASH) △ ∑ modulator with noise-shaped dithering techniques.Measurement results show that in all channels,phase noise of the synthesizer achieves -93 dBc/Hz and -118 dBc/Hz in band and out of band respectively with a phase-frequency detector (PFD) frequency of 20 MHz and a loop bandwidth of 100 kHz.The integrated RMS phase error is no more than 0.8°.The proposed synthesizer consumes 8.4 mW from a 1.2 V supply and occupies an area of 0.86 mm2.     

An agile ISM band frequency synthesizer with built-in GMSK datamodulation

In this paper, a high-resolution fractional-N RF frequency synthesizer is presented which is controlled by a fourth-order digital sigma-delta modulator. The high resolution allows the synthesizer to be digitally modulated directly at RF. A simplified digital filter which makes use of sigma-delta quantized tap coefficients is included which provides built-in GMSK pulse shaping for data transmission. Quantization of the tap coefficients to single-bit values not only simplifies the filter architecture, but the fourth-order digital sigma-delta modulator as well. The synthesizer makes extensive use of custom VLSI, with only a simple off-chip loop filter and VCO required. The synthesizer operates from a single 3-V supply, and has low power consumption. Phase noise levels are less than -90 dBc/Hz at frequency offsets within the loop bandwidth. Spurious components are less than -90 dBc/Hz over a 19.6-MHz tuning range     

UHF RFID阅读器中低噪声Σ小数频率综合器的设计

采用0.18μmRF CMOS工艺结合EPC C1G2协议和ETSI规范要求,实现了一种应用于CMOS超高频射频识别阅读器中的低噪声ΔΣ小数频率综合器。基于三位三阶误差反馈型ΔΣ解调器,采用系数重配技术,有效提高频率综合器中频段噪声性能;关键电路VCO的设计过程中采用低压差调压器技术为VCO提供稳定偏压,提高了VCO相位噪声性能。多电源供电模式下全芯片偏置电流为9.6mA,测得在中心频率频偏200kHz、1MHz处,相处噪声分别为-108dBc/Hz和-129.8dBc/Hz。     

A 1.8-GHz CMOS fractional-N frequency synthesizer with randomized multiphase VCO

A 1.8 GHz fractional-N frequency synthesizer implemented in 0.6 /spl mu/m CMOS with an on-chip multiphase voltage-controlled oscillator (VCO) exhibits no spurs resulting from phase interpolation. The proposed architecture randomly selects output phases of a multiphase VCO for fractional frequency division to eliminate spurious tones. Measured phase noise at 1.715 GHz is lower than -80 dBc/Hz within a 20 kHz loop bandwidth and -118 dBc/Hz at 1 MHz offset with no fractional spurs above -70 dBc/Hz. The synthesizer has a frequency resolution step smaller than 10 Hz. The chip consumes 52 mW at 3.3 V and occupies 3.7 mm/spl times/2.9 mm.     

数字高阶△-∑调制频率合成器的分析与实现

由小数分频频率合成器中相位累加器与数字一阶△-∑调制器的等效性出发，用ADS软件仿真证实了高阶数字△-∑调制对量化相位噪声的高通整型功能，从而有效地解决了小数分频的杂散问题。最后硬件电路实现了基于△-∑调制的小数分频跳频频率合成器，频率范围为590～1000MHz，在偏离主频10KHz时相噪优于-93．76dBc／Hz，频率分辨率可以小于100Hz，转换时间小于50μs，在跳频频率间隔1MHz时每秒可达2万跳。