共查询到20条相似文献，搜索用时 31 毫秒
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马骥祥 《国外电子测量技术》2008,27(5):36-39
低噪声放大器(简称低噪放)是射频接收前端中的重要部件。设计性能优良的低噪声放大器能够极大的提高通信系统接收机灵敏度和通信质量。本文对微波放大电路的设计方法进行了探讨,并在ADS软件界面上进行了微波窄带滤波器低噪声放大器的优化设计。 相似文献
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S. Di Pascoli L. Fanucci B. Neri D. Zito 《International Journal of Circuit Theory and Applications》2003,31(4):351-360
A new topology of bipolar low noise amplifier (LNA) for RF applications, named base coupled differential (BCD), is presented. The proposed approach is compared by simulation against most classical topologies. The BCD configuration has the key advantage to join an integrated matching on a single‐ended input with a differential output. This is done by using down‐bond wiring, so that no integrated inductors are needed. The main advantages of this new topology are a drastic area reduction and an increased linearity range (or a reduced biasing current with the same linearity) together with a noise figure (NF) and voltage supply reduction. Particularly, the BCD LNA presented in this paper has been designed for 2.44GHz frequency operation. It is characterized by a NF of 1.93dB, a voltage gain (Av) of 19.5dB, an input impedance of 50Ωa third Input‐referred Intercept Point (IIP3) of ‐7.25dBm and a dissipated power (PD) equal to 19mW. Copyright © 2003 John Wiley & Sons, Ltd. 相似文献
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Fujihiko Matsumoto Shintaro Nakamura Hiroki Wasaki Yasuaki Noguchi 《International Journal of Circuit Theory and Applications》2004,32(4):255-274
This paper presents design of linear bipolar OTAs, which are composed of two function blocks; one is an exponential‐law circuit and the other is a core cell. Multi‐tanh cells are employed as the core cell. This kind of OTA has lower power dissipation relatively to the conventional multi‐tanh cell. According as the order of the multi‐tanh core cell becomes higher, the number of circuit realization for the core cell increases. For example, we have two OTAs for the core circuit of an emitter‐coupled pair and four OTAs for the doublet core cell. Thus, we consider the generalized OTAs for an arbitrary order n of the core cell and obtain a formula to give the realization number of the linear OTAs for n. According to the formula, there must be eight OTAs in the case of n=3. All of the eight OTAs are examined. Analysis and simulation results show that the OTAs have advantage in their characteristics, such as linear input range, power dissipation, noise, and frequency response. Copyright 2004 John Wiley & Sons, Ltd. 相似文献
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《International Journal of Circuit Theory and Applications》2017,45(12):2034-2045
In this paper, a new ultra‐wideband low‐noise amplifier (LNA) is proposed. The proposed LNA has flat gain and low noise figure (NF) in the frequency range of 3.1 to 10.6 GHz. To obtain higher gain, cascode architecture is used. In this design, to have a lower NF, the noise cancellation technique applies to the cascode architecture. In addition, to have better matching at the input and output, active feedback and matching transistors are used, which also leads to better NF. To have flat gain, RLC load is used. In the proposed LNA, only one inductor is used, which leads to the smaller chip area. The proposed circuit is designed in 90 nm CMOS technology. The simulation shows NF of between 1.62 and 2.1 dB, flat gain between 11.9 and 12 dB and power consumption of 11.72 mW in the frequency range of 3.1 to 10.6 GHz. The simulation results support the theoretical predictions. Copyright © 2017 John Wiley & Sons, Ltd. 相似文献
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Francesco Centurelli Pietro Monsurrò Alessandro Trifiletti 《International Journal of Circuit Theory and Applications》2016,44(5):1039-1054
In this paper we extend the figures of merit for class AB symmetrical OTAs to the fully differential case and compare topologies from the literature. This analysis shows that the power consumption of the CMFB can have a significant role in determining the efficiency of the OTA, but on the other hand a CMFB is needed both to set the desired output common mode voltage and to improve the CMRR. We propose the complementary triode CMFB, i.e. a triode CMFB applied both at the NMOS and PMOS current mirrors, as suitable for class AB symmetrical OTAs, and show some case studies in deep submicron CMOS technology to assess the effectiveness of the proposed solution. Copyright © 2015 John Wiley & Sons, Ltd. 相似文献
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新型全集成CMOS射频接收器低噪声电源系统 总被引：2，自引：1，他引：2
针对CMOS射频接收器芯片,提出了一种新型全集成电源系统方案,相对于传统低压差线性稳压器（LDO）电源,噪声性能显著提高。在对片内模块电源域合理划分的基础上,设计了低噪声的新型电压源取代传统的带隙基准源（Bandgap）作为LDO提供参考电压,并通过对参考电压值巧妙设计,避免了使用LDO电阻反馈网络来调节输出电压,进一步减小了电阻引入的噪声。结合数字校准电路,本系统可以为片内各电路提供准确的电源电压。该设计在Smic0．18m工艺下后真结果表明,在100kHz处,新型参考电压源输出噪声为16．38nV／√Hz,片内电源输出噪声仅为21．28nV/√Hz。 相似文献
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Francesco Centurelli Pietro Monsurrò Alessandro Trifiletti 《International Journal of Circuit Theory and Applications》2019,47(4):499-512
A novel class AB operational transconductance amplifier (OTA) topology is proposed, based on a class AB flipped voltage follower. The OTA has class AB behavior, with current boosting both for the load and the compensation capacitors. It has a high gain of (gmr0)4 , obtained using a two-stage structure with cascoded stages, and is a two-stage Miller-compensated amplifier employing multipath to remove the positive zero. It has close to rail-to-rail output swing (limited by cascoding) and very low common-mode gain thanks to a replica technique (allowing the use of low-power common-mode feedback [CMFB] loops). Ninety-two decibels of gain and 176 dB of common-mode rejection ratio (CMRR) without CMFB are achieved using a 40-nm complementary metal-oxide semiconductor (CMOS) process. The OTA is used to design a low-power sample-and-hold amplifier (SHA) operating at 5 MSps, a typical application for CMOS OTAs, which has been chosen to verify the proposed circuit's performance and to show that the OTA is robust in Monte Carlo simulations under process variations and mismatches in an actual application. 相似文献
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Worapong Tangsrirat Tattaya Pukkalanun 《International Journal of Circuit Theory and Applications》2011,39(1):31-45
A versatile family of two integrator loop filter structures using current differencing transconductance amplifiers (CDTAs) and grounded capacitors is generated. The basic filter building blocks consist of current proportional blocks, current lossless integrators and a current lossy integrator based on the use of CDTAs as the major active components. It is demonstrated that the derived filter structures can realize a general class of second‐order current transfer functions. Since the resulting structures contain only CDTAs and grounded capacitors, they are general and very appropriate for integration, cascading and electronic tuning. The influences of the CDTA non‐idealities are also discussed. The functionality of the resulting filters has been verified by simulation results. Copyright © 2009 John Wiley & Sons, Ltd. 相似文献
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Kulbhushan Sharma;Ayush Kumar;Jaya Madan;Rahul Pandey; 《International Journal of Numerical Modelling》2024,37(2):e3212
Low-noise and low-voltage operation is prime requirement of an operational transconductance amplifier for low frequency applications. However, achieving low-noise operation at low supply voltages is a challenging task in CMOS technology owing to noise-power and noise-stability tradeoffs. This article outlines, the design of four differential bias self-cascode (DBSC) operational transconductance amplifiers (OTAs) working at ±0.7 V. The four design techniques namely gate driven (GD), bulk driven (BD), bulk driven quasi-floating gate (BDQFG), and gate driven quasi floating bulk (GDQFB) have been applied on DBSC OTAs. The designing aspects and performance parameters of these four OTAs such as gain, gain-bandwidth, input referred noise (IRN), settling time (ST), common mode rejection ratio (CMRR), total harmonic distortion, input impedance, transconductance, power consumption, area consumption and process/mismatch variations have been fairly compared in this work. These DBSC OTAs have been designed and simulated using a standard 0.18-μm 6M1P CMOS N-well process. The results infer GD DBSC OTA shows high CMRR of 125.83 dB. While the BD DBSC OTA consumes very low power of 0.2 μW. The BDQFG DBSC OTA shows low 1% ST of 24.83 μS. The GDQFB DBSC OTA show high transconductance (2.35 mS), high gain (64.97 dB), and low IRN (0.40 μV/√Hz at 10 Hz). The theoretical predictions for these OTAs agree with the post-layout simulations. The proposed OTAs can be used for designing various analog circuits such as programmable gain amplifiers, variable gain amplifiers, and transimpedance amplifiers for low-frequency biomedical and health care applications. 相似文献
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In this paper, we have successfully developed an intellectual parameter‐extraction methodology on the basis of a genetic algorithm (GA), involving the efficient search‐space separation and local‐minima‐convergence prevention schemes. Via an evolutionary simulation tool complemented with appropriate analytic equations, the enhanced approach has been applied to determine the significant figures‐of‐merit (FoMs), including internal quantum efficiency (ηi) as well as transparency current density (Jtr) of semiconductor lasers, minimum noise figure (NFmin) as well as associated available gain (GA,assoc) of low‐noise amplifiers (LNAs), and DC as well as AC characteristics of heterojunction bipolar transistors (HBTs). For the first time, demonstrated FoM‐extraction results, which coincide well with the actually measured data, for state‐of‐the‐art InGaAs quantum‐well lasers, advanced SiGe LNAs, and abrupt ZnSe/Ge/GaAs HBTs are simultaneously presented to validate this multi‐parameter analysis and robust optimization. Copyright © 2011 John Wiley & Sons, Ltd. 相似文献
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Yiming Yu Yunqiu Wu Chenxi Zhao Huihua Liu Yongling Ban Kai Kang 《International Journal of Numerical Modelling》2020,33(3):e2576
A V-band low-noise amplifier (LNA) employing a Gm-boosting technique is presented in this paper. With the transformers, which are applied between the adjacent stages, the transconductances of the following transistors are boosted. Thus, the gain of the circuit is effectively enhanced. The noise figure (NF) is also decreased with the technique. Utilizing a commercial 65-nm CMOS technology, the LNA is demonstrated. The measurement results show that the LNA achieves a maximum gain of 17.4 dB at 57.1 GHz with 10.9-GHz 3-dB gain bandwidth. The measured NF of the LNA is from 3.95 dB to 4.6 dB at 53 to 64 GHz. The tested input 1-dB gain compression point (IP1dB) is −14.2 dBm at 57 GHz. The DC power consumption is only 10 mW with 1-V power supply. The chip area is only 0.255 mm2 with all testing pads. 相似文献
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Soorena Zohoori;Ahmad Hosseini;Mehrdad Amirkhan Dehkordi;Seyed Mehdi Mirsanei; 《International Journal of Circuit Theory and Applications》2024,52(6):3066-3080
The present study is devoted to articulating a modified folded-cascode circuit, to make folded-cascode structures an attractive configuration as a transimpedance amplifier (TIA) for being employed in Giga-bit per second optical communication receiver systems. Giga-bps communication receivers are highly necessitating circuits to isolate the input parasitic capacitance of the photodiode. The present modification makes folded cascodes comparable to the famous regulated cascode (RGC) structures by isolating this parasitic capacitor almost by the same quantity. The system is shown to be capable of operating at 2.5 Gbps up to 8 Gbps data rate with a fixed bandwidth. The paper analyzes and evaluates the designed circuit mathematically, and the obtained simulated results from Cadence using TSMC 65 nm CMOS validate the suitability of the modified circuit as a TIA. 相似文献
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Stanislaw Szczepanski Bogdan Pankiewicz Slawomir Koziel Marek Wojcikowski 《International Journal of Circuit Theory and Applications》2015,43(11):1671-1686
A CMOS circuit realization of a highly linear multiple‐output differential operational transconductance amplifier (OTA) has been proposed. The presented approach exploits a differential pair as an input stage with both the gate and the bulk terminals as signal ports. For the proposed OTA, improved linearity is obtained by means of the active‐error feedback loop operating at the bulk terminals of the input stage. SPICE simulations of the OTA show that, for 0.35 µm AMS process, total harmonic distortion at 1.36Vpp is less than 1% with dynamic range equal to 60.1 dB at power consumption of 276 μW from 3.3 V supply. As an example, both single output and dual differential OTAs are used to design third‐order elliptic low‐pass filters. The cut‐off frequency of the filters is 1 MHz. The power consumption of the OTA‐C filter utilizing the dual output differential OTA is reduced to 1.24 mW in comparison to 2.2 mW consumed by the single output differential OTA‐C filter counterpart. Copyright © 2014 John Wiley & Sons, Ltd. 相似文献
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Faizan Ul Haq Kim B Östman Mikko Englund Kari Stadius Marko Kosunen Kimmo Koli Jussi Ryynänen 《International Journal of Circuit Theory and Applications》2018,46(8):1427-1442
This paper presents an integrated wideband radio frequency front end with improved blocker resilience achieved through selective voltage attenuation at both input and output nodes of the low noise amplifier (LNA). The architecture differs from traditional LNA architectures where blockers are only attenuated at LNA output node. The proposed dual attenuation is attained by designing a low intrinsic input impedance common‐gate common‐source LNA with capacitive feedback, together with an N‐path filtering load. The capacitive feedback across the LNA ensures that the selective N‐path filtering profile at the LNA output is transferred to the LNA input nodes creating a selective input impedance. Consequently, the achieved front‐end input impedance is low at blocker frequencies and matched to the source impedance at the desired frequencies, creating the desired voltage attenuation for blockers. Further, a detailed theoretical analysis of proposed architecture is presented, which leads to clear design guidelines. Evaluated in a 28‐nm fully depleted silicon‐on‐insulator complementary metal oxide semiconductor (CMOS) process, front end is designed for wideband operation from 0.7 to 2.7 GHz. It consumes 11‐mA current from a 1‐V supply (excluding local oscillator (LO) buffering) and possesses a maximum noise figure of 5.1 dB. The front end demonstrates an out‐of‐band blocker compression point of ?1.5 dBm and out‐of‐band IIP3 of +14 dBm at a 100‐MHz offset from LO frequency. In comparison with a traditional common‐gate common‐source LNA‐based front end with wideband input impedance matching, the proposed front end achieves 3.5‐dB improvement in the blocker compression point at a 100‐MHz offset from LO. 相似文献
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Tomasz Kulej 《International Journal of Circuit Theory and Applications》2015,43(2):187-204
A new 0.5‐V bulk‐driven operational transconductance amplifier (OTA), designed in 50 nm CMOS technology, is presented in the paper. The circuit is characterized by improved linearity and dynamic range obtained for MOS devices operating in moderate inversion region. Some basic applications of the OTA such as a voltage integrator and a second‐order low‐pass filter have also been described. The filter is compared to other low‐voltage filters presented in the literature. Copyright © 2013 John Wiley & Sons, Ltd. 相似文献
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Domenico Zito 《International Journal of Circuit Theory and Applications》2009,37(9):1008-1018
A novel low‐power receiver topology for radio‐frequency and microwave applications is presented. The proposed solution exploits a simple connection between the low‐noise amplifier and the subsequent mixer, which is realized by means of a high‐value resistor and a current mirror, achieving low noise and high linearity performance with an extremely low power consumption. The criteria for its optimal design are derived in order to accomplish the main trade‐offs among noise figure (NF), linearity, and current consumption performance. As a case of study, the new topology has been designed in the case of I/Q direct conversion receiver for IEEE 802.15.4 standard (ZigBee) applications at 2.45 GHz. The receiver exhibits a NF of 8.7 dB, 50Ω input impedance, a voltage gain of 26 dB, an input‐referred third‐order intercept point of ?13 dBm, and a power consumption of 8.6 mW, which represent one of the best performance trade‐offs obtained in the literature. Copyright © 2008 John Wiley & Sons, Ltd. 相似文献
